DuneNvme 1.0.2 This is a simple NVMe test environment that allows experimentation with the low level PCIe NVMe interfaces as available on a Xilinx FPGA environment. |
This module passes register access signals across a clock domain. More...
![](classRegAccessClockConvertor.png)
Entities | |
Behavioral | architecture |
Libraries | |
ieee | |
unisim | |
work |
Use Clauses | |
std_logic_1164 | |
numeric_std | |
vcomponents | |
NvmeStoragePkg | Package <NvmeStoragePkg> |
NvmeStorageIntPkg | Package <NvmeStorageIntPkg> |
Ports | ||
clk1 | in | std_logic |
The interface clock line. | ||
reset1 | in | std_logic |
The active high reset line. | ||
regWrite1 | in | std_logic |
Enable write to register. | ||
regRead1 | in | std_logic |
Enable read from register. | ||
regAddress1 | in | unsigned ( 5 downto 0 ) |
Register to read/write. | ||
regDataIn1 | in | std_logic_vector ( 31 downto 0 ) |
Register write data. | ||
regDataOut1 | out | std_logic_vector ( 31 downto 0 ) |
Register contents. | ||
clk2 | in | std_logic |
The interface clock line. | ||
reset2 | in | std_logic |
The active high reset line. | ||
regWrite2 | out | std_logic |
Enable write to register. | ||
regRead2 | out | std_logic |
Enable read from register. | ||
regAddress2 | out | unsigned ( 5 downto 0 ) |
Register to read/write. | ||
regDataIn2 | out | std_logic_vector ( 31 downto 0 ) |
Register write data. | ||
regDataOut2 | in | std_logic_vector ( 31 downto 0 ) |
Register contents. |
Detailed Description
This module passes register access signals across a clock domain.
- Date
- 2020-08-06
- Version
- 1.0.1
This is a very simple, low utilisation, clock domain crossing unit for the register interface. It is designed to work with asynchronous clocks of the same frequency. It delays the write and read signals by 1 cycle from the address and data transitions to make sure all bits are stable before the actual register write. It also holds the read and write signals for and extra cycle to guarantee they pass through. For reads you need to wait 7 cycles for the read data to be latched and sent across the clock domains. Note this module requires appropriate timing constraints for the CDC applied. This would normally be a set_max_delay or set_false_path constraint on the timing to the sendCdcReg1 and recvCdcReg1 registers.
- Copyright
- 2020 Beam Ltd, Apache License, Version 2.0 Copyright 2020 Beam Ltd Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.
The documentation for this class was generated from the following file:
- /src/dune/source/DuneNvme/src/RegAccessClockConvertor.vhd
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