DuneNvme 1.0.2 This is a simple NVMe test environment that allows experimentation with the low level PCIe NVMe interfaces as available on a Xilinx FPGA environment. |
NvmeStorageIntPkg Package Reference
System constants. More...
Package Body >> NvmeStorageIntPkgFunctions | |
std_logic_vector | to_stl ( v: in integer , b: in integer ) |
Generaly useful functions. | |
std_logic_vector | to_stl ( v: in unsigned , b: in integer ) |
std_logic_vector | to_stl ( v: in unsigned ) |
integer | log2 ( v: in integer ) |
integer | log2_roundup ( v: in integer ) |
std_logic_vector | concat ( v: in std_logic , n: in integer ) |
std_logic_vector | zeros ( n: in integer ) |
unsigned | zeros ( n: in integer ) |
std_logic_vector | ones ( n: in integer ) |
unsigned | truncate ( v: in unsigned , n: in integer ) |
std_logic_vector | extend ( v: in std_logic_vector , n: in integer ) |
std_logic_vector | keepBits ( numWords: in unsigned ) |
std_logic_vector | keepBits ( numWords: in integer ) |
std_logic_vector | to_stl ( v: in PcieRequestHeadType ) |
PcieRequestHeadType | to_PcieRequestHeadType ( v: in std_logic_vector ) |
PcieRequestHeadType | set_PcieRequestHeadType ( requesterId: in integer request: in integer address: in integer count: in integer tag: in integer ) |
std_logic_vector | to_stl ( v: in PcieReplyHeadType ) |
PcieReplyHeadType | to_PcieReplyHeadType ( v: in std_logic_vector ) |
PcieReplyHeadType | set_PcieReplyHeadType ( requesterId: in integer status: in integer address: in integer count: in integer tag: in integer ) |
std_logic_vector | to_stl ( v: in NvmeRequestHeadType , word: in integer ) |
NvmeReplyHeadType | to_NvmeReplyHeadType ( v: in std_logic_vector ) |
Procedures | |
axisConnect( signal streamOut: inout AxisStreamType ,signal streamIn: inout AxisStreamType ) | |
axisConnect( signal streamOut: out AxisType signal ready: in std_logic signal streamIn: inout AxisStreamType ) | |
axisConnect( signal streamOut: inout AxisStreamType signal streamIn: in AxisType signal ready: out std_logic ) |
Libraries | |
ieee | |
work |
Use Clauses | |
std_logic_1164 | |
numeric_std | |
NvmeStoragePkg | Package <NvmeStoragePkg> |
Constants | |
NvmeQueueNum | integer := 16 |
The number of queue entries. Has to be greater than NvmeWriteNum and number of trim requests. | |
NvmeWriteNum | integer := 8 |
The number of concurrent data write's. | |
PcieMaxPayloadSize | integer := 32 |
The maximum Pcie packet size in 32bit DWords. | |
AxisStreamDataWidth | integer := 128 |
AxisStreamKeepWidth | integer := 4 |
AxisStreamInput | AxisStreamType := ( ' 0 ' , ' Z ' , ' Z ' , ( others = > ' Z ' ) , ( others = > ' Z ' ) ) |
AxisStreamOutput | AxisStreamType := ( ' Z ' , ' 0 ' , ' 0 ' , ( others = > ' 0 ' ) , ( others = > ' 0 ' ) ) |
AxisStreamInOut | AxisStreamType := ( ' Z ' , ' Z ' , ' Z ' , ( others = > ' Z ' ) , ( others = > ' Z ' ) ) |
AxisStreamSink | AxisStreamType := ( ' 1 ' , ' Z ' , ' Z ' , ( others = > ' Z ' ) , ( others = > ' Z ' ) ) |
Types | |
AxisStreamArrayType | array ( natural range <> ) of AxisStreamType |
Subtypes | |
RegReturnType | std_logic_vector ( 31 downto 0 ) |
Records | |
AxisStreamType | |
ready | std_logic |
valid | std_logic |
last | std_logic |
data | std_logic_vector ( AxisStreamDataWidth - 1 downto 0 ) |
keep | std_logic_vector ( AxisStreamKeepWidth- 1 downto 0 ) |
PcieRequestHeadType | |
PCIe request packet head. This uses the Xilinx Pcie Gen3 IP Pcie packet header style. | |
reply | std_logic |
This is a reply header. | |
address | unsigned ( 31 downto 0 ) |
tag | unsigned ( 7 downto 0 ) |
request | unsigned ( 3 downto 0 ) |
count | unsigned ( 10 downto 0 ) |
requesterId | unsigned ( 15 downto 0 ) |
PcieReplyHeadType | |
PCIe reply packet head. This uses the Xilinx Pcie Gen3 IP Pcie packet header style. | |
byteCount | unsigned ( 12 downto 0 ) |
error | unsigned ( 3 downto 0 ) |
address | unsigned ( 11 downto 0 ) |
status | unsigned ( 2 downto 0 ) |
NvmeRequestHeadType | |
Nvme request queue entry. | |
opcode | unsigned ( 15 downto 0 ) |
cid | unsigned ( 15 downto 0 ) |
namespace | unsigned ( 31 downto 0 ) |
cdw10 | unsigned ( 31 downto 0 ) |
cdw11 | unsigned ( 31 downto 0 ) |
cdw12 | unsigned ( 31 downto 0 ) |
cdw13 | unsigned ( 31 downto 0 ) |
cdw14 | unsigned ( 31 downto 0 ) |
cdw15 | unsigned ( 31 downto 0 ) |
NvmeReplyHeadType | |
Nvme reply queue entry. | |
dw0 | unsigned ( 31 downto 0 ) |
sqptr | unsigned ( 15 downto 0 ) |
sqid | unsigned ( 15 downto 0 ) |
status | unsigned ( 14 downto 0 ) |
RegAccessType | |
Simple register access. | |
write | std_logic |
address | unsigned ( 7 downto 0 ) |
writeData | std_logic_vector ( 31 downto 0 ) |
Detailed Description
System constants.
This package provides definitions for the NvmeStorage system internals.
- Date
- 2020-03-18
- Version
- 1.0.0
Included are useful functions, core system types and overal system parameters.
- Copyright
- 2020 Beam Ltd, Apache License, Version 2.0 Copyright 2020 Beam Ltd Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.
Member Data Documentation
◆ AxisStreamDataWidth
| Constant |
AXI Stream interface This implemtation of Axis makes it easy to pass and manipulate streams in VHDL. It's not nice as it uses inout to acheive this as VHDL is very limited when using records especialy as module in's and out's. However this scheme simplifies the code syntax a lot at the expense of less in/out validation in the initial compilation stages.
The documentation for this class was generated from the following file:
- /src/dune/source/DuneNvme/src/NvmeStorageIntPkg.vhd
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