Behavioral Architecture Reference

Processes
PROCESS_36	( clk2 )
	The send process.
PROCESS_37	( clk1 )
	The receive process.

Constants
TCQ	time := 1 ns
SigSendWidth	integer := 2 + regAddress1 ' length+ regDataIn1 ' length
SigRecvWidth	integer := 32

Subtypes
SigSendType	std_logic_vector ( SigSendWidth- 1 downto 0 )
SigRecvType	std_logic_vector ( SigRecvWidth- 1 downto 0 )

Signals
regWrite1Delayed	std_logic := ' 0 '
regWrite1Delayed1	std_logic := ' 0 '
regRead1Delayed	std_logic := ' 0 '
regRead1Delayed1	std_logic := ' 0 '
sendCdcReg0	SigSendType := ( others = > ' 0 ' )
sendCdcReg1	SigSendType := ( others = > ' 0 ' )
sendCdcReg2	SigSendType := ( others = > ' 0 ' )
recvCdcReg0	SigRecvType := ( others = > ' 0 ' )
recvCdcReg1	SigRecvType := ( others = > ' 0 ' )
recvCdcReg2	SigRecvType := ( others = > ' 0 ' )

Attributes
keep	string
async_reg	string
keep	sendCdcReg0 : signal is " true "
keep	sendCdcReg1 : signal is " true "
keep	sendCdcReg2 : signal is " true "
keep	recvCdcReg0 : signal is " true "
keep	recvCdcReg1 : signal is " true "
keep	recvCdcReg2 : signal is " true "
async_reg	sendCdcReg1 : signal is " true "
async_reg	sendCdcReg2 : signal is " true "
async_reg	recvCdcReg1 : signal is " true "
async_reg	recvCdcReg2 : signal is " true "

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The documentation for this class was generated from the following file:

• /src/dune/source/DuneNvme/src/RegAccessClockConvertor.vhd