Behavioral Architecture Reference

Functions
integer	queueNext ( pos: in integer )

Processes
PROCESS_12	( clk )
	Host requests including register access.
PROCESS_13	( clk )
	Process host request packets.
PROCESS_14	( clk )
	Process queued requests.

Constants
TCQ	time := 1 ns
NumQueue	integer := 16
	Number of queue entries.
RegWidth	integer := 32
NumWordsRead	integer := BlockSize / 4
	Number of 32bit Dwords in a block.

Types
ReqStateType	( REQSTATE_IDLE , REQSTATE_WRITE , REQSTATE_READ , REQSTATE_REPLY )
StateType	( STATE_IDLE , STATE_READ_QUEUE_START , STATE_READ_QUEUE , STATE_QUEUE_REPLY_HEAD , STATE_QUEUE_REPLY_DATA , STATE_READ_DATA_START , STATE_READ_DATA_RECV_START , STATE_READ_DATA_RECV , STATE_WRITE_DATA_START , STATE_WRITE_DATA_HEAD , STATE_WRITE_DATA , STATE_REPLY_QUEUE )
QueueRequestType	( 0 to 15 ) std_logic_vector ( 31 downto 0 )

Subtypes
RegDataType	std_logic_vector ( RegWidth- 1 downto 0 )

Signals
reqState	ReqStateType := REQSTATE_IDLE
hostRequestHead	PcieRequestHeadType
hostRequestHead1	PcieRequestHeadType := set_PcieRequestHeadType ( 0 , 0 , 0 , 0 , 0 )
hostReplyHead	PcieReplyHeadType := set_PcieReplyHeadType ( 0 , 0 , 0 , 0 , 0 )
hostReplyHead1	PcieReplyHeadType := set_PcieReplyHeadType ( 0 , 0 , 0 , 0 , 0 )
reg_pci_command	RegDataType := ( others = > ' 0 ' )
reg_admin_queue	RegDataType := ( others = > ' 0 ' )
reg_io1_queue	RegDataType := ( others = > ' 0 ' )
reg_io2_queue	RegDataType := ( others = > ' 0 ' )
queueAdminIn	integer range 0 to NumQueue - 1 := 0
queueAdminOut	integer range 0 to NumQueue - 1 := 0
queueWriteIn	integer range 0 to NumQueue - 1 := 0
queueWriteOut	integer range 0 to NumQueue - 1 := 0
queueReadIn	integer range 0 to NumQueue - 1 := 0
queueReadOut	integer range 0 to NumQueue - 1 := 0
state	StateType := STATE_IDLE
queue	integer range 0 to NumQueue - 1 := 0
queue_pos	integer range 0 to NumQueue - 1 := 0
nvmeReply1	AxisStreamType
	Nvme reply stream for valid replies.
nvmeRequestHead	PcieRequestHeadType
nvmeReply1Head	PcieReplyHeadType
regData	RegDataType := ( others = > ' 0 ' )
streamNum	integer := 1
count	unsigned ( 10 downto 0 )
chunkCount	unsigned ( 10 downto 0 )
queueRequest	QueueRequestType := ( others = > ( others = > ' 0 ' ) )
queueRequestPos	integer := 0
waitingForReply	std_logic := ' 0 '
data	std_logic_vector ( 127 downto 0 )
readData	unsigned ( 127 downto 0 )

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The documentation for this class was generated from the following file:

• /src/dune/source/DuneNvme/src/NvmeSim.vhd