| DuneNvme 1.0.2 This is a simple NVMe test environment that allows experimentation with the low level PCIe NVMe interfaces as available on a Xilinx FPGA environment. |
Constants | Components | Subtypes | Types | Signals | Procedures | Functions | Processes | Instantiations
Behavioral Architecture Reference
Functions | |
| unsigned | doorbellAddress ( queueNum: in integer , reply: in integer ) |
Processes | |
| PROCESS_6 | ( clk ) |
| Process requests. | |
Procedures | |
| queueAddress( address: unsigned ,signal ramAddress: out unsigned ) | |
| Given Pcie address calculate RAM address. | |
| queueAddressStart( signal queueArray: inout QueuePosArrayType queueNum: unsigned signal address: out unsigned ) | |
| Sets the RAM access address from last queue position and updates queue position. | |
| queueOutIncrement( signal queueArray: inout QueuePosArrayType , queueNum: unsigned ) | |
Components | |
| Ram | <Entity Ram> |
| The data width of the RAM in bits. | |
Constants | |
| TCQ | time := 1 ns |
| NUM_QUEUES | integer := 4 |
| RAM_SIZE | integer := NUM_QUEUES* NumQueueEntries * 4 |
| Only write to request queues are stored. | |
| ADDRESS_WIDTH | integer := log2 ( RAM_SIZE ) |
Types | |
| QueuePosArrayType | ( 0 to NUM_QUEUES- 1 ) QueuePosType |
| StateType | ( STATE_IDLE , STATE_WRITE , STATE_READHEAD1 , STATE_READHEAD2 , STATE_READDATA , STATE_WRITE_QUEUE , STATE_SEND_DOORBELL_HEAD , STATE_SEND_DOORBELL_POS , STATE_REPLY_RDATA , STATE_REPLY_SHEAD , STATE_REPLY_SDATA , STATE_SEND_RDOORBELL_HEAD ) |
Subtypes | |
| QueueNumRange | integer range 17 downto 16 |
| The active high reset line. | |
| QueuePosType | unsigned ( log2 ( NumQueueEntries ) - 1 downto 0 ) |
Signals | |
| state | StateType := STATE_IDLE |
| ramWriteEnable | std_logic := ' 0 ' |
| ramReadEnable | std_logic := ' 0 ' |
| ramAddressWrite | unsigned ( ADDRESS_WIDTH- 1 downto 0 ) := ( others = > ' 0 ' ) |
| ramAddressRead | unsigned ( ADDRESS_WIDTH- 1 downto 0 ) := ( others = > ' 0 ' ) |
| ramReadData | std_logic_vector ( 127 downto 0 ) := ( others = > ' 0 ' ) |
| data1 | std_logic_vector ( 127 downto 0 ) := ( others = > ' 0 ' ) |
| queueIn | integer range 0 to NUM_QUEUES- 1 := 0 |
| queueInArrayPos | QueuePosArrayType := ( others = > ( others = > ' 0 ' ) ) |
| queueOutArrayPos | QueuePosArrayType := ( others = > ( others = > ' 0 ' ) ) |
| requestHead | PcieRequestHeadType |
| requestHead1 | PcieRequestHeadType |
| replyHead | PcieReplyHeadType |
| doorbellReqHead | PcieRequestHeadType |
Instantiations | |
| queuemem0 | Ram <Entity Ram> |
The documentation for this class was generated from the following file:
- /src/dune/source/DuneNvme/src/NvmeQueues.vhd
Generated by
1.8.15