DuneNvme 1.0.2 This is a simple NVMe test environment that allows experimentation with the low level PCIe NVMe interfaces as available on a Xilinx FPGA environment. |
Behavioral Architecture Reference
Processes | |
PROCESS_15 | ( clk ) |
PROCESS_16 | ( clk ) |
Implement input block dropping on request. |
Components | |
NvmeStorageUnit | <Entity NvmeStorageUnit> |
Generate simulation core. | |
AxisDataConvertFifo | <Entity AxisDataConvertFifo> |
nvme PCIe RX minus lanes | |
NvmeStreamMux | <Entity NvmeStreamMux> |
The Fifo size in bytes. |
Constants | |
TCQ | time := 1 ns |
Nvme1 replies output stream. |
Signals | |
reset_l | std_logic := ' 0 ' |
wvalid_delay | std_logic := ' 0 ' |
regRead_delay | std_logic := ' 0 ' |
rvalid_delay | unsigned ( 8 downto 0 ) := ( others = > ' 0 ' ) |
hostSend0 | AxisStreamType |
hostRecv0 | AxisStreamType |
data0 | AxisStreamType := AxisStreamOutput |
nvme0Send | AxisStreamType |
nvme0Recv | AxisStreamType |
data1 | AxisStreamType := AxisStreamOutput |
nvme1Send | AxisStreamType |
nvme1Recv | AxisStreamType |
regControl | std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' ) |
Control register. | |
regWrite | std_logic := ' 0 ' |
Enable write to register. | |
regRead | std_logic := ' 0 ' |
Enable read from register. | |
regAddress | unsigned ( 9 downto 0 ) := ( others = > ' 0 ' ) |
Register to read/write. | |
regWrite0 | std_logic := ' 0 ' |
regWrite1 | std_logic := ' 0 ' |
readNvme1 | std_logic := ' 0 ' |
regDataOut0 | std_logic_vector ( 31 downto 0 ) |
regDataOut1 | std_logic_vector ( 31 downto 0 ) |
enabled_n | std_logic := ' 0 ' |
dataSelect | std_logic := ' 0 ' |
dataIn_ready_l | std_logic := ' U ' |
dataIn0 | AxisDataStreamType |
dataIn0_ready | std_logic := ' U ' |
dataIn1 | AxisDataStreamType |
dataIn1_ready | std_logic := ' U ' |
dataEnabledOut0 | std_logic := ' U ' |
dataEnabledOut1 | std_logic := ' U ' |
dropCount | integer range 0 to NumBlocksDrop := 0 |
dropBlocks | std_logic := ' 0 ' |
regBlocksLost | unsigned ( 31 downto 0 ) := ( others = > ' 0 ' ) |
Instantiations | |
dataconvert0 | AxisDataConvertFifo <Entity AxisDataConvertFifo> |
Store incomming block for Nvme0. | |
dataconvert1 | AxisDataConvertFifo <Entity AxisDataConvertFifo> |
Store incomming block for Nvme1. | |
nvmestreammux0 | NvmeStreamMux <Entity NvmeStreamMux> |
Multiplex/de-multiplex Pcie packet streams to the two NvmeStorageUnits. | |
nvmestorageunit0 | NvmeStorageUnit <Entity NvmeStorageUnit> |
Nvme0 storage unit. | |
nvmestorageunit1 | NvmeStorageUnit <Entity NvmeStorageUnit> |
Nvme1 storage unit. |
Member Data Documentation
◆ nvmestorageunit0
| Instantiation |
Nvme0 storage unit.
The Pcie hardblock block to use
◆ nvmestorageunit1
| Instantiation |
Nvme1 storage unit.
The Pcie hardblock block to use
The documentation for this class was generated from the following file:
- /src/dune/source/DuneNvme/src/NvmeStorage.vhd
Generated by
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