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Dune NVMe Storage Support
DuneNvme  1.0.2
This is a simple NVMe test environment that allows experimentation with the low level PCIe NVMe interfaces as available on a Xilinx FPGA environment.
Fifo Entity Reference

This module provides a simple, single clocked FWFT FIFO. More...

Inheritance diagram for Fifo:
AxisDataConvertFifo NvmeRead NvmeWrite NvmeStorage NvmeStorageUnit NvmeStorageUnit DuneNvmeTestOsperoTop DuneNvmeTestTop NvmeStorage NvmeStorage DuneNvmeTestOsperoTop DuneNvmeTestTop DuneNvmeTestOsperoTop DuneNvmeTestTop

Entities

Behavioral  architecture
 

Libraries

ieee 
unisim 
work 

Use Clauses

std_logic_1164 
numeric_std 
vcomponents 
NvmeStoragePkg  Package <NvmeStoragePkg>
NvmeStorageIntPkg  Package <NvmeStorageIntPkg>

Generics

Simulate  boolean := False
 Simulation.
DataWidth  integer := 128
 The data width of the Fifo in bits.
Size  integer := 2
 The size of the fifo.
NearFullLevel  integer := 0
 Nearly full level, 0 disables.
RegisterOutputs  boolean := False
 Register the outputs.

Ports

clk   in   std_logic
  The interface clock line.
reset   in   std_logic
  The active high reset line.
nearFull   out   std_logic
  Fifo is nearly full.
inReady   out   std_logic
  Fifo is ready for input.
inValid   in   std_logic
  Data input is valid.
inData   in   std_logic_vector ( DataWidth - 1 downto 0 )
  The input data.
outReady   in   std_logic
  The external logic is ready for output.
outValid   out   std_logic
  The data output is available.
outData   out   std_logic_vector ( DataWidth - 1 downto 0 )
  The output data.

Detailed Description

This module provides a simple, single clocked FWFT FIFO.

Author
Terry Barnaby (terry.nosp@m..bar.nosp@m.naby@.nosp@m.beam.nosp@m..ltd..nosp@m.uk)
Date
2020-08-11
Version
1.0.1

This is a simple single clock first word fall through FIFO. Its data storage memory will be implemented in registers for small Fifo's and in BlockRAM for larger Fifos the Size parameter defining the depth of the Fifo. The data width is defined by the DataWidth parameter. It has a programmable nearFull output that can be enabled by setting the NearFullLevel parameter to the appropriate Fifo level. The RegisterOutputs parameter provides registered output of the data for better system timing at the expense of one cycle of latency.


The documentation for this class was generated from the following file:
  • /src/dune/source/DuneNvme/src/Fifo.vhd