DuneNvme 1.0.2 This is a simple NVMe test environment that allows experimentation with the low level PCIe NVMe interfaces as available on a Xilinx FPGA environment. |
This is the main top level NvmeStorage module that provides access to the NVMe devices over the Axil bus and Axis request/reply streams. More...
![](classNvmeStorage.png)
Entities | |
Behavioral | architecture |
Libraries | |
ieee | |
unisim | |
work |
Use Clauses | |
std_logic_1164 | |
numeric_std | |
vcomponents | |
NvmeStoragePkg | Package <NvmeStoragePkg> |
NvmeStorageIntPkg | Package <NvmeStorageIntPkg> |
Generics | |
Simulate | boolean := False |
Generate simulation core. | |
Platform | string := " Ultrascale " |
The underlying target platform. | |
ClockPeriod | time := 4 ns |
Clock period for timers (250 MHz) | |
BlockSize | integer := NvmeStorageBlockSize |
System block size. | |
NumBlocksDrop | integer := 2 |
The number of blocks to drop at a time. | |
UseConfigure | boolean := False |
The module configures the Nvme's on reset. | |
NvmeBlockSize | integer := 512 |
The NVMe's formatted block size. | |
NvmeTotalBlocks | integer := 104857600 |
The total number of 4k blocks available (400 G) | |
NvmeRegStride | integer := 4 |
The doorbell register stride. |
Ports | ||
clk | in | std_logic |
The interface clock line. | ||
reset | in | std_logic |
The active high reset line. | ||
axilIn | in | AxilToSlaveType |
Axil bus input signals. | ||
axilOut | out | AxilToMasterType |
Axil bus output signals. | ||
hostSend | in | AxisType |
Host request stream. | ||
hostSend_ready | out | std_logic |
Host request stream ready line. | ||
hostRecv | out | AxisType |
Host reply stream. | ||
hostRecv_ready | in | std_logic |
Host reply stream ready line. | ||
dataDropBlocks | in | std_logic |
If set to '1' drop complete input blocks and account for the loss. | ||
dataEnabledOut | out | std_logic |
Indicates that data ingest is enabled. | ||
dataIn | in | AxisDataStreamType |
Raw data input stream. | ||
dataIn_ready | out | std_logic |
Raw data input ready. | ||
nvme0_clk | in | std_logic |
Nvme0 external clock. | ||
nvme0_clk_gt | in | std_logic |
Nvme0 external GT clock. | ||
nvme0_reset_n | out | std_logic |
Nvme0 reset output to reset NVMe device. | ||
nvme0_exp_txp | out | std_logic_vector ( 3 downto 0 ) |
Nvme0 PCIe TX plus lanes. | ||
nvme0_exp_txn | out | std_logic_vector ( 3 downto 0 ) |
Nvme0 PCIe TX minus lanes. | ||
nvme0_exp_rxp | in | std_logic_vector ( 3 downto 0 ) |
Nvme0 PCIe RX plus lanes. | ||
nvme0_exp_rxn | in | std_logic_vector ( 3 downto 0 ) |
Nvme0 PCIe RX minus lanes. | ||
nvme1_clk | in | std_logic |
Nvme1 external clock. | ||
nvme1_clk_gt | in | std_logic |
Nvme1 external GT clock. | ||
nvme1_reset_n | out | std_logic |
Nvme1 reset output to reset NVMe device. | ||
nvme1_exp_txp | out | std_logic_vector ( 3 downto 0 ) |
Nvme1 PCIe TX plus lanes. | ||
nvme1_exp_txn | out | std_logic_vector ( 3 downto 0 ) |
Nvme1 PCIe TX minus lanes. | ||
nvme1_exp_rxp | in | std_logic_vector ( 3 downto 0 ) |
Nvme1 PCIe RX plus lanes. | ||
nvme1_exp_rxn | in | std_logic_vector ( 3 downto 0 ) |
Nvme1 PCIe RX minus lanes. | ||
leds | out | std_logic_vector ( 5 downto 0 ) |
Detailed Description
This is the main top level NvmeStorage module that provides access to the NVMe devices over the Axil bus and Axis request/reply streams.
- Date
- 2020-05-12
- Version
- 1.0.0
The main Nvme working module is NvmeStorageUnit. This NvmeStorage module splits the incomming data stream into two at the NvmeStoargeBlock level (4k) passing alternate blocks into the two NvmeStorageUnit engines. It passes register access signals to both NvmeStorageUnit's and multiplexes/de-multiplexes the AXI4 Streams from/to these.
The module accepts a 250 MHz clock input to which all input and output signals are syncronised with. The Platform parameter is available to handle alternative Pcie hard block interface types. The UseConfigure parameter sets the system to automatically configure the Nvme device on reset. Parameters for the actual Nvme device in use need to be set in the NvmeBlockSize, NvmeTotalBlocks and NvmeRegStride parameters. See the DuneNvmeStorageManual for more details.
- Copyright
- 2020 Beam Ltd, Apache License, Version 2.0 Copyright 2020 Beam Ltd Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.
The documentation for this class was generated from the following file:
- /src/dune/source/DuneNvme/src/NvmeStorage.vhd
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