Signals
sys_clk	std_logic := ' U '
pci_clk	std_logic := ' U '
pci_clk_gt	std_logic := ' U '
nvme0_clk	std_logic := ' U '
nvme0_clk_gt	std_logic := ' U '
nvme0_reset_n	std_logic := ' U '
nvme1_clk	std_logic := ' U '
nvme1_clk_gt	std_logic := ' U '
nvme1_reset_n	std_logic := ' U '
leds_l	std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
axil_clk	std_logic
axil_reset_n	std_logic
axil_reset	std_logic
axil	AxilBusType
	The AXI lite bus.
hostSend	AxisType
	AXI stream to send requests from the host.
hostSend_ready	std_logic
hostRecv	AxisType
	AXI stream for replies to the host.
hostrecv_ready	std_logic
dataStream	AxisDataStreamType
	AXI stream for test data.
dataStream_ready	std_logic
dataEnabled	std_logic
	Enabled signal for test data.

Instantiations
sys_clk_buf	clk_core
pci_clk_buf0	ibufds_gte3
nvme_clk_buf0	ibufds_gte3
nvme_clk_buf1	ibufds_gte3
pcie_host0	Pcie_host <Entity Pcie_host>
nvmestorage0	NvmeStorage <Entity NvmeStorage>
	Generate simulation core.
testdata0	TestData <Entity TestData>
obuf_led_i	obuf

Member Data Documentation

◆ nvmestorage0

nvmestorage0 NvmeStorage

Instantiation

Generate simulation core.

The doorbell register stride

The documentation for this class was generated from the following file: