| DuneNvme 1.0.2 This is a simple NVMe test environment that allows experimentation with the low level PCIe NVMe interfaces as available on a Xilinx FPGA environment. |
DuneNvmeTestOsperoTop Entity Reference
This module implements a complete test design for the NvmeStorage system with the KCU104 and Ospero OP47 boards. More...
Inheritance diagram for DuneNvmeTestOsperoTop:
Entities | |
| Behavioral | architecture |
Libraries | |
| ieee | |
| unisim | |
| work | |
Use Clauses | |
| std_logic_1164 | |
| numeric_std | |
| vcomponents | |
| NvmeStoragePkg | Package <NvmeStoragePkg> |
Generics | |
| Simulate | boolean := False |
| Platform | string := " Ultrascale " |
| The underlying target platform. | |
Ports | ||
| sys_clk_p | in | std_logic |
| sys_clk_n | in | std_logic |
| sys_reset | in | std_logic |
| pci_clk_p | in | std_logic |
| pci_clk_n | in | std_logic |
| pci_reset_n | in | std_logic |
| pci_exp_txp | out | std_logic_vector ( 3 downto 0 ) |
| pci_exp_txn | out | std_logic_vector ( 3 downto 0 ) |
| pci_exp_rxp | in | std_logic_vector ( 3 downto 0 ) |
| pci_exp_rxn | in | std_logic_vector ( 3 downto 0 ) |
| nvme0_clk_p | in | std_logic |
| nvme0_clk_n | in | std_logic |
| nvme0_reset | out | std_logic |
| nvme0_exp_txp | out | std_logic_vector ( 3 downto 0 ) |
| nvme0_exp_txn | out | std_logic_vector ( 3 downto 0 ) |
| nvme0_exp_rxp | in | std_logic_vector ( 3 downto 0 ) |
| nvme0_exp_rxn | in | std_logic_vector ( 3 downto 0 ) |
| nvme1_clk_p | in | std_logic |
| nvme1_clk_n | in | std_logic |
| nvme1_reset | out | std_logic |
| nvme1_exp_txp | out | std_logic_vector ( 3 downto 0 ) |
| nvme1_exp_txn | out | std_logic_vector ( 3 downto 0 ) |
| nvme1_exp_rxp | in | std_logic_vector ( 3 downto 0 ) |
| nvme1_exp_rxn | in | std_logic_vector ( 3 downto 0 ) |
| leds | out | std_logic_vector ( 7 downto 0 ) |
Detailed Description
This module implements a complete test design for the NvmeStorage system with the KCU104 and Ospero OP47 boards.
- Date
- 2020-05-12
- Version
- 1.0.0
The FPGA bit file produced allows a host computer to access a NVMe storage device connected to the FPGA via the hosts PCIe interface. It has a simple test data source and allows a host computer program to communicate with the NVMe device for research and development test work. See the DuneNvmeStorageManual for more details.
- Copyright
- 2020 Beam Ltd, Apache License, Version 2.0 Copyright 2020 Beam Ltd Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.
The documentation for this class was generated from the following file:
- /src/dune/source/DuneNvme/src/KCU105/DuneNvmeOpseroTop.vhd
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