DuneNvme 1.0.2 This is a simple NVMe test environment that allows experimentation with the low level PCIe NVMe interfaces as available on a Xilinx FPGA environment. |
CdcSingle Entity Reference
This is a simple module to pass a single bit wide signal across a clock domain. More...
Inheritance diagram for CdcSingle:
![](classCdcSingle.png)
Entities | |
Behavioral | architecture |
Libraries | |
ieee |
Use Clauses | |
std_logic_1164 | |
numeric_std |
Ports | ||
clk1 | in | std_logic |
The interface clock line. | ||
signal1 | in | std_logic |
The signal to pass. | ||
clk2 | in | std_logic |
The interface clock line. | ||
reset2 | in | std_logic |
The active high reset line. | ||
signal2 | out | std_logic |
The signals passed. |
Detailed Description
This is a simple module to pass a single bit wide signal across a clock domain.
- Date
- 2020-05-18
- Version
- 1.0.0
This is a very simple, low utilisation clock domain crossing unit for a single bit wide signal. It uses two clock synchronisation registers.
- Copyright
- 2020 Beam Ltd, Apache License, Version 2.0 Copyright 2020 Beam Ltd Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.
The documentation for this class was generated from the following file:
- /src/dune/source/DuneNvme/src/Cdc.vhd
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