DuneNvme 1.0.2 This is a simple NVMe test environment that allows experimentation with the low level PCIe NVMe interfaces as available on a Xilinx FPGA environment. |
Behavioral Architecture Reference
Processes | |
PROCESS_0 | ( clk ) |
Fifo input. |
Components | |
Fifo | <Entity Fifo> |
Simulation. |
Constants | |
TCQ | time := 1 ns |
FifoSize | integer := ( FifoSizeBytes * 8 / AxisDataStreamWidth ) |
DataWidth | integer := AxisDataStreamWidth+ 1 |
Signals | |
writeData | std_logic_vector ( DataWidth- 1 downto 0 ) := ( others = > ' 0 ' ) |
The output data. | |
readData | std_logic_vector ( DataWidth- 1 downto 0 ) := ( others = > ' U ' ) |
readDataReady | std_logic := ' 0 ' |
readDataValid | std_logic := ' 0 ' |
readDataHigh | std_logic_vector ( 127 downto 0 ) := ( others = > ' 0 ' ) |
readLastHigh | std_logic := ' 0 ' |
readHigh | std_logic := ' 0 ' |
Instantiations | |
fifo0 | Fifo <Entity Fifo> |
Fifo memory. |
The documentation for this class was generated from the following file:
- /src/dune/source/DuneNvme/src/AxisDataConvertFifo.vhd
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