AxisClockConverter Entity Reference

AxisStream clock domain crossing module. More...

Inheritance diagram for AxisClockConverter:

Entities
Behavioral	architecture

Libraries
ieee
unisim
work

Use Clauses
std_logic_1164
numeric_std
vcomponents
NvmeStoragePkg	Package <NvmeStoragePkg>
NvmeStorageIntPkg	Package <NvmeStorageIntPkg>

Generics
Simulate	boolean := False

Ports
clkRx	in	std_logic
		The input stream clock line.
resetRx	in	std_logic
		The input stream reset.
streamRx	inout	AxisStreamType := AxisStreamInput
		The input stream.
clkTx	in	std_logic
		The output stream clock line.
resetTx	in	std_logic
		The output stream reset.
streamTx	inout	AxisStreamType := AxisStreamOutput
		The output stream.

Detailed Description

AxisStream clock domain crossing module.

Author

Terry Barnaby (terry.nosp@m..bar.nosp@m.naby@.nosp@m.beam.nosp@m..ltd..nosp@m.uk)

Date

2020-03-28

Version

1.0.0

This module implements a clock crossing for an AXI4 stream encoded using the AxisStream record type. It uses the Xilinx AXI4 stream CDC IP to implement this. The Simulate parameter reduces the functionality to a simple pass through for simple system simulations.

Copyright

2020 Beam Ltd, Apache License, Version 2.0 Copyright 2020 Beam Ltd Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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The documentation for this class was generated from the following file:

• /src/dune/source/DuneNvme/src/AxisClockConverter.vhd