NvmeAccess Class Reference

Nvme access class. More...

#include <NvmeAccess.h>

Inheritance diagram for NvmeAccess:

Public Member Functions
int	init ()
void	close ()
void	setNvme (BUInt n)
BUInt	getNvme ()
void	reset ()
void	start ()
	Start NVMe request processing thread.
int	nvmeRequest (Bool wait, int queue, int opcode, BUInt nameSpace, BUInt32 address, BUInt32 arg10, BUInt32 arg11=0, BUInt32 arg12=0)
int	nvmeProcess ()
	This function runs as a separate thread in order to receive both replies and requests from the Nvme.
virtual void	nvmeDataPacket (NvmeRequestPacket &packet)
	Called when read data packet received.
BUInt32	readNvmeStorageReg (BUInt32 address)
void	writeNvmeStorageReg (BUInt32 address, BUInt32 data)
int	readNvmeReg32 (BUInt32 address, BUInt32 &data)
int	writeNvmeReg32 (BUInt32 address, BUInt32 data)
int	readNvmeReg64 (BUInt32 address, BUInt64 &data)
int	writeNvmeReg64 (BUInt32 address, BUInt64 data)
int	pcieWrite (BUInt8 request, BUInt32 address, BUInt32 num, BUInt32 *data)
int	pcieRead (BUInt8 request, BUInt32 address, BUInt32 num, BUInt32 *data)
int	packetSend (const NvmeRequestPacket &packet)
int	packetSend (const NvmeReplyPacket &packet)
int	readAvailable ()
	The number of bytes available on the receive stream.
void	dumpRegs (int nvmeNum=-1)
void	dumpDmaRegs (bool c2h, int chan)
void	dumpStatus ()

Protected Attributes
int	oregsFd
	Device drive fd for register access.
int	ohostSendFd
	Device driver fd for DMA send channel.
int	ohostRecvFd
	Device driver fd for DMA receive channel.
BFpgaInfo	oinfo
	Device driver information.
volatile BUInt32 *	oregs
	FPGA design's registers memory mapped.
volatile BUInt32 *	odmaRegs
	FPGA's PCIe XDMA modules DMA control registers memory mapped.
BUInt32 *	obufTx
BUInt32 *	obufRx
BUInt8	otag
BSemaphore	opacketReplySem
	Semaphore when a reply packet has been received.
NvmeReplyPacket	opacketReply
	Reply to request.
BSemaphore	oqueueReplySem
	Semaphore when a queue reply packet has been received.
pthread_t	othread
BUInt32	onvmeNum
	The nvme to communicate with, 0 is both.
BUInt32	onvmeRegbase
	The register base address.
BUInt32	oqueueNum
BUInt32	oqueueAdminMem [4096]
BUInt32	oqueueAdminRx
BUInt32	oqueueAdminTx
BUInt32	oqueueAdminId
BUInt32	oqueueDataMem [4096]
BUInt32	oqueueDataRx
BUInt32	oqueueDataTx
BUInt32	odataBlockMem [8192]

Detailed Description

Nvme access class.

This is a simple class that provides access to an Nvme storage device on FpgaFabric.

Author

Terry Barnaby terry.nosp@m..bar.nosp@m.naby@.nosp@m.beam.nosp@m..ltd..nosp@m.uk

Date

2020-04-10

Version

0.0.1

This requires an Nvme device on a KCU105 with the DuneNvmeStorageTest bit file running. The system allows an NVMe situtated on the Xilinx KCU105 to be accessed and experimented with. It implements the following:

• Configuration of the NVMe PCIe configuration space registers.
• Accessing the NVMe registers.
• Configuration of the NVMe's registers.
• Sending Admin commands to the NVMe via the admin request/completion shared memory queues. This includes configuration commands.
• Sending of read and write IO commands to the NVMe via IO request/completion shared memory queues.

There is access to the memory mappend NvmeStorage registers and there is one bi-directional DMA stream used for communication. The send and receive DMA streams are multiplexed between requests from the host and replies from the Nvme and also requests from the Nvme and replies from the host. The packets sent have a 128bit multiplexing stream number headerand are then encapsulated in the Xilinx PCIe DMA IP's headers.

The class accesses the FPGA system over the hosts PCIe bus using the Beam bfpga Linux driver. This interfaces with the Xilinx PCIe DMA IP. The class uses a thread to respond to Nvme requests.

Copyright

2020 Beam Ltd, Apache License, Version 2.0 Copyright 2020 Beam Ltd Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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The documentation for this class was generated from the following files:

• /src/dune/source/DuneNvme/test/NvmeAccess.h
• /src/dune/source/DuneNvme/test/NvmeAccess.cpp