NvmeAccess.h

/*******************************************************************************
 *  NvmeAccess.h    Provides access to an Nvme storage device on FpgaFabric
 *  T.Barnaby,  Beam Ltd,   2020-04-10
 *******************************************************************************
 */
#pragma once

#include <BeamLibBasic.h>
#include <stdio.h>
#include <string.h>
#include <stdlib.h>
#include <errno.h>
#include <unistd.h>
#include <fcntl.h>
#include <sys/mman.h>
#include <arpa/inet.h>
#include <pthread.h>
#include <sys/ioctl.h>
#include <bfpga_driver/bfpga.h>

const Bool  UseFpgaConfigure = 0;           
const Bool  UseConfigEngine = 0;            
const Bool  UseQueueEngine = 1;         
const BUInt PcieMaxPayloadSize = 32;        
const BUInt MaxPayloadSize = 1024;          
const BUInt BlockSize = 4096;           

const BUInt RegIdent        = 0x000;    
const BUInt RegControl      = 0x004;    
const BUInt RegStatus       = 0x008;    
const BUInt RegTotalBlocks      = 0x00C;    
const BUInt RegLostBlocks       = 0x010;    

const BUInt RegDataChunkStart   = 0x040;    
const BUInt RegDataChunkSize    = 0x044;    
const BUInt RegWriteError       = 0x048;    
const BUInt RegWriteNumBlocks   = 0x04C;    
const BUInt RegWriteTime        = 0x050;    
const BUInt RegWritePeakLatency = 0x054;    

const BUInt RegReadControl      = 0x080;    
const BUInt RegReadStatus       = 0x084;    
const BUInt RegReadBlock        = 0x088;    
const BUInt RegReadNumBlocks    = 0x08C;    
const BUInt RegReadError        = 0x090;    

const BUInt NvmeRegCapLow       = 0x000;    
const BUInt NvmeRegCapHigh      = 0x004;    

class NvmeRequestPacket {
public:
            NvmeRequestPacket(){
                memset(this, 0, sizeof(*this));
            }

    BUInt64     address;        
    BUInt32     numWords:11;        
    BUInt32     request:4;      
    BUInt32     fill2:1;        
    BUInt32     requesterId:16;     
    BUInt32     tag:8;          
    BUInt32     completerId:16;     
    BUInt32     requesterIdEnable:1;    
    BUInt32     fill3:7;        
    BUInt32     data[MaxPayloadSize];   
};

class NvmeReplyPacket {
public:
            NvmeReplyPacket(){
                memset(this, 0, sizeof(*this));
            }

    BUInt32     address:12;     
    BUInt32     error:4;        
    BUInt32     numBytes:13;        
    BUInt32     fill1:3;        
    BUInt32     numWords:11;        
    BUInt32     status:3;       
    BUInt32     fill2:2;        
    BUInt32     requesterId:16;     
    BUInt32     tag:8;          
    BUInt32     completerId:16;     
    BUInt32     fill3:7;        
    BUInt32     reply:1;        
    BUInt32     data[MaxPayloadSize];   
};

const BUInt NvmeSglTypeData = 0;

class NvmeSgl {
    BUInt64     address;
    BUInt32     length;
    BUInt8      fill0[2];
    BUInt8      subtype:4;
    BUInt8      type:4;
};

class NvmeAccess {
public:
            NvmeAccess();
            ~NvmeAccess();
    
    int     init();
    void        close();

    void        setNvme(BUInt n);
    BUInt       getNvme();
    void        reset();
    void        start();                            

    // Send a queued request to the NVMe
    int     nvmeRequest(Bool wait, int queue, int opcode, BUInt nameSpace, BUInt32 address, BUInt32 arg10, BUInt32 arg11 = 0, BUInt32 arg12 = 0);
    
    // NVMe process received requests thread
    int     nvmeProcess();
    virtual void    nvmeDataPacket(NvmeRequestPacket& packet);          
    
    // NvmeStorage units register access
    BUInt32     readNvmeStorageReg(BUInt32 address);
    void        writeNvmeStorageReg(BUInt32 address, BUInt32 data);
    
    // NVMe register access
    int     readNvmeReg32(BUInt32 address, BUInt32& data);
    int     writeNvmeReg32(BUInt32 address, BUInt32 data);
    int     readNvmeReg64(BUInt32 address, BUInt64& data);
    int     writeNvmeReg64(BUInt32 address, BUInt64 data);

    // Perform register access over PCIe both config and NVMe registers
    int     pcieWrite(BUInt8 request, BUInt32 address, BUInt32 num, BUInt32* data);
    int     pcieRead(BUInt8 request, BUInt32 address, BUInt32 num, BUInt32* data);

    // Packet send and receive
    int     packetSend(const NvmeRequestPacket& packet);
    int     packetSend(const NvmeReplyPacket& packet);
    int     readAvailable();                        
    
    // Debug
    void        dumpRegs(int nvmeNum = -1);
    void        dumpDmaRegs(bool c2h, int chan);
    void        dumpStatus();

    
protected:
    int         oregsFd;            
    int         ohostSendFd;            
    int         ohostRecvFd;            
    BFpgaInfo       oinfo;              
    volatile BUInt32*   oregs;              
    volatile BUInt32*   odmaRegs;           

    BUInt32*        obufTx;
    BUInt32*        obufRx;
    BUInt8          otag;

    BSemaphore      opacketReplySem;        
    NvmeReplyPacket     opacketReply;           
    BSemaphore      oqueueReplySem;         

    pthread_t       othread;
    BUInt32         onvmeNum;           
    BUInt32         onvmeRegbase;           
    BUInt32         oqueueNum;

    BUInt32         oqueueAdminMem[4096];
    BUInt32         oqueueAdminRx;
    BUInt32         oqueueAdminTx;
    BUInt32         oqueueAdminId;
    
    BUInt32         oqueueDataMem[4096];
    BUInt32         oqueueDataRx;
    BUInt32         oqueueDataTx;

    BUInt32         odataBlockMem[8192];
};