PcieStreamMuxFifo Entity Reference

This module implements a simple 1/2 stage Fifo for the PcieStreamMux module. More...

Inheritance diagram for PcieStreamMuxFifo:

Entities
Behavioral	architecture

Libraries
ieee
unisim
work

Use Clauses
std_logic_1164
numeric_std
vcomponents
NvmeStoragePkg	Package <NvmeStoragePkg>
NvmeStorageIntPkg	Package <NvmeStorageIntPkg>

Ports
clk	in	std_logic
		The interface clock line.
reset	in	std_logic
		The active high reset line.
streamIn	inout	AxisStreamType := AxisStreamInput
		Single multiplexed Input stream.
streamOut	inout	AxisStreamType := AxisStreamOutput
		Single multiplexed Ouput stream.

Detailed Description

This module implements a simple 1/2 stage Fifo for the PcieStreamMux module.

Author

Terry Barnaby (terry.nosp@m..bar.nosp@m.naby@.nosp@m.beam.nosp@m..ltd..nosp@m.uk)

Date

2020-05-31

Version

1.0.0

This is a simple 1/2 register FIFO of AxisStream's.

Copyright

2020 Beam Ltd, Apache License, Version 2.0 Copyright 2020 Beam Ltd Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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The documentation for this class was generated from the following file:

• /src/dune/source/DuneNvme/src/PcieStreamMux.vhd