Behavioral Architecture Reference

Functions
integer	pcieRqUserBits ( )
integer	pcieCqUserBits ( )

Processes
PROCESS_17	( clk )
PROCESS_18	( nvme_user_clk )
PROCESS_19	( nvme_user_clk )

Components
RegAccessClockConvertor	<Entity RegAccessClockConvertor>
	The interface clock line.
AxisClockConverter	<Entity AxisClockConverter>
	Register contents.
CdcSingle	<Entity CdcSingle>
	The interface clock line.
Pcie_nvme0	<Entity Pcie_nvme0>
	The signals passed.
Pcie_nvme1
StreamSwitch	<Entity StreamSwitch>
	The number of stream.
NvmeQueues	<Entity NvmeQueues>
	Output stream.
NvmeConfig	<Entity NvmeConfig>
	replies and requests
PcieStreamMux	<Entity PcieStreamMux>
	Nvme reply stream.
NvmeSim	<Entity NvmeSim>
	Nvme replies output stream.
NvmeWrite	<Entity NvmeWrite>
	System block size.
NvmeRead	<Entity NvmeRead>
	Register contents.

Constants
TCQ	time := 1 ns
NumStreams	integer := 8
ResetCycles	integer := ( 100 ms/ ClockPeriod )
RegWidth	integer := 32

Types
StateType	( STATE_START , STATE_IDLE , STATE_WRITE , STATE_READ1 , STATE_READ2 )

Subtypes
RegDataType	std_logic_vector ( RegWidth- 1 downto 0 )

Signals
reset_local	std_logic := ' 0 '
	Register contents.
reset_local_active	std_logic := ' 0 '
reset_local_counter	integer range 0 to ResetCycles := 0
streamSend	AxisStreamArrayType ( 0 to NumStreams- 1 )
streamRecv	AxisStreamArrayType ( 0 to NumStreams- 1 )
dataIn1	AxisStreamType
streamNone	AxisStreamType := AxisStreamOutput
streamSink	AxisStreamType := AxisStreamSink
hostReq	AxisStreamType
hostReq_ready	std_logic_vector ( 3 downto 0 )
hostReq_morethan1	std_logic
hostReq_user	std_logic_vector ( pcieRqUserBits- 1 downto 0 )
hostReply	AxisStreamType
nvmeReq	AxisStreamType
nvmeReply	AxisStreamType
nvmeReply_ready	std_logic_vector ( 3 downto 0 )
nvmeReply_user	std_logic_vector ( 32 downto 0 )
state	StateType := STATE_START
regWrite1	std_logic
	Enable write to register.
regRead1	std_logic
	Enable read from register.
regReadActive	std_logic
	Register read in progress.
regAddress1	unsigned ( 5 downto 0 ) := ( others = > ' 0 ' )
	Register to read/write.
regDataIn1	std_logic_vector ( 31 downto 0 )
	Register write data.
regDataOut0	std_logic_vector ( 31 downto 0 )
	Register contents.
regDataOut1	std_logic_vector ( 31 downto 0 )
	Register contents.
reg_id	RegDataType := x " 56010001 "
reg_control	RegDataType := ( others = > ' 0 ' )
reg_status	RegDataType := ( others = > ' 0 ' )
reg_totalBlocks	RegDataType := to_stl ( NvmeTotalBlocks , RegWidth )
reg_blocksLost	RegDataType := ( others = > ' 0 ' )
reg_nvmeWrite	RegDataType := ( others = > ' 0 ' )
reg_nvmeRead	RegDataType := ( others = > ' 0 ' )
nvmeWrite_write	std_logic := ' 0 '
nvmeRead_write	std_logic := ' 0 '
configStart	std_logic := ' U '
configStartDone	std_logic := ' U '
configComplete	std_logic := ' U '
writeEnable	std_logic := ' U '
waitingForData	std_logic := ' U '
dataEnabledOut1	std_logic := ' U '
writeComplete	std_logic := ' U '
phy_rdy_out	std_logic := ' U '
user_lnk_up	std_logic := ' U '
nvme_reset_local_n	std_logic := ' 0 '
nvme_user_clk	std_logic := ' U '
nvme_user_reset	std_logic := ' U '

Attributes
keep	string
keep	reset_local : signal is " true "
keep	nvme_reset_local_n : signal is " true "

Instantiations
regclockconvertor	RegAccessClockConvertor <Entity RegAccessClockConvertor>
axisclockconverter0	AxisClockConverter <Entity AxisClockConverter>
axisclockconverter1	AxisClockConverter <Entity AxisClockConverter>
axisclockconverter2	AxisClockConverter <Entity AxisClockConverter>
cdc0	CdcSingle <Entity CdcSingle>
pciestreammux0	PcieStreamMux <Entity PcieStreamMux>
nvmesim0	NvmeSim <Entity NvmeSim>
pcie_nvme_0	Pcie_nvme0 <Entity Pcie_nvme0>
	The PCIe to NVMe 0 interface.
pcie_nvme_1	pcie_nvme1
streamswitch0	StreamSwitch <Entity StreamSwitch>
nvmequeues0	NvmeQueues <Entity NvmeQueues>
nvmeconfig0	NvmeConfig <Entity NvmeConfig>
nvmewrite0	NvmeWrite <Entity NvmeWrite>
nvmeread0	NvmeRead <Entity NvmeRead>

Aliases
nvmeSend	is streamSend ( 0 )
nvmeRecv	is streamRecv ( 0 )
hostSend1	is streamSend ( 1 )
hostRecv1	is streamRecv ( 1 )
queueSend	is streamSend ( 2 )
queueRecv	is streamRecv ( 2 )
configSend	is streamSend ( 3 )
configRecv	is streamRecv ( 3 )
writeSend	is streamSend ( 4 )
writeRecv	is streamRecv ( 4 )
writeMemSend	is streamSend ( 5 )
writeMemRecv	is streamRecv ( 5 )
readSend	is streamSend ( 6 )
readRecv	is streamRecv ( 6 )
readMemSend	is streamSend ( 7 )
readMemRecv	is streamRecv ( 7 )

Member Data Documentation

pcie_nvme_0

pcie_nvme_0 Pcie_nvme0

Instantiation

The PCIe to NVMe 0 interface.

The PCIe to NVMe 1 interface

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The documentation for this class was generated from the following file:

• /src/dune/source/DuneNvme/src/NvmeStorageUnit.vhd