| DuneNvme 1.0.2 This is a simple NVMe test environment that allows experimentation with the low level PCIe NVMe interfaces as available on a Xilinx FPGA environment. |
AxilClockConverter Entity Reference
AXI Lite "bus" clock domain crossing module. More...
Entities | |
| Behavioral | architecture |
Libraries | |
| ieee | |
| unisim | |
| work | |
Use Clauses | |
| std_logic_1164 | |
| numeric_std | |
| vcomponents | |
| NvmeStoragePkg | Package <NvmeStoragePkg> |
Generics | |
| Simulate | boolean := False |
Ports | ||
| clk0 | in | std_logic |
| reset0 | in | std_logic |
| axil0In | in | AxilToSlaveType |
| axil0Out | out | AxilToMasterType |
| clk1 | in | std_logic |
| reset1 | in | std_logic |
| axil1Out | out | AxilToSlaveType |
| axil1In | in | AxilToMasterType |
Detailed Description
AXI Lite "bus" clock domain crossing module.
- Date
- 2020-02-28
- Version
- 1.0.0
This module provides a clock domain crossing implementation for an AXI4 lite "bus" interface. It uses the Xilinx IP in order to perform this.
- Copyright
- 2020 Beam Ltd, Apache License, Version 2.0 Copyright 2020 Beam Ltd Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.
The documentation for this class was generated from the following file:
- /src/dune/source/DuneNvme/src/AxilClockConverter.vhd
Generated by
1.8.15