FPGA Reconfigurable Hardware
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"Key in todays fast moving electronics market are time to market, flexibility and performance"
In recent years BEAM has been involved in the development of systems that utilise reconfigurable hardware. Specifically field programmable gate arrays (FPGAs).
Programmable hardware has been around for many years. The earliest parts were often used to 'soak up' simple standard fixed functionality 'glue logic'. In recent year the technologies have progressed very rapidly such that now complete systems on a chip (SoC) can be envisaged, all fully reconfigurable.
Traditional fixed systems with high development and tooling costs were confined to volume manufacture. The flexibility and capability of the these new devices open interesting avenues for development in small to medium manufacturing volumes.
The functionality of a reconfigurable hardware part is defined by specifically developed 'software'. Development is usually in one of the hardware definitions languages such as Verilog or VHDL. Traditional chips such as ethernet controllers, uarts etc. become software modules. Importantly traditional software algorithms can also become hardware. A number of companies now specialise in the provision of these IP modules. Applications
- Embedded systems
- Signal processing
- Parallel processing
- Algorithm acceleration
- Data acquisition & processing
System on a chip Taken to the exteme, the entire functionality of the traditional discrete chip system can be incorporated into a single chip. The attactions include :-
- Update path
- Migration in the event of part obsolesence
- Hardware performance
Many real world applications require processing large amounts of data in real time. Reconfigurable hardware preprocessing may be used to reduce the processing load on a primary processor.
An FPGA can pre-process the incoming data at great speed and in real time. The inherent parallism of an FPGA may perform algorithms very efficiently. An example of such a topology is the AstroFFTsystem, where a 14 bit, 4096 point FFT algorithm is performed on 50MSamples/sec incoming data.
Hardware Assist Similar in hardware terms to the topology of the hardware pre-process above. In this instance the data flow is both sourced and sunk by the hosting system. Such a system may for example perform parallel searching on a data stream to identify certain data patterns. These systems are best suited to algorithms which exibit a high degree of low level parallism.
BEAM Services BEAM has 12 years of experience in parallel processing. If you feel that the techniques and technologies outlined might be applicable solutions for your requirements, please feel free to contact us to discuss matters.