DuneNvme  1.0.0
This is a simple NVMe test environment that allows experimentation with the low level PCIe NVMe interfaces as available on a Xilinx FPGA environment.
Classes | Macros | Functions
test_nvme.cpp File Reference

This is a simple test program that uses the Xilinx xdma Linux driver to access. More...

#include <NvmeAccess.h>
#include <stdio.h>
#include <getopt.h>
#include <stdarg.h>
#include <math.h>

Classes

class  Control
 Overal program control class. More...
 

Macros

#define LDEBUG1   0
 
#define VERSION   "1.0.0"
 

Functions

BUInt8 get8 (void *data, BUInt address)
 
BUInt32 get32 (void *data, BUInt address)
 
BUInt64 get64 (void *data, BUInt address)
 
void usage (void)
 
int main (int argc, char **argv)
 

Detailed Description

This is a simple test program that uses the Xilinx xdma Linux driver to access.

Author
Terry Barnaby terry.nosp@m..bar.nosp@m.naby@.nosp@m.beam.nosp@m..ltd..nosp@m.uk
Date
2020-06-05
Version
1.0.0

This requires an Nvme device on a KCU105 with the DuneNvmeStorageTest bit file running. The system allows an NVMe situtated on the Xilinx KCU105 to be accessed and experimented with. It implements the following:

There is access to the memory mappend NvmeStorage registers and there is one bi-directional DMA stream used for communication. The send and receive DMA streams are multiplexed between requests from the host and replies from the Nvme and also requests from the Nvme and replies from the host. The packets sent have a 128bit multiplexing stream number headerand are then encapsulated in the Xilinx PCIe DMA IP's headers.

The program accesses the FPGA system over the hosts PCIe bus using the Beam bfpga Linux driver. This interfaces with the Xilinx PCIe DMA IP. The program uses a thread to respond to Nvme requests.