DuneNvme
1.0.0
This is a simple NVMe test environment that allows experimentation with the low level PCIe NVMe interfaces as available on a Xilinx FPGA environment.
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This is a simple module to pass a set of signals across a clock domain. More...
Entities | |
Behavioral | architecture |
Libraries | |
ieee |
Use Clauses | |
std_logic_1164 | |
numeric_std |
Generics | |
Width | integer := 1 |
Ports | ||
clk1 | in | std_logic |
The interface clock line. | ||
signals1 | in | std_logic_vector ( Width- 1 downto 0 ) |
The signals to pass. | ||
clk2 | in | std_logic |
The interface clock line. | ||
reset2 | in | std_logic |
The active high reset line. | ||
signals2 | out | std_logic_vector ( Width- 1 downto 0 ) |
The signals passed. |
This is a simple module to pass a set of signals across a clock domain.
This is a very simple, low utilisation clock domain crossing unit for a set of signals. There is no specific structure to the signals and with multiple signals their state can appear across the clock domain crossing on separate clock edges. So if multiple signals are passed some form of handshake system is needed on top of this. A simple method of acheiving this would be to have one of the signals be a valid signal that is activated/deactivated one clock cycle after the rest of the signals have changed state. It uses two clock synchronisation registers. Note it doesn't have an integral input clock domain register and thus it expects the input signals to be stable for at least two input clock cycles prior to a valid signal going high.
Note this module requires appropriate timing constraints for the CDC applied. This would normally a set_max_delay or set_false_path constraint on the timing to the sendCdcReg1 and recvCdcReg1 registers.