DuneNvme
1.0.0
This is a simple NVMe test environment that allows experimentation with the low level PCIe NVMe interfaces as available on a Xilinx FPGA environment.
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This is a simple module to pass a single bit wide signal across a clock domain. More...
Entities | |
Behavioral | architecture |
Libraries | |
ieee |
Use Clauses | |
std_logic_1164 | |
numeric_std |
Ports | ||
clk1 | in | std_logic |
The interface clock line. | ||
signal1 | in | std_logic |
The signal to pass. | ||
clk2 | in | std_logic |
The interface clock line. | ||
reset2 | in | std_logic |
The active high reset line. | ||
signal2 | out | std_logic |
The signals passed. |
This is a simple module to pass a single bit wide signal across a clock domain.
This is a very simple, low utilisation clock domain crossing unit for a single bit wide signal. It uses two clock synchronisation registers.