DuneNvme
1.0.0
This is a simple NVMe test environment that allows experimentation with the low level PCIe NVMe interfaces as available on a Xilinx FPGA environment.
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This module passes register access signals across a clock domain. More...
Entities | |
Behavioral | architecture |
Libraries | |
ieee | |
unisim | |
work |
Use Clauses | |
std_logic_1164 | |
numeric_std | |
vcomponents | |
NvmeStoragePkg | Package <NvmeStoragePkg> |
NvmeStorageIntPkg | Package <NvmeStorageIntPkg> |
Ports | ||
clk1 | in | std_logic |
The interface clock line. | ||
reset1 | in | std_logic |
The active high reset line. | ||
regWrite1 | in | std_logic |
Enable write to register. | ||
regAddress1 | in | unsigned ( 5 downto 0 ) |
Register to read/write. | ||
regDataIn1 | in | std_logic_vector ( 31 downto 0 ) |
Register write data. | ||
regDataOut1 | out | std_logic_vector ( 31 downto 0 ) |
Register contents. | ||
clk2 | in | std_logic |
The interface clock line. | ||
reset2 | in | std_logic |
The active high reset line. | ||
regWrite2 | out | std_logic |
Enable write to register. | ||
regAddress2 | out | unsigned ( 5 downto 0 ) |
Register to read/write. | ||
regDataIn2 | out | std_logic_vector ( 31 downto 0 ) |
Register write data. | ||
regDataOut2 | in | std_logic_vector ( 31 downto 0 ) |
Register contents. |
This module passes register access signals across a clock domain.
This is a very simple, low utilisation, clock domain crossing unit for the register interface. It is designed to work with asynchronous clocks of the same frequency. It assumes the write signal is delayed by 1 cycle from the address and data transitions to make sure all bits are stable before the actual register write. For reads you need to wait 6 cycles for the read data to be latched and sent across the clock domains. Note this module requires appropriate timing constraints for the CDC applied. This would normally a set_max_delay or set_false_path constraint on the timing to the sendCdcReg1 and recvCdcReg1 registers.