This module provides a simple dual ported RAM module that will be implemented in blockram if large enough.
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This module provides a simple dual ported RAM module that will be implemented in blockram if large enough.
- Author
- Terry Barnaby (terry.nosp@m..bar.nosp@m.naby@.nosp@m.beam.nosp@m..ltd..nosp@m.uk)
- Date
- 2020-05-09
- Version
- 1.0.0
This is a simple single clock dual ported RAM element written so that blockram can be easily infered by synthesis tools. The data width and size of the RAM are configurable parameters. Writes to memory happen in 1 clock cycle when the writeEnable signal is high. Reads from memory take two clock cycles. One to latch the read address and one for the readData to become available. There is a RegisterOutputs option on the readData output that will use the block RAM's internal data register for better system timing. This will add an additional 1 cycle latency on memory reads.
- Copyright
- GNU GPL License Copyright (c) Beam Ltd, All rights reserved.
This code is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
You should have received a copy of the GNU General Public License along with this code. If not, see https://www.gnu.org/licenses/.