DuneNvme  1.0.0
This is a simple NVMe test environment that allows experimentation with the low level PCIe NVMe interfaces as available on a Xilinx FPGA environment.
NvmeStorage Member List

This is the complete list of members for NvmeStorage, including all inherited members.

AddressWidth (defined in Ram)RamGeneric
AddressWidth (defined in Ram)RamGeneric
axilInNvmeStoragePort
axilOutNvmeStoragePort
BlockSizeNvmeStorageGeneric
clkNvmeStoragePort
RegAccessClockConvertor.clk1RegAccessClockConvertorPort
CdcSingle.clk1CdcSinglePort
RegAccessClockConvertor.clk2RegAccessClockConvertorPort
CdcSingle.clk2CdcSinglePort
clkRxAxisClockConverterPort
clkTxAxisClockConverterPort
ClockPeriodNvmeStorageGeneric
completeNvmeWritePort
configCompleteNvmeConfigPort
configStartNvmeConfigPort
dataDropBlocksNvmeStoragePort
dataEnabledOutNvmeStoragePort
dataInNvmeStoragePort
dataIn_readyNvmeStoragePort
AxisDataConvertFifo.DataWidthFifoGeneric
NvmeStorageUnit.NvmeQueues.DataWidthRamGeneric
NvmeStorageUnit.NvmeWrite.Ram.DataWidthRamGeneric
NvmeStorageUnit.NvmeWrite.Fifo.DataWidthFifoGeneric
NvmeWrite.enableNvmeWritePort
NvmeRead.enableNvmeReadPort
FifoSizeBytesAxisDataConvertFifoGeneric
hostInNvmeStreamMuxPort
hostOutNvmeStreamMuxPort
hostRecvNvmeStoragePort
hostRecv_readyNvmeStoragePort
hostReplyNvmeSimPort
hostReqNvmeSimPort
hostSendNvmeStoragePort
hostSend_readyNvmeStoragePort
ieee (defined in NvmeStorage)NvmeStorageLibrary
AxisDataConvertFifo.inDataFifoPort
NvmeStorageUnit.inDataFifoPort
AxisDataConvertFifo.inReadyFifoPort
NvmeStorageUnit.inReadyFifoPort
AxisDataConvertFifo.inValidFifoPort
NvmeStorageUnit.inValidFifoPort
leds (defined in NvmeStorage)NvmeStoragePort
memReplyOutNvmeWritePort
memReqInNvmeWritePort
AxisDataConvertFifo.nearFullFifoPort
NvmeStorageUnit.nearFullFifoPort
AxisDataConvertFifo.NearFullLevelFifoGeneric
NvmeStorageUnit.NearFullLevelFifoGeneric
NumBlocksDropNvmeStorageGeneric
numeric_std (defined in NvmeStorage)NvmeStorageuse clause
NumQueueEntriesNvmeQueuesGeneric
NumStreamsStreamSwitchGeneric
nvme0_clkNvmeStoragePort
nvme0_clk_gtNvmeStoragePort
nvme0_exp_rxnNvmeStoragePort
nvme0_exp_rxpNvmeStoragePort
nvme0_exp_txnNvmeStoragePort
nvme0_exp_txpNvmeStoragePort
nvme0_reset_nNvmeStoragePort
nvme0InNvmeStreamMuxPort
nvme0OutNvmeStreamMuxPort
nvme1_clkNvmeStoragePort
nvme1_clk_gtNvmeStoragePort
nvme1_exp_rxnNvmeStoragePort
nvme1_exp_rxpNvmeStoragePort
nvme1_exp_txnNvmeStoragePort
nvme1_exp_txpNvmeStoragePort
nvme1_reset_nNvmeStoragePort
nvme1InNvmeStreamMuxPort
nvme1OutNvmeStreamMuxPort
nvme_clkNvmeStorageUnitPort
nvme_clk_gtNvmeStorageUnitPort
nvme_exp_rxnNvmeStorageUnitPort
nvme_exp_rxpNvmeStorageUnitPort
nvme_exp_txnNvmeStorageUnitPort
nvme_exp_txpNvmeStorageUnitPort
nvme_reset_nNvmeStorageUnitPort
NvmeBlockSizeNvmeStorageGeneric
NvmeRegStrideNvmeStorageGeneric
nvmeReplyNvmeSimPort
nvmeReqNvmeSimPort
NvmeStorageIntPkg (defined in NvmeStorage)NvmeStorageuse clause
NvmeStoragePkg (defined in NvmeStorage)NvmeStorageuse clause
NvmeTotalBlocksNvmeStorageGeneric
AxisDataConvertFifo.outDataFifoPort
NvmeStorageUnit.outDataFifoPort
AxisDataConvertFifo.outReadyFifoPort
NvmeStorageUnit.outReadyFifoPort
AxisDataConvertFifo.outValidFifoPort
NvmeStorageUnit.outValidFifoPort
PcieCoreNvmeStorageUnitGeneric
PlatformNvmeStorageGeneric
readAddress (defined in Ram)RamPort
readAddress (defined in Ram)RamPort
readData (defined in Ram)RamPort
readData (defined in Ram)RamPort
readEnable (defined in Ram)RamPort
readEnable (defined in Ram)RamPort
regAddressNvmeStorageUnitPort
regAddress1RegAccessClockConvertorPort
regAddress2RegAccessClockConvertorPort
regDataNvmeWritePort
regDataInNvmeStorageUnitPort
regDataIn1RegAccessClockConvertorPort
regDataIn2RegAccessClockConvertorPort
regDataOutNvmeStorageUnitPort
regDataOut1RegAccessClockConvertorPort
regDataOut2RegAccessClockConvertorPort
AxisDataConvertFifo.RegisterOutputsFifoGeneric
NvmeStorageUnit.PcieStreamMux.RegisterOutputsPcieStreamMuxGeneric
NvmeStorageUnit.NvmeQueues.RegisterOutputsRamGeneric
NvmeStorageUnit.NvmeWrite.Ram.RegisterOutputsRamGeneric
NvmeStorageUnit.NvmeWrite.Fifo.RegisterOutputsFifoGeneric
regWriteNvmeStorageUnitPort
regWrite1RegAccessClockConvertorPort
regWrite2RegAccessClockConvertorPort
NvmeWrite.replyInNvmeWritePort
NvmeRead.replyInNvmeReadPort
NvmeWrite.requestOutNvmeWritePort
NvmeRead.requestOutNvmeReadPort
resetNvmeStoragePort
reset1RegAccessClockConvertorPort
RegAccessClockConvertor.reset2RegAccessClockConvertorPort
CdcSingle.reset2CdcSinglePort
resetRxAxisClockConverterPort
resetTxAxisClockConverterPort
signal1CdcSinglePort
signal2CdcSinglePort
SimulateNvmeStorageGeneric
AxisDataConvertFifo.SizeFifoGeneric
NvmeStorageUnit.NvmeQueues.SizeRamGeneric
NvmeStorageUnit.NvmeWrite.Ram.SizeRamGeneric
NvmeStorageUnit.NvmeWrite.Fifo.SizeFifoGeneric
std_logic_1164 (defined in NvmeStorage)NvmeStorageuse clause
stream1InPcieStreamMuxPort
stream1OutPcieStreamMuxPort
stream2InPcieStreamMuxPort
stream2OutPcieStreamMuxPort
stream3InPcieStreamMuxPort
stream3OutPcieStreamMuxPort
PcieStreamMux.streamInPcieStreamMuxFifoPort
StreamSwitch.streamInStreamSwitchPort
NvmeQueues.streamInNvmeQueuesPort
NvmeConfig.streamInNvmeConfigPort
PcieStreamMux.streamOutPcieStreamMuxFifoPort
StreamSwitch.streamOutStreamSwitchPort
NvmeQueues.streamOutNvmeQueuesPort
NvmeConfig.streamOutNvmeConfigPort
AxisDataConvertFifo.streamRxAxisDataConvertFifoPort
NvmeStorageUnit.streamRxAxisClockConverterPort
streamRx_readyAxisDataConvertFifoPort
AxisDataConvertFifo.streamTxAxisDataConvertFifoPort
NvmeStorageUnit.streamTxAxisClockConverterPort
unisim (defined in NvmeStorage)NvmeStorageLibrary
UseConfigureNvmeStorageGeneric
vcomponents (defined in NvmeStorage)NvmeStorageuse clause
waitingForDataNvmeWritePort
work (defined in NvmeStorage)NvmeStorageLibrary
writeAddress (defined in Ram)RamPort
writeAddress (defined in Ram)RamPort
writeData (defined in Ram)RamPort
writeData (defined in Ram)RamPort
writeEnable (defined in Ram)RamPort
writeEnable (defined in Ram)RamPort