This module Multiplexes/De-multiplexes a PCIe 128 bit stream into two streams using the 128bit header.
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clk | in | std_logic |
| | The interface clock line.
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reset | in | std_logic |
| | The active high reset line.
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stream1In | inout | AxisStreamType := AxisStreamInput |
| | Single multiplexed Input stream.
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stream1Out | inout | AxisStreamType := AxisStreamOutput |
| | Single multiplexed Ouput stream.
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stream2In | inout | AxisStreamType := AxisStreamInput |
| | Host Replies input stream.
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stream2Out | inout | AxisStreamType := AxisStreamOutput |
| | Host Requests output stream.
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stream3In | inout | AxisStreamType := AxisStreamInput |
| | Nvme Requests input stream.
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stream3Out | inout | AxisStreamType := AxisStreamOutput |
| | Nvme replies output stream.
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This module Multiplexes/De-multiplexes a PCIe 128 bit stream into two streams using the 128bit header.
- Author
- Terry Barnaby (terry.nosp@m..bar.nosp@m.naby@.nosp@m.beam.nosp@m..ltd..nosp@m.uk)
- Date
- 2020-04-08
- Version
- 1.0.0
This module will multiplex two bi-directional AxisStream's into a single bi-directional stream and de-multiplex a single bi-directional stream into two such streams. It is used to handle the quad stream nature of the Xilinx Pcie Gen3 hardblock merging the two streams into one for easy processing. The Xilinx Pcie Gen3 IP uses a pair of streams for host requests to the Pcie device (stream2) and a pair of streams for Pcie device requests to the host (stream3). Because of the 4 streams and their usage each will solely transport request or reply packets. This module sets and uses the state of bit 95 in the Pcie request and reply headers when multiplexing/de-muliplexing packets to/from the single stream (stream1). When muliplexing the packets bit 95 is set in the header on any reply packets and when de-multiplexing it looks at bit 95 in the header to determine which stream to send the packet on. The RegisterOutputs parameter allows the output data streams to be latched for better system timing at the expence of a 1 clock cycle latency. the module prioritises packet replies from the Pcie device when multiplexing. The multiplex and de-multiplex processes are separate and function independantly.
- Copyright
- GNU GPL License Copyright (c) Beam Ltd, All rights reserved.
This code is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
You should have received a copy of the GNU General Public License along with this code. If not, see https://www.gnu.org/licenses/.