DuneNvme  1.0.0
This is a simple NVMe test environment that allows experimentation with the low level PCIe NVMe interfaces as available on a Xilinx FPGA environment.
DuneNvmeTestTop Member List

This is the complete list of members for DuneNvmeTestTop, including all inherited members.

AddressWidth (defined in Ram)RamGeneric
AddressWidth (defined in Ram)RamGeneric
axilInNvmeStoragePort
axilOutNvmeStoragePort
NvmeStorage.BlockSizeNvmeStorageGeneric
TestData.BlockSizeTestDataGeneric
NvmeStorage.clkNvmeStoragePort
TestData.clkTestDataPort
RegAccessClockConvertor.clk1RegAccessClockConvertorPort
CdcSingle.clk1CdcSinglePort
RegAccessClockConvertor.clk2RegAccessClockConvertorPort
CdcSingle.clk2CdcSinglePort
clkRxAxisClockConverterPort
clkTxAxisClockConverterPort
ClockPeriodNvmeStorageGeneric
completeNvmeWritePort
configCompleteNvmeConfigPort
configStartNvmeConfigPort
dataDropBlocksNvmeStoragePort
dataEnabledOutNvmeStoragePort
dataInNvmeStoragePort
dataIn_readyNvmeStoragePort
dataOutTestDataPort
dataOutReadyTestDataPort
AxisDataConvertFifo.DataWidthFifoGeneric
NvmeStorageUnit.NvmeQueues.DataWidthRamGeneric
NvmeStorageUnit.NvmeWrite.Ram.DataWidthRamGeneric
NvmeStorageUnit.NvmeWrite.Fifo.DataWidthFifoGeneric
NvmeStorage.NvmeWrite.enableNvmeWritePort
NvmeStorage.NvmeRead.enableNvmeReadPort
TestData.enableTestDataPort
FifoSizeBytesAxisDataConvertFifoGeneric
hostInNvmeStreamMuxPort
hostOutNvmeStreamMuxPort
hostRecvNvmeStoragePort
hostRecv_readyNvmeStoragePort
hostReplyNvmeSimPort
hostReqNvmeSimPort
hostSendNvmeStoragePort
hostSend_readyNvmeStoragePort
ieee (defined in DuneNvmeTestTop)DuneNvmeTestTopLibrary
AxisDataConvertFifo.inDataFifoPort
NvmeStorageUnit.inDataFifoPort
AxisDataConvertFifo.inReadyFifoPort
NvmeStorageUnit.inReadyFifoPort
AxisDataConvertFifo.inValidFifoPort
NvmeStorageUnit.inValidFifoPort
leds (defined in DuneNvmeTestTop)DuneNvmeTestTopPort
memReplyOutNvmeWritePort
memReqInNvmeWritePort
AxisDataConvertFifo.nearFullFifoPort
NvmeStorageUnit.nearFullFifoPort
AxisDataConvertFifo.NearFullLevelFifoGeneric
NvmeStorageUnit.NearFullLevelFifoGeneric
NumBlocksDropNvmeStorageGeneric
numeric_std (defined in DuneNvmeTestTop)DuneNvmeTestTopuse clause
NumQueueEntriesNvmeQueuesGeneric
NumStreamsStreamSwitchGeneric
nvme0_clkNvmeStoragePort
nvme0_clk_gtNvmeStoragePort
nvme0_exp_rxn (defined in DuneNvmeTestTop)DuneNvmeTestTopPort
nvme0_exp_rxp (defined in DuneNvmeTestTop)DuneNvmeTestTopPort
nvme0_exp_txn (defined in DuneNvmeTestTop)DuneNvmeTestTopPort
nvme0_exp_txp (defined in DuneNvmeTestTop)DuneNvmeTestTopPort
nvme0_reset_nNvmeStoragePort
nvme0InNvmeStreamMuxPort
nvme0OutNvmeStreamMuxPort
nvme1_clkNvmeStoragePort
nvme1_clk_gtNvmeStoragePort
nvme1_exp_rxn (defined in DuneNvmeTestTop)DuneNvmeTestTopPort
nvme1_exp_rxp (defined in DuneNvmeTestTop)DuneNvmeTestTopPort
nvme1_exp_txn (defined in DuneNvmeTestTop)DuneNvmeTestTopPort
nvme1_exp_txp (defined in DuneNvmeTestTop)DuneNvmeTestTopPort
nvme1_reset_nNvmeStoragePort
nvme1InNvmeStreamMuxPort
nvme1OutNvmeStreamMuxPort
nvme_clkNvmeStorageUnitPort
nvme_clk_gtNvmeStorageUnitPort
nvme_clk_n (defined in DuneNvmeTestTop)DuneNvmeTestTopPort
nvme_clk_p (defined in DuneNvmeTestTop)DuneNvmeTestTopPort
nvme_exp_rxnNvmeStorageUnitPort
nvme_exp_rxpNvmeStorageUnitPort
nvme_exp_txnNvmeStorageUnitPort
nvme_exp_txpNvmeStorageUnitPort
nvme_reset_n (defined in DuneNvmeTestTop)DuneNvmeTestTopPort
NvmeBlockSizeNvmeStorageGeneric
NvmeRegStrideNvmeStorageGeneric
nvmeReplyNvmeSimPort
nvmeReqNvmeSimPort
NvmeStorageIntPkg (defined in NvmeStorage)NvmeStorageuse clause
NvmeStorageIntPkg (defined in TestData)TestDatause clause
NvmeStoragePkg (defined in DuneNvmeTestTop)DuneNvmeTestTopuse clause
NvmeTotalBlocksNvmeStorageGeneric
AxisDataConvertFifo.outDataFifoPort
NvmeStorageUnit.outDataFifoPort
AxisDataConvertFifo.outReadyFifoPort
NvmeStorageUnit.outReadyFifoPort
AxisDataConvertFifo.outValidFifoPort
NvmeStorageUnit.outValidFifoPort
pci_clk_n (defined in DuneNvmeTestTop)DuneNvmeTestTopPort
pci_clk_p (defined in DuneNvmeTestTop)DuneNvmeTestTopPort
pci_exp_rxn (defined in DuneNvmeTestTop)DuneNvmeTestTopPort
pci_exp_rxp (defined in DuneNvmeTestTop)DuneNvmeTestTopPort
pci_exp_txn (defined in DuneNvmeTestTop)DuneNvmeTestTopPort
pci_exp_txp (defined in DuneNvmeTestTop)DuneNvmeTestTopPort
pci_reset_n (defined in DuneNvmeTestTop)DuneNvmeTestTopPort
PcieCoreNvmeStorageUnitGeneric
PlatformNvmeStorageGeneric
readAddress (defined in Ram)RamPort
readAddress (defined in Ram)RamPort
readData (defined in Ram)RamPort
readData (defined in Ram)RamPort
readEnable (defined in Ram)RamPort
readEnable (defined in Ram)RamPort
regAddressNvmeStorageUnitPort
regAddress1RegAccessClockConvertorPort
regAddress2RegAccessClockConvertorPort
regDataNvmeWritePort
regDataInNvmeStorageUnitPort
regDataIn1RegAccessClockConvertorPort
regDataIn2RegAccessClockConvertorPort
regDataOutNvmeStorageUnitPort
regDataOut1RegAccessClockConvertorPort
regDataOut2RegAccessClockConvertorPort
AxisDataConvertFifo.RegisterOutputsFifoGeneric
NvmeStorageUnit.PcieStreamMux.RegisterOutputsPcieStreamMuxGeneric
NvmeStorageUnit.NvmeQueues.RegisterOutputsRamGeneric
NvmeStorageUnit.NvmeWrite.Ram.RegisterOutputsRamGeneric
NvmeStorageUnit.NvmeWrite.Fifo.RegisterOutputsFifoGeneric
regWriteNvmeStorageUnitPort
regWrite1RegAccessClockConvertorPort
regWrite2RegAccessClockConvertorPort
NvmeWrite.replyInNvmeWritePort
NvmeRead.replyInNvmeReadPort
NvmeWrite.requestOutNvmeWritePort
NvmeRead.requestOutNvmeReadPort
NvmeStorage.resetNvmeStoragePort
TestData.resetTestDataPort
reset1RegAccessClockConvertorPort
RegAccessClockConvertor.reset2RegAccessClockConvertorPort
CdcSingle.reset2CdcSinglePort
resetRxAxisClockConverterPort
resetTxAxisClockConverterPort
signal1CdcSinglePort
signal2CdcSinglePort
Simulate (defined in DuneNvmeTestTop)DuneNvmeTestTopGeneric
AxisDataConvertFifo.SizeFifoGeneric
NvmeStorageUnit.NvmeQueues.SizeRamGeneric
NvmeStorageUnit.NvmeWrite.Ram.SizeRamGeneric
NvmeStorageUnit.NvmeWrite.Fifo.SizeFifoGeneric
std_logic_1164 (defined in DuneNvmeTestTop)DuneNvmeTestTopuse clause
stream1InPcieStreamMuxPort
stream1OutPcieStreamMuxPort
stream2InPcieStreamMuxPort
stream2OutPcieStreamMuxPort
stream3InPcieStreamMuxPort
stream3OutPcieStreamMuxPort
PcieStreamMux.streamInPcieStreamMuxFifoPort
StreamSwitch.streamInStreamSwitchPort
NvmeQueues.streamInNvmeQueuesPort
NvmeConfig.streamInNvmeConfigPort
PcieStreamMux.streamOutPcieStreamMuxFifoPort
StreamSwitch.streamOutStreamSwitchPort
NvmeQueues.streamOutNvmeQueuesPort
NvmeConfig.streamOutNvmeConfigPort
AxisDataConvertFifo.streamRxAxisDataConvertFifoPort
NvmeStorageUnit.streamRxAxisClockConverterPort
streamRx_readyAxisDataConvertFifoPort
AxisDataConvertFifo.streamTxAxisDataConvertFifoPort
NvmeStorageUnit.streamTxAxisClockConverterPort
sys_clk_n (defined in DuneNvmeTestTop)DuneNvmeTestTopPort
sys_clk_p (defined in DuneNvmeTestTop)DuneNvmeTestTopPort
sys_reset (defined in DuneNvmeTestTop)DuneNvmeTestTopPort
unisim (defined in DuneNvmeTestTop)DuneNvmeTestTopLibrary
UseConfigureNvmeStorageGeneric
vcomponents (defined in DuneNvmeTestTop)DuneNvmeTestTopuse clause
waitingForDataNvmeWritePort
work (defined in DuneNvmeTestTop)DuneNvmeTestTopLibrary
writeAddress (defined in Ram)RamPort
writeAddress (defined in Ram)RamPort
writeData (defined in Ram)RamPort
writeData (defined in Ram)RamPort
writeEnable (defined in Ram)RamPort
writeEnable (defined in Ram)RamPort