|
SigSendType | std_logic_vector ( SigSendWidth- 1 downto 0 ) |
SigRecvType | std_logic_vector ( SigRecvWidth- 1 downto 0 ) |
|
keep | string |
async_reg | string |
keep | sendCdcReg1 : signal is " true " |
keep | sendCdcReg2 : signal is " true " |
keep | recvCdcReg0 : signal is " true " |
keep | recvCdcReg1 : signal is " true " |
keep | recvCdcReg2 : signal is " true " |
async_reg | sendCdcReg1 : signal is " true " |
async_reg | sendCdcReg2 : signal is " true " |
async_reg | recvCdcReg1 : signal is " true " |
async_reg | recvCdcReg2 : signal is " true " |
The documentation for this class was generated from the following file:
- /src/dune/FpgaPlay/test035-nvme/src/RegAccessClockConvertor.vhd