# BEGIN Project Options
SET flowvendor = Foundation_iSE
SET vhdlsim = True
SET verilogsim = True
SET workingdirectory = C:\DESIGNS\FPGA\Custom_Libera
SET speedgrade = -6
SET simulationfiles = Behavioral
SET asysymbol = True
SET addpads = False
SET device = xc2vp30
SET implementationfiletype = Edif
SET busformat = BusFormatAngleBracketNotRipped
SET foundationsym = False
SET package = ff1152
SET createndf = False
SET designentry = VHDL
SET devicefamily = virtex2p
SET formalverification = False
SET removerpms = False
# END Project Options
# BEGIN Select
SELECT Single_Port_Block_Memory family Xilinx,_Inc. 6.2
# END Select
# BEGIN Parameters
CSET handshaking_pins=false
CSET init_value=0
CSET select_primitive=16kx1
CSET initialization_pin_polarity=Active_High
CSET global_init_value=0
CSET depth=8192
CSET write_enable_polarity=Active_High
CSET port_configuration=Read_And_Write
CSET enable_pin_polarity=Active_High
CSET component_name=spram8192x32
CSET active_clock_edge=Rising_Edge_Triggered
CSET additional_output_pipe_stages=0
CSET disable_warning_messages=true
CSET limit_data_pitch=18
CSET primitive_selection=Optimize_For_Area
CSET enable_pin=false
CSET init_pin=false
CSET write_mode=No_Read_On_Write
CSET has_limit_data_pitch=false
CSET load_init_file=false
CSET width=32
CSET register_inputs=false
# END Parameters
GENERATE