library ieee; use ieee.std_logic_1164.ALL; use ieee.numeric_std.ALL; use IEEE.STD_LOGIC_SIGNED.ALL; use IEEE.STD_LOGIC_ARITH.ALL; -- synopsys translate_off library UNISIM; use UNISIM.Vcomponents.ALL; -- synopsys translate_on entity pll3 is port ( --global signals reset : in std_logic; clk : in std_logic; init : in std_logic; --PLL controls loop_gain : in std_logic_vector (3 downto 0); loop_ctrl : in std_logic; freq_init : in std_logic_vector (31 downto 0); dds_freq_min : in std_logic_vector (31 downto 0); dds_freq_max : in std_logic_vector (31 downto 0); dds_freq_limit_en : in std_logic; ph_init : in std_logic_vector (8 downto 0); --azimuth frev_gain : in std_logic_vector(13 downto 0); LO_delay : in std_logic_vector(7 downto 0); LO_sel : out std_logic; --ADCs input signals adc_a_i : in std_logic_vector (13 downto 0); adc_b_i : in std_logic_vector (13 downto 0); adc_c_i : in std_logic_vector (13 downto 0); -- PHASETABLE WRITE phase_addr_in : in std_logic_vector (12 downto 0); phase_data_in : in std_logic_vector (3 downto 0); write_enable : in std_logic; --others -- trigger : in std_logic; LO_out : out std_logic; --software timings ELFT_in : in std_logic; INJ_cnt_rst : in std_logic; --hardware timings F_rev_in : in std_logic; HC_timing_in : in std_logic; ST_timing_in : in std_logic; inject_trig : in std_logic; --READOUT OF POINTER TABLES C_table_addr : out std_logic; HC_table_addr : out std_logic; HC_TAB_RD_ADDR : in std_logic_vector (4 downto 0); HC_TAB_RD_DAT : out std_logic_vector (31 downto 0); C_TAB_RD_ADDR : in std_logic_vector (12 downto 0); C_TAB_RD_DAT : out std_logic_vector (31 downto 0); ST_TAB_RD_ADDR : in std_logic_vector (2 downto 0); ST_TAB_RD_DAT : out std_logic_vector (31 downto 0); INJ_TAB_RD_ADDR : in std_logic_vector (2 downto 0); INJ_TAB_RD_DAT : out std_logic_vector (31 downto 0); --readout of pointer registers ST_tab_ST_addr : out std_logic_vector (2 downto 0); HC_tab_ST_addr : out std_logic_vector (4 downto 0); C_tab_ST_addr : out std_logic_vector (12 downto 0); INJ_tab_ST_addr : out std_logic_vector (2 downto 0); SDRAM_ST_addr : out std_logic_vector (25 downto 0); --injection number INJ_cnt_o : out std_logic_vector (3 downto 0); --SDRAM SIGNALS SDRAM_ADDR_OUT : out std_logic_vector (25 downto 0); write_SDRAM : out std_logic; result_0 : out std_logic_vector (23 downto 0); result_1 : out std_logic_vector (23 downto 0); result_2 : out std_logic_vector (23 downto 0); -- ANALYSER SIGNALS ANA_record_len : in std_logic_vector(12 downto 0); ANA_addr_pointer : out std_logic_vector(12 downto 0); ANA_RD_addr : in std_logic_vector(13 downto 0); ANA_RD_DAT : out std_logic_vector(31 downto 0); ANA_slope : in std_logic; ANA_ARM : in std_logic; ANA_timer_en : in std_logic; ANA_DATA_ACQUIRED : out std_logic; ANA_trig_src : in std_logic_vector(2 downto 0); ANA_CH1_src : in std_logic_vector(2 downto 0); ANA_CH2_src : in std_logic_vector(2 downto 0); ANA_timer : in std_logic_vector(23 downto 0); ANA_delay : in std_logic_vector(31 downto 0) ); end pll3; architecture BEHAVIORAL of pll3 is --BLR signal e0,e1,e2 :std_logic_vector(23 downto 0) ; signal b0,b1,b2 :std_logic_vector(23 downto 0) ; signal x0,x1,x2,y0,y1,y2 :std_logic_vector(23 downto 0) ; signal BLR_data_in_0, BLR_data_in_1, BLR_data_in_2 : std_logic_vector (23 downto 0); signal BLR_data_out_0 : std_logic_vector (23 downto 0); signal BLR_data_out_1 : std_logic_vector (23 downto 0); signal BLR_data_out_2 : std_logic_vector (23 downto 0); --DDS signal ph_table_addr : std_logic_vector (12 downto 0); signal dds_ph,dds_freq, dds_freq_limit : std_logic_vector (31 downto 0); signal f_error_dds : std_logic_vector(31 downto 0) ; signal load_dds_freq, dds_freq_OVR, dds_freq_UR,clk62 : std_logic; --phase table signal ram_out : std_logic_vector (3 downto 0); signal LO_pulse, BLR_pulse, phtable_sel, GATE_pulse, write_enable_0, write_enable_1 : std_logic; signal PT_cnt : std_logic_vector (3 downto 0); signal PT_cnt_reset, PT_cnt_en : std_logic; --multiplier signal mul_data_in, mult_out, mult_neg_data_in : std_logic_vector (13 downto 0); --filter signal n1,n2,n3,n4,n5,n6,s3,s4,s5,s6,filter_data_out : std_logic_vector(23 downto 0); -- integrators TYPE STATE_TYPE IS (idle,integrate,ready,reset_acc); SIGNAL state: STATE_TYPE; signal accumulate_0,accumulate_1,accumulate_2, result0_tmp,result1_tmp,result2_tmp: std_logic_vector (23 downto 0); signal acc_reset,result_Write_en,result_valid : std_logic; --sychronisation unit TYPE STATE_TYPE_synch IS (idle_synch,wait_frev,wait_beam,start_acq,stop_acq); SIGNAL state_synch: STATE_TYPE_synch; signal HC_synch : std_logic; signal HC_tim_rising : std_logic; signal inj_trig_rising : std_logic; signal PT_MSB_rising : std_logic; signal F_rev_rising : std_logic; signal LO_delay_stop : std_logic; signal LO_delay_count : std_logic_vector(7 downto 0); signal LO_delay_count_enable : std_logic; signal LO_delay_load : std_logic; signal inj_trig_edg_det : std_logic_vector(1 downto 0); signal HC_tim_edg_det : std_logic_vector(1 downto 0); signal ST_edg_det : std_logic_vector(1 downto 0); signal HC_timing_rising : std_logic; signal ST_timing_rising : std_logic; signal HC_temp : std_logic; signal F_rev_edg_det : std_logic_vector(1 downto 0); signal PT_MSB_edg_det : std_logic_vector(1 downto 0); signal measurements_valid : std_logic; signal terminate_measurements : std_logic; signal sig_PU_sel : std_logic; signal ram_out_0,ram_out_1 : std_logic_vector(3 downto 0); signal Frev_num : std_logic_vector(13 downto 0); signal C_timer_count : std_logic_vector(16 downto 0); signal C_timer_stop : std_logic; signal C_timer_load : std_logic; signal C_timer_val : std_logic_vector(16 downto 0):=std_logic_vector(to_signed(125000,17)); signal C_timing : std_logic; --phasetable number counter signal PhaseTable_cnt_rst : std_logic; signal PhaseTable_cnt : std_logic_vector(3 downto 0); signal change_PT_en, change_PT : std_logic; --injection number counter signal INJ_cnt_en : std_logic; signal INJ_cnt : std_logic_vector(2 downto 0); --memory pointers tables signal INJ_tab_wr_addr : std_logic_vector (2 downto 0); signal INJ_tab_wr_dat : std_logic_vector (31 downto 0); signal INJ_tab_wen : std_logic; signal HC_tab_wr_addr : std_logic_vector (4 downto 0); signal HC_tab_wr_dat : std_logic_vector (31 downto 0); signal HC_tab_wen : std_logic; signal C_tab_wr_addr : std_logic_vector (12 downto 0); signal C_tab_wr_dat : std_logic_vector (31 downto 0); signal C_tab_wen : std_logic; signal ST_tab_wr_addr : std_logic_vector (2 downto 0); signal ST_tab_wr_dat : std_logic_vector (31 downto 0); signal ST_tab_wen : std_logic; signal INJ_tab_addr_cnt_en : std_logic; signal INJ_tab_addr_cnt : std_logic_vector (2 downto 0); signal HC_tab_addr_cnt : std_logic_vector (4 downto 0); signal C_tab_addr_cnt : std_logic_vector (12 downto 0); signal ST_tab_addr_cnt : std_logic_vector (2 downto 0); signal HC_tab_addr_cnt_en : std_logic; signal C_tab_addr_cnt_en : std_logic; signal ST_tab_addr_cnt_en : std_logic; signal SDRAM_Addr_cnt : std_logic_vector (25 downto 0); signal SDRAM_Addr_cnt_en : std_logic; --others signal f_error,F_ERR : std_logic_vector (23 downto 0); signal filter1_in : std_logic_vector (23 downto 0); signal inj_num : std_logic_vector(5 downto 0); --chipscope signal data_ch1, data_alt_ch1 : std_logic_vector(47 downto 0); signal data_ch0, data_alt_ch0 : std_logic_vector(95 downto 0); signal trig_ch0, trig_ch1 : std_logic_vector(3 downto 0); signal control_port_i, async_port_i : std_logic_vector (31 downto 0); --ANALYSER signal ANA_trig : std_logic_vector(7 downto 0); signal data_0 : std_logic_vector(31 downto 0); signal data_1 : std_logic_vector(31 downto 0); signal data_2 : std_logic_vector(31 downto 0); signal data_3 : std_logic_vector(31 downto 0); signal data_4 : std_logic_vector(31 downto 0); signal data_5 : std_logic_vector(31 downto 0); signal data_6 : std_logic_vector(31 downto 0); signal data_7 : std_logic_vector(31 downto 0); component phasetable IS port ( addra: IN std_logic_VECTOR(12 downto 0); addrb: IN std_logic_VECTOR(12 downto 0); clka: IN std_logic; clkb: IN std_logic; dina: IN std_logic_VECTOR(3 downto 0); doutb: OUT std_logic_VECTOR(3 downto 0); wea: IN std_logic); END component; component dpram8192x32 port ( addra: IN std_logic_VECTOR(12 downto 0); addrb: IN std_logic_VECTOR(12 downto 0); clka: IN std_logic; clkb: IN std_logic; dinb: IN std_logic_VECTOR(31 downto 0); douta: OUT std_logic_VECTOR(31 downto 0); web: IN std_logic); end component; component dpram8x32 port ( addra: IN std_logic_VECTOR(2 downto 0); addrb: IN std_logic_VECTOR(2 downto 0); clka: IN std_logic; clkb: IN std_logic; dinb: IN std_logic_VECTOR(31 downto 0); douta: OUT std_logic_VECTOR(31 downto 0); web: IN std_logic); end component; component dpram32x32 port ( addra: IN std_logic_VECTOR(4 downto 0); addrb: IN std_logic_VECTOR(4 downto 0); clka: IN std_logic; clkb: IN std_logic; dinb: IN std_logic_VECTOR(31 downto 0); douta: OUT std_logic_VECTOR(31 downto 0); web: IN std_logic); end component; component chipscope_analyser port ( data_ch0 : in STD_LOGIC_VECTOR (95 downto 0); data_ch1 : in STD_LOGIC_VECTOR (47 downto 0); clk : in STD_LOGIC; reset : in std_logic; clk_ext : in std_logic; trig_ch0 : in STD_LOGIC_VECTOR (3 downto 0); trig_ch1 : in STD_LOGIC_VECTOR (3 downto 0); control_port_i : in STD_LOGIC_VECTOR (31 downto 0); async_port_i : in STD_LOGIC_VECTOR (31 downto 0); control_port_o : out STD_LOGIC_VECTOR (7 downto 0); data_alt_ch0 : in STD_LOGIC_VECTOR (95 downto 0); data_alt_ch1 : in STD_LOGIC_VECTOR (47 downto 0) ); end component; component analyser Port ( clk : in std_logic; reset : in std_logic; ANA_record_len : in std_logic_vector(12 downto 0); ANA_addr_pointer : out std_logic_vector(12 downto 0); ANA_RD_addr : in std_logic_vector(13 downto 0); ANA_RD_DAT : out std_logic_vector(31 downto 0); ANA_slope : in std_logic; ANA_ARM : in std_logic; ANA_timer_en : in std_logic; ANA_DATA_ACQUIRED : out std_logic; ANA_trig : in std_logic_vector(7 downto 0); data_0 : in std_logic_vector(31 downto 0); data_1 : in std_logic_vector(31 downto 0); data_2 : in std_logic_vector(31 downto 0); data_3 : in std_logic_vector(31 downto 0); data_4 : in std_logic_vector(31 downto 0); data_5 : in std_logic_vector(31 downto 0); data_6 : in std_logic_vector(31 downto 0); data_7 : in std_logic_vector(31 downto 0); ANA_trig_src : in std_logic_vector(2 downto 0); ANA_CH1_src : in std_logic_vector(2 downto 0); ANA_CH2_src : in std_logic_vector(2 downto 0); ANA_timer : in std_logic_vector(23 downto 0); ANA_delay : in std_logic_vector(31 downto 0) ); end component; begin --************************************************************************************************************** --**************************** Loop Gain Control *************************************************** --************************************************************************************************************** With loop_gain (3 downto 0) select F_ERR <= f_error(23 downto 0) when "0000", (f_error(23)& f_error(23 downto 1)) when "0001", (f_error(23)& f_error(23)& f_error(23 downto 2)) when "0010", (f_error(23)& f_error(23)& f_error(23)& f_error(23 downto 3)) when "0011", (f_error(23)& f_error(23)& f_error(23)& f_error(23)& f_error(23 downto 4)) when "0100", (f_error(23)& f_error(23)& f_error(23)& f_error(23)& f_error(23)& f_error(23 downto 5)) when "0101", (f_error(23)& f_error(23)& f_error(23)& f_error(23)& f_error(23)& f_error(23)& f_error(23 downto 6)) when "0110", (f_error(23)& f_error(23)& f_error(23)& f_error(23)& f_error(23)& f_error(23)& f_error(23)& f_error(23 downto 7)) when "0111", (f_error(23)& f_error(23)& f_error(23)& f_error(23)& f_error(23)& f_error(23)& f_error(23)& f_error(23)& f_error(23 downto 8)) when "1000", (f_error(23)& f_error(23)& f_error(23)& f_error(23)& f_error(23)& f_error(23)& f_error(23)& f_error(23)& f_error(23) & f_error(23 downto 9)) when "1001", (f_error(23)& f_error(23)& f_error(23)& f_error(23)& f_error(23)& f_error(23)& f_error(23)& f_error(23)& f_error(23) & f_error(23) & f_error(23 downto 10)) when "1010", (f_error(23)& f_error(23)& f_error(23)& f_error(23)& f_error(23)& f_error(23)& f_error(23)& f_error(23)& f_error(23) & f_error(23) & f_error(23) & f_error(23 downto 11)) when "1011", (f_error(23)& f_error(23)& f_error(23)& f_error(23)& f_error(23)& f_error(23)& f_error(23)& f_error(23)& f_error(23) & f_error(23) & f_error(23) & f_error(23) & f_error(23 downto 12)) when "1100", (f_error(23)& f_error(23)& f_error(23)& f_error(23)& f_error(23)& f_error(23)& f_error(23)& f_error(23)& f_error(23) & f_error(23) & f_error(23) & f_error(23) & f_error(23) & f_error(23 downto 13)) when "1101", (f_error(23)& f_error(23)& f_error(23)& f_error(23)& f_error(23)& f_error(23)& f_error(23)& f_error(23)& f_error(23) & f_error(23) & f_error(23) & f_error(23) & f_error(23) & f_error(23) & f_error(23 downto 14)) when "1110", (f_error(23)& f_error(23)& f_error(23)& f_error(23)& f_error(23)& f_error(23)& f_error(23)& f_error(23)& f_error(23) & f_error(23) & f_error(23) & f_error(23) & f_error(23) & f_error(23) & f_error(23) & f_error(23 downto 15)) when "1111", f_error(23 downto 0) when others; --************************************************************************************************************** --************************* injection counter ************************************************* --************************************************************************************************************** INJ_cnt_en <= inj_trig_rising; process(clk) begin if rising_edge(clk) then if INJ_cnt_rst = '1' or reset = '1' then INJ_cnt <= (others=>'0'); elsif INJ_cnt_en = '1' then INJ_cnt <= INJ_cnt + '1'; end if; end if; end process; --************************************************************************************************************** --************************* Generation of phase table number ************************************************* --************************************************************************************************************** PhaseTable_cnt_rst <= inj_trig_rising; process(clk) begin if rising_edge(clk) then if PhaseTable_cnt_rst = '1' or reset = '1' then PhaseTable_cnt <= (others=>'0'); elsif change_PT = '1' and change_PT_en = '1' then PhaseTable_cnt <= PhaseTable_cnt + '1'; end if; end if; end process; ph_table_addr(12 downto 9) <= PhaseTable_cnt; --************************************************************************************************************** --************************* Generation of SDRAM address ************************************************* --************************************************************************************************************** SDRAM_Addr_cnt_en <= result_valid; write_SDRAM <= result_valid; process(clk) begin if rising_edge(clk) then if reset = '1' then SDRAM_Addr_cnt <= (others=>'0'); elsif SDRAM_Addr_cnt_en = '1' then SDRAM_Addr_cnt <= SDRAM_Addr_cnt + '1'; SDRAM_ADDR_OUT <= SDRAM_Addr_cnt; --store valid address end if; end if; end process; inj_num <= '0' & INJ_cnt & "00"; C_tab_wr_dat <= inj_num & SDRAM_Addr_cnt; ST_tab_wr_dat <= inj_num & SDRAM_Addr_cnt; HC_tab_wr_dat <= inj_num & SDRAM_Addr_cnt; --************************************************************************************************************** --**************************** POINTER MOMORIES *************************************************** --************************************************************************************************************** C_TABLE : dpram8192x32 port map ( addra => C_TAB_RD_ADDR, addrb => C_tab_wr_addr, clka => clk, clkb => clk, dinb => C_tab_wr_dat, douta => C_TAB_RD_DAT, web => C_tab_wen ); ST_TABLE : dpram8x32 port map ( addra => ST_TAB_RD_ADDR, addrb => ST_tab_wr_addr, clka => clk, clkb => clk, dinb => ST_tab_wr_dat, douta => ST_TAB_RD_DAT, web => ST_tab_wen ); HC_TABLE : dpram32x32 port map ( addra => HC_TAB_RD_ADDR, addrb => HC_tab_wr_addr, clka => clk, clkb => clk, dinb => HC_tab_wr_dat, douta => HC_TAB_RD_DAT, web => HC_tab_wen ); INJ_TABLE : dpram8x32 port map ( addra => INJ_TAB_RD_ADDR, addrb => INJ_tab_wr_addr, clka => clk, clkb => clk, dinb => INJ_tab_wr_dat, douta => INJ_TAB_RD_DAT, web => INJ_tab_wen ); ST_tab_addr_cnt_en <= ST_timing_rising; HC_tab_addr_cnt_en <= change_PT; C_tab_addr_cnt_en <= C_timing; INJ_tab_addr_cnt_en <= inj_trig_rising; --pointer tables address counters process(clk,reset) begin if rising_edge(clk) then if reset = '1' then ST_tab_addr_cnt <= (others=>'0'); elsif ST_tab_addr_cnt_en = '1' then ST_tab_addr_cnt <= ST_tab_addr_cnt + '1'; end if; if reset = '1' then HC_tab_addr_cnt <= (others=>'0'); elsif HC_tab_addr_cnt_en = '1' then HC_tab_addr_cnt <= HC_tab_addr_cnt + '1'; end if; if reset = '1' then C_tab_addr_cnt <= (others=>'0'); elsif C_tab_addr_cnt_en = '1' then C_tab_addr_cnt <= C_tab_addr_cnt + '1'; end if; if reset = '1' then INJ_tab_addr_cnt <= (others=>'0'); elsif INJ_tab_addr_cnt_en = '1' then INJ_tab_addr_cnt <= INJ_tab_addr_cnt + '1'; end if; end if; end process; ST_tab_wr_addr <= ST_tab_addr_cnt; HC_tab_wr_addr <= HC_tab_addr_cnt; C_tab_wr_addr <= C_tab_addr_cnt; process(clk,reset) begin if rising_edge(clk) then if reset = '1' then ST_tab_ST_addr <= (others=>'0'); HC_tab_ST_addr <= (others=>'0'); C_tab_ST_addr <= (others=>'0'); INJ_tab_ST_addr <= (others=>'0'); SDRAM_ST_addr <= (others=>'0'); elsif ST_timing_rising = '1' then ST_tab_ST_addr <= ST_tab_addr_cnt; HC_tab_ST_addr <= HC_tab_addr_cnt; C_tab_ST_addr <= C_tab_addr_cnt; INJ_tab_ST_addr <= INJ_tab_addr_cnt; SDRAM_ST_addr <= SDRAM_Addr_cnt; end if; end if; end process; --************************************************************************************************************** --**************************** synchronisation state machine *************************************************** --************************************************************************************************************** PROCESS (clk, init) BEGIN IF init = '1' THEN state_synch <= idle_synch; ELSIF rising_edge(clk) THEN CASE state_synch IS WHEN idle_synch => IF inj_trig_rising ='1' THEN state_synch <= wait_frev; END IF; WHEN wait_frev=> IF F_rev_rising ='1' THEN state_synch <= wait_beam; END IF; When wait_beam => IF PT_MSB_rising ='1' THEN state_synch <= start_acq; END IF; WHEN start_acq=> IF ELFT_in ='1' THEN state_synch <= stop_acq; END if; WHEN stop_acq => state_synch <= idle_synch ; END CASE; END IF; END PROCESS; WITH state_synch SELECT LO_delay_count_enable <= '1' WHEN wait_beam, '0' WHEN others; WITH state_synch SELECT LO_delay_load <= '1' WHEN wait_frev, '0' WHEN others; WITH state_synch SELECT measurements_valid <= '1' WHEN start_acq, '0' WHEN others; --WITH state_synch SELECT -- sig_PU_sel <= '1' WHEN start_acq, -- '0' WHEN others; result_Write_en <= sig_PU_sel; phtable_sel <= '0' ; sig_PU_sel <= '1'; --**************************** detection of incoming HC timing pulse ****************************** --**************************** and synchronisation with C timing ****************************** --**************************** generation of change_PT signal ****************************** PROCESS (CLK,init) BEGIN IF (CLK'EVENT AND CLK = '1') THEN --reset if init = '1' or inj_trig_rising = '1' then HC_synch <= '0'; HC_temp <= '0'; end if; -- synchronise HC timing with C_timing to generate HC_synch if HC_timing_rising = '1' then HC_temp <= '1'; end if; if C_timing = '1' and HC_temp = '1' then HC_synch <= '1'; end if; --generate Phase Table change signal --HC_synch is HIGH until the end of phasetatable. if PT_MSB_rising = '1' and HC_synch = '1' then change_PT <= '1'; end if; --clear PT immediately if change_PT = '1' then change_PT <= '0'; HC_synch <= '0'; end if; END IF; END PROCESS; --************************************************************************************************************** --************************* Generation of internal C-timing ************************************************* --************************************************************************************************************** -- division of 125MHz system clock /125000 to get 1 KHz timing C_timer_load <= inj_trig_rising; PROCESS (CLK,C_timer_load,C_timer_count) BEGIN IF (CLK'EVENT AND CLK = '1') THEN if C_timer_load = '1' then C_timer_count <= C_timer_val; C_timer_stop <= '0'; elsif C_timer_stop = '0' then C_timer_count <= C_timer_count - 1; end if; if C_timer_count = x"0000" then C_timer_stop<='1'; else C_timer_stop<='0'; end if; END IF; END PROCESS; C_timing <= C_timer_stop; --**************************** LO delay counter *************************************************** --counts phasetable turns to indicate proper phase of the system to start acquisition PROCESS (clk,LO_delay_count) BEGIN IF (CLK'EVENT AND CLK = '1') THEN if LO_delay_load = '1' then LO_delay_count <= LO_delay; LO_delay_stop <= '0'; elsif LO_delay_count_enable = '1' and LO_delay_stop = '0' and PT_MSB_rising = '1' then LO_delay_count <= LO_delay_count - 1; end if; END IF; if LO_delay_count = x"00" then LO_delay_stop<='1'; else LO_delay_stop<='0'; end if; END PROCESS; --************************************************************************************************************** --**************************** pulses edge detection *************************************************** --************************************************************************************************************** --ST_timing_in process (clk, init) begin -- process if init = '0' then -- asynchronous reset (active low) inj_trig_edg_det <= "00"; HC_tim_edg_det <= "00"; F_rev_edg_det <= "00"; PT_MSB_edg_det <= "00"; elsif clk'event and clk = '1' then -- rising clock edge inj_trig_edg_det(0) <= inject_trig; inj_trig_edg_det(1) <= inj_trig_edg_det(0); inj_trig_rising <= inj_trig_edg_det(0) and not inj_trig_edg_det(1); HC_tim_edg_det(0) <= HC_timing_in; HC_tim_edg_det(1) <= HC_tim_edg_det(0); HC_timing_rising <= HC_tim_edg_det(0) and not HC_tim_edg_det(1); F_rev_edg_det(0) <= F_rev_in; F_rev_edg_det(1) <= F_rev_edg_det(0); F_rev_rising <= F_rev_edg_det(0) and not F_rev_edg_det(1); PT_MSB_edg_det(0) <= ph_table_addr(8); PT_MSB_edg_det(1) <= PT_MSB_edg_det(0); PT_MSB_rising <= PT_MSB_edg_det(0) and not PT_MSB_edg_det(1); ST_edg_det(0) <= ST_timing_in; ST_edg_det(1) <= ST_edg_det(0); ST_timing_rising <= ST_edg_det(0) and not ST_edg_det(1); end if; end process; --************************************************************************************************************** --**************************** Input signal selection ****************************************************** --************************************************************************************************************** --selection of algorithm input signal mul_data_in <= adc_a_i when sig_PU_sel = '1' else Frev_num; --generation of bipolar revolution frequency word Frev_num <= frev_gain when F_rev_in = '0' else (- frev_gain); --************************************************************************************************************** --**************************** DDS ****************************************************** --************************************************************************************************************** f_error_dds <= F_ERR(23) & F_ERR(23) & F_ERR(23) & F_ERR(23) & F_ERR(23) & F_ERR(23) & F_ERR(23) & F_ERR(23) & F_ERR(23 downto 0) ; process(clk) begin if rising_edge(clk) then clk62<= not clk62; end if; end process; process(clk,init,freq_init) begin if init='1' then dds_ph<=(others=>'0'); dds_freq<=freq_init; dds_freq_OVR <= '0'; dds_freq_UR <= '0'; elsif rising_edge(clk) then if clk62 = '1' then dds_ph <= dds_ph + dds_freq; if dds_freq > dds_freq_max then dds_freq_OVR <= '1'; dds_freq_UR <= '0'; elsif dds_freq < dds_freq_min then dds_freq_OVR <= '0'; dds_freq_UR <= '1'; end if; if load_dds_freq = '1' then dds_freq<=dds_freq_limit; elsif loop_ctrl = '0' then --dds_freq<=dds_freq- f_error(23 downto 0) ; dds_freq<=dds_freq - f_error_dds; dds_freq_OVR <= '0'; dds_freq_UR <= '0'; end if; end if; end if; end process; dds_freq_limit <= dds_freq_max when dds_freq_OVR = '1' else dds_freq_min; load_dds_freq <= dds_freq_limit_en and (dds_freq_OVR or dds_freq_UR); ph_table_addr(8 downto 0) <= dds_ph(31 downto 23) + ph_init; --************************************************************************************************************** --**************************** multiplier ****************************************************** --************************************************************************************************************** --multiplier function call mult_neg_data_in<= (not mul_data_in) + '1'; mult_out <= mul_data_in when LO_pulse='0' else mult_neg_data_in; process(clk) begin if rising_edge(clk) then filter1_in <= mult_out(13) & mult_out(13) & mult_out(13) & mult_out(13) & mult_out(13) & mult_out(13) & mult_out(13) & mult_out(13) & mult_out(13) & mult_out(13) & mult_out ; end if; end process; --************************************************************************************************************** --**************************** filter ****************************************************** --************************************************************************************************************** n1<= filter1_in(13) & filter1_in(13) & filter1_in(13) & filter1_in(13) & filter1_in(13)& filter1_in(13) & filter1_in(13) & filter1_in(13) & filter1_in(13) & filter1_in(13) & filter1_in(13 downto 0); process(clk,init) begin if rising_edge(clk) then if init = '1' then n2 <=x"000000"; n3 <=x"000000"; n4 <=x"000000"; n5 <=x"000000"; n6 <=x"000000"; s4 <=x"000000"; s6 <=x"000000"; -- else elsif clk62 = '1' then n2 <= n1 + n2 - (n2(23) & n2(23) & n2(23) & n2(23) & n2(23) & n2(23) & n2(23) & n2(23) & n2(23 downto 8)); n3 <= n2 + n3 - (n3(23) & n3(23) & n3(23) & n3(23) & n3(23) & n3(23) & n3(23) & n3(23) & n3(23 downto 8)); s4 <= n3 - (n3(23) & n3(23) & n3(23) & n3(23) & n3(23) & n3(23) & n3(23) & n3(23) & n3(23) & n3(23) & n3(23 downto 10)); -- s3 <= n3; --pipeline delay n4 <= n3 - s4; n5 <= n4 + n5 - (n5(23) & n5(23) & n5(23) & n5(23) & n5(23) & n5(23) & n5(23) & n5(23) & n5(23 downto 8)); s6 <= n5 - (n5(23) & n5(23) & n5(23) & n5(23) & n5(23) & n5(23) & n5(23) & n5(23) & n5(23) & n5(23) & n5(23 downto 10)); -- s5 <= n5; --pipeline delay n6 <= n5 - s6; end if; end if; end process; filter_data_out <= n6(23 downto 0); f_error <= filter_data_out; --************************************************************************************************************** --**************************** PHASE TABLE ****************************************************** --************************************************************************************************************** ph_table_0 : phasetable port map ( addra => phase_addr_in, addrb => ph_table_addr, clka => clk, clkb => clk, dina => phase_data_in(3 downto 0), doutb => ram_out_0(3 downto 0), wea => write_enable_0 ); ph_table_1 : phasetable port map ( addra => phase_addr_in, addrb => ph_table_addr, clka => clk, clkb => clk, dina => phase_data_in(3 downto 0), doutb => ram_out_1(3 downto 0), wea => write_enable_1 ); ram_out <= ram_out_0 when phtable_sel = '0' else ram_out_1; write_enable_0 <= write_enable when phtable_sel = '0' else '0'; write_enable_1 <= write_enable when phtable_sel = '1' else '0'; LO_out <= ram_out(0); LO_pulse <= ram_out(0); BLR_pulse <= ram_out(1); GATE_pulse <= ram_out(2); --************************************************************************************************************** --**************************** INTEGRATORS ****************************************************** --************************************************************************************************************** process(clk) begin if rising_edge(clk) then if acc_reset = '1' then accumulate_0 <= x"000000"; accumulate_1 <= x"000000"; accumulate_2 <= x"000000"; elsif GATE_PULSE = '1' then accumulate_0 <= accumulate_0 + BLR_data_out_0; accumulate_1 <= accumulate_1 + BLR_data_out_1; accumulate_2 <= accumulate_2 + BLR_data_out_2; end if; end if; end process; PROCESS (clk, init) BEGIN IF init = '1' THEN state <= idle; ELSIF rising_edge(clk) THEN CASE state IS WHEN idle => IF GATE_PULSE ='1' THEN state <= integrate; else state <= idle; END IF; WHEN integrate=> IF GATE_PULSE ='1' THEN state <= integrate; else state <= ready; END IF; WHEN ready=> state <= reset_acc; WHEN reset_acc => state <= idle ; END CASE; END IF; END PROCESS; WITH state SELECT acc_reset <= '1' WHEN ready, '0' WHEN others; WITH state SELECT result_valid <= result_Write_en WHEN reset_acc, '0' WHEN others; process(clk) begin if rising_edge(clk) then if state = ready then result0_tmp <= accumulate_0; result1_tmp <= accumulate_1; result2_tmp <= accumulate_2; end if; end if; end process; result_0 <= result0_tmp; result_1 <= result1_tmp; result_2 <= result2_tmp; --************************************************************************************************************** --**************************** BASELINE RESTORATION ********************************************** --************************************************************************************************************** BLR_data_in_0(23 downto 14) <= (others => adc_a_i(13) ); BLR_data_in_0(13 downto 0) <= adc_a_i; BLR_data_in_1(23 downto 14) <= (others => adc_b_i(13) ); BLR_data_in_1(13 downto 0) <= adc_b_i; BLR_data_in_2(23 downto 14) <= (others => adc_c_i(13) ); BLR_data_in_2(13 downto 0) <= adc_c_i; --accumulate e process(clk,init) begin if init = '1' then e0 <= (others=>'0'); e1 <= (others=>'0'); e2 <= (others=>'0'); b0 <= (others=>'0'); b1 <= (others=>'0'); b2 <= (others=>'0'); y0 <= (others=>'0'); y1 <= (others=>'0'); y2 <= (others=>'0'); x0 <= (others=>'0'); x1 <= (others=>'0'); x2 <= (others=>'0'); elsif rising_edge(clk) then --accumulate e x0 <= BLR_data_in_0 - b0; x1 <= BLR_data_in_1 - b1; x2 <= BLR_data_in_2 - b2; e0 <= e0+x0; e1 <= e1+x1; e2 <= e2+x2; y0 <= x0 +(e0(23) & e0(23)& e0(23) & e0(23) & e0(23) & e0(23) & e0(23) & e0(23 downto 7)); y1 <= x1 +(e1(23) & e1(23)& e1(23) & e1(23) & e1(23) & e1(23) & e1(23) & e1(23 downto 7)); y2 <= x2 +(e2(23) & e2(23)& e2(23) & e2(23) & e2(23) & e2(23) & e2(23) & e2(23 downto 7)); if BLR_pulse = '1' then b0 <= b0 + ( y0(23) & y0(23) & y0(23 downto 2)); b1 <= b1 + ( y1(23) & y1(23) & y1(23 downto 2)); b2 <= b2 + ( y2(23) & y2(23) & y2(23 downto 2)); end if; end if; end process; BLR_data_out_0 <= y0; BLR_data_out_1 <= y1; BLR_data_out_2 <= y2; --************************************************************************************************************** --**************************** CHIPSCOPE ANALYSER ********************************************** --************************************************************************************************************** data_ch0(19 downto 0) <=filter_data_out(19 downto 0); data_ch0(43 downto 20) <=dds_freq(23 downto 0); data_ch0(57 downto 44) <=adc_a_i; data_ch0(58) <=LO_pulse; data_ch0(72 downto 59) <=mult_out; data_ch0(95 downto 73) <=F_ERR(22 downto 0); data_alt_ch0(15 downto 0) <=result0_tmp(15 downto 0); data_alt_ch0(16) <= BLR_pulse; data_alt_ch0(17) <= acc_reset; data_alt_ch0(18) <= result_valid; data_alt_ch0(19) <= GATE_PULSE; data_alt_ch0(43 downto 20) <=BLR_data_out_0(23 downto 0); data_alt_ch0(57 downto 44) <=adc_a_i; data_alt_ch0(58) <=LO_pulse; data_alt_ch0(72 downto 59) <=mult_out; data_alt_ch0(95 downto 73) <=F_ERR(22 downto 0); data_ch1(15 downto 0) <= F_ERR(15 downto 0); data_ch1(47 downto 16) <= dds_freq(31 downto 0); data_alt_ch1 (15 downto 0) <= result0_tmp(15 downto 0); data_alt_ch1 (31 downto 16)<= result1_tmp(15 downto 0); data_alt_ch1 (47 downto 32)<= result2_tmp(15 downto 0); async_port_i <= dds_freq; control_port_i <= (others => '0'); trig_ch0(0)<= loop_ctrl; trig_ch0(1)<= init; trig_ch0(2)<= write_enable; trig_ch0(3)<= init; trig_ch1(0)<= loop_ctrl; trig_ch1(1)<= init; trig_ch1(2)<= write_enable; trig_ch1(3)<= init; chipscope : chipscope_analyser port map ( data_ch0 => data_ch0, data_ch1 => data_ch1, clk => clk, clk_ext => result_valid, reset => reset, trig_ch0 => trig_ch0, trig_ch1 => trig_ch1, control_port_i => control_port_i, async_port_i => async_port_i, control_port_o => OPEN , data_alt_ch0 => data_alt_ch0, data_alt_ch1 => data_alt_ch1 ); --************************************************************************************************************** --**************************** EMBEDDED SIGNAL ANALYSER ********************************************** --************************************************************************************************************** data_0 <= dds_freq; data_1 <= LO_pulse & BLR_pulse & adc_a_i & "00" & adc_b_i; data_2 <= LO_pulse & GATE_pulse & mult_out & "00" & adc_c_i; data_3 <= x"00" & F_ERR; data_4(23 downto 0) <= result0_tmp; data_4(31 downto 24) <= (others =>result0_tmp(23)); data_5(23 downto 0) <= result1_tmp; data_5(31 downto 24) <= (others =>result1_tmp(23)); data_6(23 downto 0) <= result2_tmp; data_6(31 downto 24) <= (others =>result2_tmp(23)); data_7 <= x"00000000"; ANA_trig(0) <= loop_ctrl; ANA_trig(1) <= write_enable; ANA_trig(2) <= init; ANA_trig(3) <= ELFT_in; ANA_trig(4) <= inject_trig; ANA_trig(5) <= F_rev_in; ANA_trig(6) <= HC_timing_in; ANA_trig(7) <= ST_timing_in; -- sig_analyser: analyser -- Port map( -- clk => clk, -- reset => reset, -- ANA_record_len => ANA_record_len, -- ANA_addr_pointer => ANA_addr_pointer, -- ANA_RD_addr => ANA_RD_addr, -- ANA_RD_DAT => ANA_RD_DAT, -- ANA_slope => ANA_slope, -- ANA_ARM => ANA_ARM, -- ANA_timer_en => ANA_timer_en, -- ANA_DATA_ACQUIRED => ANA_DATA_ACQUIRED, -- ANA_trig => ANA_trig, -- data_0 => data_0, -- data_1 => data_1, -- data_2 => data_2, -- data_3 => data_3, -- data_4 => data_4, -- data_5 => data_5, -- data_6 => data_6, -- data_7 => data_7, -- ANA_trig_src => ANA_trig_src, -- ANA_CH1_src => ANA_CH1_src, -- ANA_CH2_src => ANA_CH2_src, -- ANA_timer => ANA_timer, -- ANA_delay => ANA_delay -- ); end BEHAVIORAL;