Release 8.1i - xst I.24 Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved. --> Parameter TMPDIR set to ./xst/projnav.tmp CPU : 0.00 / 0.27 s | Elapsed : 0.00 / 0.00 s --> Parameter xsthdpdir set to ./xst CPU : 0.00 / 0.27 s | Elapsed : 0.00 / 0.00 s --> Reading design: pll3.prj TABLE OF CONTENTS 1) Synthesis Options Summary 2) HDL Compilation 3) HDL Analysis 4) HDL Synthesis 4.1) HDL Synthesis Report 5) Advanced HDL Synthesis 5.1) Advanced HDL Synthesis Report 6) Low Level Synthesis 7) Final Report 7.1) Device utilization summary 7.2) TIMING REPORT ========================================================================= * Synthesis Options Summary * ========================================================================= ---- Source Parameters Input File Name : "pll3.prj" Input Format : mixed Ignore Synthesis Constraint File : NO ---- Target Parameters Output File Name : "pll3" Output Format : NGC Target Device : xc2vp30-6-ff1152 ---- Source Options Top Module Name : pll3 Automatic FSM Extraction : YES FSM Encoding Algorithm : Auto FSM Style : lut RAM Extraction : Yes RAM Style : Auto ROM Extraction : Yes Mux Style : Auto Decoder Extraction : YES Priority Encoder Extraction : YES Shift Register Extraction : YES Logical Shifter Extraction : YES XOR Collapsing : YES ROM Style : Auto Mux Extraction : YES Resource Sharing : YES Multiplier Style : auto Automatic Register Balancing : No ---- Target Options Add IO Buffers : YES Global Maximum Fanout : 500 Add Generic Clock Buffer(BUFG) : 16 Register Duplication : YES Slice Packing : YES Pack IO Registers into IOBs : auto Equivalent register Removal : YES ---- General Options Optimization Goal : Speed Optimization Effort : 1 Keep Hierarchy : NO RTL Output : Yes Global Optimization : AllClockNets Write Timing Constraints : NO Hierarchy Separator : / Bus Delimiter : <> Case Specifier : maintain Slice Utilization Ratio : 100 Slice Utilization Ratio Delta : 5 ---- Other Options lso : pll3.lso Read Cores : YES cross_clock_analysis : NO verilog2001 : YES safe_implementation : No Optimize Instantiated Primitives : NO tristate2logic : Yes use_clock_enable : Yes use_sync_set : Yes use_sync_reset : Yes ========================================================================= ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file "C:/DESIGNS/FPGA/Custom_Libera/chipscope_analyser.vhd" in Library work. Architecture behavioral of Entity chipscope_analyser is up to date. Compiling vhdl file "C:/DESIGNS/FPGA/Custom_Libera/pll3.vhd" in Library work. Architecture behavioral of Entity pll3 is up to date. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity (Architecture ). WARNING:Xst:819 - "C:/DESIGNS/FPGA/Custom_Libera/pll3.vhd" line 156: The following signals are missing in the process sensitivity list: freq_init. WARNING:Xst:766 - "C:/DESIGNS/FPGA/Custom_Libera/pll3.vhd" line 242: Generating a Black Box for component . Entity analyzed. Unit generated. Analyzing Entity (Architecture ). WARNING:Xst:766 - "C:/DESIGNS/FPGA/Custom_Libera/chipscope_analyser.vhd" line 153: Generating a Black Box for component . WARNING:Xst:766 - "C:/DESIGNS/FPGA/Custom_Libera/chipscope_analyser.vhd" line 167: Generating a Black Box for component . WARNING:Xst:766 - "C:/DESIGNS/FPGA/Custom_Libera/chipscope_analyser.vhd" line 183: Generating a Black Box for component . WARNING:Xst:766 - "C:/DESIGNS/FPGA/Custom_Libera/chipscope_analyser.vhd" line 200: Generating a Black Box for component . WARNING:Xst:766 - "C:/DESIGNS/FPGA/Custom_Libera/chipscope_analyser.vhd" line 216: Generating a Black Box for component . WARNING:Xst:819 - "C:/DESIGNS/FPGA/Custom_Libera/chipscope_analyser.vhd" line 232: The following signals are missing in the process sensitivity list: timer. Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is "C:/DESIGNS/FPGA/Custom_Libera/chipscope_analyser.vhd". WARNING:Xst:647 - Input is never used. WARNING:Xst:647 - Input is never used. WARNING:Xst:653 - Signal is used but never assigned. Tied to value 0000. WARNING:Xst:653 - Signal is used but never assigned. Tied to value 0000. WARNING:Xst:646 - Signal > is assigned but never used. Found 24-bit down counter for signal . Summary: inferred 1 Counter(s). Unit synthesized. Synthesizing Unit . Related source file is "C:/DESIGNS/FPGA/Custom_Libera/pll3.vhd". WARNING:Xst:647 - Input > is never used. WARNING:Xst:653 - Signal is used but never assigned. Tied to value 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000. WARNING:Xst:653 - Signal is used but never assigned. Tied to value 000000000000000000000000000000000000000000000000. WARNING:Xst:653 - Signal is used but never assigned. Tied to value 00000000000000000000000000000000. WARNING:Xst:646 - Signal > is assigned but never used. WARNING:Xst:1780 - Signal is never used or assigned. WARNING:Xst:1780 - Signal is never used or assigned. WARNING:Xst:653 - Signal is used but never assigned. Tied to value 0000. WARNING:Xst:653 - Signal is used but never assigned. Tied to value 0000. WARNING:Xst:646 - Signal > is assigned but never used. WARNING:Xst:653 - Signal is used but never assigned. Tied to value 00000000000000000000000000000000. WARNING:Xst:646 - Signal is assigned but never used. WARNING:Xst:653 - Signal is used but never assigned. Tied to value 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000. WARNING:Xst:653 - Signal is used but never assigned. Tied to value 000000000000000000000000000000000000000000000000. WARNING:Xst:646 - Signal > is assigned but never used. Found finite state machine for signal . ----------------------------------------------------------------------- | States | 4 | | Transitions | 6 | | Inputs | 1 | | Outputs | 2 | | Clock | clk (rising_edge) | | Reset | init (positive) | | Reset type | asynchronous | | Reset State | idle | | Power Up State | idle | | Encoding | automatic | | Implementation | LUT | ----------------------------------------------------------------------- Found 32-bit register for signal . Found 32-bit register for signal . Found 32-bit register for signal . Found 24-bit subtractor for signal <$n0013> created at line 218. Found 24-bit subtractor for signal <$n0014> created at line 219. Found 24-bit subtractor for signal <$n0015> created at line 222. Found 24-bit subtractor for signal <$n0016> created at line 223. Found 24-bit subtractor for signal <$n0017> created at line 226. Found 24-bit subtractor for signal <$n0018> created at line 220. Found 24-bit subtractor for signal <$n0019> created at line 224. Found 24-bit subtractor for signal <$n0020> created at line 364. Found 24-bit subtractor for signal <$n0021> created at line 365. Found 24-bit subtractor for signal <$n0022> created at line 366. Found 24-bit adder for signal <$n0023> created at line 370. Found 24-bit adder for signal <$n0024> created at line 371. Found 24-bit adder for signal <$n0025> created at line 372. Found 24-bit adder for signal <$n0026> created at line 218. Found 24-bit adder for signal <$n0027> created at line 219. Found 24-bit adder for signal <$n0028> created at line 223. Found 32-bit up accumulator for signal . Found 32-bit up accumulator for signal . Found 32-bit up accumulator for signal . Found 24-bit up accumulator for signal . Found 24-bit up accumulator for signal . Found 24-bit up accumulator for signal . Found 24-bit down accumulator for signal . Found 24-bit up accumulator for signal . Found 24-bit up accumulator for signal . Found 24-bit up accumulator for signal . Found 24-bit up accumulator for signal . Found 24-bit shifter arithmetic right for signal . Found 14-bit adder for signal . Found 24-bit register for signal . Found 24-bit register for signal . Found 24-bit register for signal . Found 24-bit register for signal . Found 24-bit register for signal . Found 9-bit adder for signal . Found 24-bit register for signal . Found 24-bit register for signal . Found 24-bit register for signal . Found 24-bit register for signal . Found 24-bit register for signal . Found 24-bit register for signal . Found 24-bit register for signal . Found 24-bit register for signal . Summary: inferred 1 Finite State Machine(s). inferred 11 Accumulator(s). inferred 408 D-type flip-flop(s). inferred 18 Adder/Subtractor(s). inferred 1 Combinational logic shifter(s). Unit synthesized. ========================================================================= HDL Synthesis Report Macro Statistics # Adders/Subtractors : 18 14-bit adder : 1 24-bit adder : 6 24-bit subtractor : 10 9-bit adder : 1 # Counters : 1 24-bit down counter : 1 # Accumulators : 11 24-bit down accumulator : 1 24-bit up accumulator : 7 32-bit up accumulator : 3 # Registers : 16 24-bit register : 13 32-bit register : 3 # Logic shifters : 1 24-bit shifter arithmetic right : 1 ========================================================================= ========================================================================= * Advanced HDL Synthesis * ========================================================================= Analyzing FSM for best encoding. Optimizing FSM on signal with gray encoding. ----------------------- State | Encoding ----------------------- idle | 00 integrate | 01 ready | 11 reset_acc | 10 ----------------------- Reading module "rom512x4.ngo" ( "rom512x4.ngo" unchanged since last run )... Reading module "icon.ngo" ( "icon.ngo" unchanged since last run )... Reading module "vio_control.ngo" ( "vio_control.ngo" unchanged since last run )... Reading module "vio.ngo" ( "vio.ngo" unchanged since last run )... Executing edif2ngd -noa "ila_6CH.edn" "ila_6CH.ngo" Release 8.1i - edif2ngd I.24 Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved. INFO:NgdBuild - Release 8.1i edif2ngd I.24 INFO:NgdBuild - Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved. Applying constraints in "ila_6CH.ncf" to module "ila_6CH"... Writing module to "ila_6CH.ngo"... Executing edif2ngd -noa "ila_2CH.edn" "ila_2CH.ngo" Release 8.1i - edif2ngd I.24 Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved. INFO:NgdBuild - Release 8.1i edif2ngd I.24 INFO:NgdBuild - Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved. Applying constraints in "ila_2CH.ncf" to module "ila_2CH"... Writing module to "ila_2CH.ngo"... Loading core for timing and area information for instance . WARNING:Xst:1474 - Core was not loaded for as one or more ports did not line up with component declaration. Declared output port > was not found in the core. Please make sure that component declaration ports are consistent with the core ports including direction and bus-naming conventions. WARNING:Xst:1474 - Core was not loaded for as one or more ports did not line up with component declaration. Declared input port > was not found in the core. Please make sure that component declaration ports are consistent with the core ports including direction and bus-naming conventions. WARNING:Xst:1474 - Core was not loaded for as one or more ports did not line up with component declaration. Declared input port > was not found in the core. Please make sure that component declaration ports are consistent with the core ports including direction and bus-naming conventions. WARNING:Xst:1474 - Core was not loaded for as one or more ports did not line up with component declaration. Declared input port > was not found in the core. Please make sure that component declaration ports are consistent with the core ports including direction and bus-naming conventions. WARNING:Xst:1474 - Core was not loaded for as one or more ports did not line up with component declaration. Declared input port > was not found in the core. Please make sure that component declaration ports are consistent with the core ports including direction and bus-naming conventions. WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . ========================================================================= Advanced HDL Synthesis Report Macro Statistics # FSMs : 1 # Adders/Subtractors : 18 14-bit adder : 1 24-bit adder : 6 24-bit subtractor : 10 9-bit adder : 1 # Counters : 1 24-bit down counter : 1 # Accumulators : 11 24-bit down accumulator : 1 24-bit up accumulator : 7 32-bit up accumulator : 3 # Registers : 404 Flip-Flops : 404 # Logic shifters : 1 24-bit shifter arithmetic right : 1 ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= Loading device for application Rf_Device from file '2vp30.nph' in environment C:\Xilinx. Optimizing unit ... Optimizing unit ... Mapping all equations... Building and optimizing final netlist ... Found area constraint ratio of 100 (+ 5) on block pll3, actual ratio is 3. FlipFlop n6_23 has been replicated 1 time(s) ========================================================================= * Final Report * ========================================================================= Final Results RTL Top Level Output File Name : pll3.ngr Top Level Output File Name : pll3 Output Format : NGC Optimization Goal : Speed Keep Hierarchy : NO Design Statistics # IOs : 194 Cell Usage : # BELS : 2306 # BUF : 1 # GND : 2 # INV : 67 # LUT1 : 29 # LUT1_L : 9 # LUT2 : 519 # LUT2_D : 3 # LUT2_L : 115 # LUT3 : 46 # LUT3_D : 2 # LUT3_L : 51 # LUT4 : 19 # LUT4_L : 37 # MUXCY : 695 # MUXF5 : 15 # VCC : 2 # XORCY : 694 # FlipFlops/Latches : 716 # FDC : 242 # FDC_1 : 23 # FDCE : 72 # FDCPE : 24 # FDE : 96 # FDP_1 : 1 # FDR : 162 # FDRE : 96 # RAMS : 1 # RAMB16_S4_S4 : 1 # Clock Buffers : 1 # BUFGP : 1 # IO Buffers : 192 # IBUF : 95 # OBUF : 97 # Others : 5 # icon : 1 # ila_2CH : 1 # ila_6CH : 1 # vio : 1 # vio_control : 1 ========================================================================= Device utilization summary: --------------------------- Selected Device : 2vp30ff1152-6 Number of Slices: 493 out of 13696 3% Number of Slice Flip Flops: 716 out of 27392 2% Number of 4 input LUTs: 830 out of 27392 3% Number of bonded IOBs: 193 out of 644 29% Number of BRAMs: 1 out of 136 0% Number of GCLKs: 1 out of 16 6% ========================================================================= TIMING REPORT NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE. FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT GENERATED AFTER PLACE-and-ROUTE. Clock Information: ------------------ -----------------------------------+------------------------+-------+ Clock Signal | Clock buffer(FF name) | Load | -----------------------------------+------------------------+-------+ clk | BUFGP | 717 | -----------------------------------+------------------------+-------+ Timing Summary: --------------- Speed Grade: -6 Minimum period: 7.285ns (Maximum Frequency: 137.268MHz) Minimum input arrival time before clock: 8.606ns Maximum output required time after clock: 4.557ns Maximum combinational path delay: 2.034ns Timing Detail: -------------- All values displayed in nanoseconds (ns) ========================================================================= Timing constraint: Default period analysis for Clock 'clk' Clock period: 7.285ns (frequency: 137.268MHz) Total number of paths / destination ports: 64428 / 1083 ------------------------------------------------------------------------- Delay: 7.285ns (Levels of Logic = 30) Source: n6_19 (FF) Destination: dds_freq_23 (FF) Source Clock: clk rising Destination Clock: clk rising Data Path: n6_19 to dds_freq_23 Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ FDR:C->Q 4 0.374 0.629 n6_19 (n6_19) LUT3:I0->O 2 0.313 0.588 Mshift_F_ERR_Sh<12>1 (Mshift_F_ERR_Sh<12>) LUT3_L:I0->LO 1 0.313 0.000 Mshift_F_ERR_Sh<40>1_G (N5761) MUXF5:I1->O 2 0.340 0.473 Mshift_F_ERR_Sh<40>1 (Mshift_F_ERR_Sh<40>) LUT4:I2->O 1 0.313 0.506 Mshift_F_ERR_Result<0>68 (F_ERR<0>) LUT2_L:I1->LO 1 0.313 0.000 dds_freq_LPM_ACCUM_4__n0000<0>lut (dds_freq_N3) MUXCY:S->O 1 0.377 0.000 dds_freq_LPM_ACCUM_4__n0000<0>cy (dds_freq_LPM_ACCUM_4__n0000<0>_cyo) MUXCY:CI->O 1 0.042 0.000 dds_freq_LPM_ACCUM_4__n0000<1>cy (dds_freq_LPM_ACCUM_4__n0000<1>_cyo) MUXCY:CI->O 1 0.042 0.000 dds_freq_LPM_ACCUM_4__n0000<2>cy (dds_freq_LPM_ACCUM_4__n0000<2>_cyo) MUXCY:CI->O 1 0.042 0.000 dds_freq_LPM_ACCUM_4__n0000<3>cy (dds_freq_LPM_ACCUM_4__n0000<3>_cyo) MUXCY:CI->O 1 0.042 0.000 dds_freq_LPM_ACCUM_4__n0000<4>cy (dds_freq_LPM_ACCUM_4__n0000<4>_cyo) MUXCY:CI->O 1 0.042 0.000 dds_freq_LPM_ACCUM_4__n0000<5>cy (dds_freq_LPM_ACCUM_4__n0000<5>_cyo) MUXCY:CI->O 1 0.042 0.000 dds_freq_LPM_ACCUM_4__n0000<6>cy (dds_freq_LPM_ACCUM_4__n0000<6>_cyo) MUXCY:CI->O 1 0.042 0.000 dds_freq_LPM_ACCUM_4__n0000<7>cy (dds_freq_LPM_ACCUM_4__n0000<7>_cyo) MUXCY:CI->O 1 0.042 0.000 dds_freq_LPM_ACCUM_4__n0000<8>cy (dds_freq_LPM_ACCUM_4__n0000<8>_cyo) MUXCY:CI->O 1 0.042 0.000 dds_freq_LPM_ACCUM_4__n0000<9>cy (dds_freq_LPM_ACCUM_4__n0000<9>_cyo) MUXCY:CI->O 1 0.042 0.000 dds_freq_LPM_ACCUM_4__n0000<10>cy (dds_freq_LPM_ACCUM_4__n0000<10>_cyo) MUXCY:CI->O 1 0.042 0.000 dds_freq_LPM_ACCUM_4__n0000<11>cy (dds_freq_LPM_ACCUM_4__n0000<11>_cyo) MUXCY:CI->O 1 0.042 0.000 dds_freq_LPM_ACCUM_4__n0000<12>cy (dds_freq_LPM_ACCUM_4__n0000<12>_cyo) MUXCY:CI->O 1 0.042 0.000 dds_freq_LPM_ACCUM_4__n0000<13>cy (dds_freq_LPM_ACCUM_4__n0000<13>_cyo) MUXCY:CI->O 1 0.042 0.000 dds_freq_LPM_ACCUM_4__n0000<14>cy (dds_freq_LPM_ACCUM_4__n0000<14>_cyo) MUXCY:CI->O 1 0.042 0.000 dds_freq_LPM_ACCUM_4__n0000<15>cy (dds_freq_LPM_ACCUM_4__n0000<15>_cyo) MUXCY:CI->O 1 0.042 0.000 dds_freq_LPM_ACCUM_4__n0000<16>cy (dds_freq_LPM_ACCUM_4__n0000<16>_cyo) MUXCY:CI->O 1 0.042 0.000 dds_freq_LPM_ACCUM_4__n0000<17>cy (dds_freq_LPM_ACCUM_4__n0000<17>_cyo) MUXCY:CI->O 1 0.042 0.000 dds_freq_LPM_ACCUM_4__n0000<18>cy (dds_freq_LPM_ACCUM_4__n0000<18>_cyo) MUXCY:CI->O 1 0.041 0.000 dds_freq_LPM_ACCUM_4__n0000<19>cy (dds_freq_LPM_ACCUM_4__n0000<19>_cyo) MUXCY:CI->O 1 0.041 0.000 dds_freq_LPM_ACCUM_4__n0000<20>cy (dds_freq_LPM_ACCUM_4__n0000<20>_cyo) MUXCY:CI->O 1 0.041 0.000 dds_freq_LPM_ACCUM_4__n0000<21>cy (dds_freq_LPM_ACCUM_4__n0000<21>_cyo) MUXCY:CI->O 0 0.041 0.000 dds_freq_LPM_ACCUM_4__n0000<22>cy (dds_freq_LPM_ACCUM_4__n0000<22>_cyo) XORCY:CI->O 1 0.868 0.418 dds_freq_LPM_ACCUM_4__n0000<23>_xor (dds_freq__n0000<23>) LUT3_L:I2->LO 1 0.313 0.000 dds_freq__n0001<23>1 (dds_freq__n0001<23>) FDCPE:D 0.234 dds_freq_23 ---------------------------------------- Total 7.285ns (4.671ns logic, 2.614ns route) (64.1% logic, 35.9% route) ========================================================================= Timing constraint: Default OFFSET IN BEFORE for Clock 'clk' Total number of paths / destination ports: 61053 / 348 ------------------------------------------------------------------------- Offset: 8.606ns (Levels of Logic = 30) Source: adc_a_i<0> (PAD) Destination: n2_23 (FF) Destination Clock: clk rising Data Path: adc_a_i<0> to n2_23 Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ IBUF:I->O 3 0.919 0.610 adc_a_i_0_IBUF (adc_a_i_0_IBUF) LUT1:I0->O 1 0.313 0.000 adc_a_i_0_IBUF_rt (adc_a_i_0_IBUF_rt) MUXCY:S->O 1 0.377 0.000 pll3_mult_neg_data_in<0>cy (pll3_mult_neg_data_in<0>_cyo) MUXCY:CI->O 1 0.042 0.000 pll3_mult_neg_data_in<1>cy (pll3_mult_neg_data_in<1>_cyo) MUXCY:CI->O 1 0.042 0.000 pll3_mult_neg_data_in<2>cy (pll3_mult_neg_data_in<2>_cyo) MUXCY:CI->O 1 0.042 0.000 pll3_mult_neg_data_in<3>cy (pll3_mult_neg_data_in<3>_cyo) MUXCY:CI->O 1 0.042 0.000 pll3_mult_neg_data_in<4>cy (pll3_mult_neg_data_in<4>_cyo) MUXCY:CI->O 1 0.042 0.000 pll3_mult_neg_data_in<5>cy (pll3_mult_neg_data_in<5>_cyo) MUXCY:CI->O 1 0.042 0.000 pll3_mult_neg_data_in<6>cy (pll3_mult_neg_data_in<6>_cyo) MUXCY:CI->O 1 0.042 0.000 pll3_mult_neg_data_in<7>cy (pll3_mult_neg_data_in<7>_cyo) MUXCY:CI->O 1 0.042 0.000 pll3_mult_neg_data_in<8>cy (pll3_mult_neg_data_in<8>_cyo) MUXCY:CI->O 1 0.042 0.000 pll3_mult_neg_data_in<9>cy (pll3_mult_neg_data_in<9>_cyo) MUXCY:CI->O 1 0.042 0.000 pll3_mult_neg_data_in<10>cy (pll3_mult_neg_data_in<10>_cyo) MUXCY:CI->O 1 0.042 0.000 pll3_mult_neg_data_in<11>cy (pll3_mult_neg_data_in<11>_cyo) MUXCY:CI->O 0 0.042 0.000 pll3_mult_neg_data_in<12>cy (pll3_mult_neg_data_in<12>_cyo) XORCY:CI->O 2 0.868 0.588 pll3_mult_neg_data_in<13>_xor (mult_neg_data_in<13>) LUT3:I0->O 0 0.313 0.000 mult_out<13>1 (mult_out<13>) MUXCY:DI->O 1 0.595 0.000 pll3__n0026<13>cy (pll3__n0026<13>_cyo) MUXCY:CI->O 1 0.042 0.000 pll3__n0026<14>cy (pll3__n0026<14>_cyo) MUXCY:CI->O 1 0.042 0.000 pll3__n0026<15>cy (pll3__n0026<15>_cyo) MUXCY:CI->O 1 0.042 0.000 pll3__n0026<16>cy (pll3__n0026<16>_cyo) MUXCY:CI->O 1 0.042 0.000 pll3__n0026<17>cy (pll3__n0026<17>_cyo) MUXCY:CI->O 1 0.042 0.000 pll3__n0026<18>cy (pll3__n0026<18>_cyo) MUXCY:CI->O 1 0.042 0.000 pll3__n0026<19>cy (pll3__n0026<19>_cyo) MUXCY:CI->O 1 0.042 0.000 pll3__n0026<20>cy (pll3__n0026<20>_cyo) MUXCY:CI->O 1 0.042 0.000 pll3__n0026<21>cy (pll3__n0026<21>_cyo) XORCY:CI->O 1 0.868 0.533 pll3__n0026<22>_xor (_n0026<22>) LUT2_L:I0->LO 1 0.313 0.000 pll3__n0013<22>lut (N579) MUXCY:S->O 0 0.377 0.000 pll3__n0013<22>cy (pll3__n0013<22>_cyo) XORCY:CI->O 1 0.868 0.000 pll3__n0013<23>_xor (_n0013<23>) FDR:D 0.234 n2_23 ---------------------------------------- Total 8.606ns (6.875ns logic, 1.731ns route) (79.9% logic, 20.1% route) ========================================================================= Timing constraint: Default OFFSET OUT AFTER for Clock 'clk' Total number of paths / destination ports: 122 / 98 ------------------------------------------------------------------------- Offset: 4.557ns (Levels of Logic = 2) Source: state_FFd1 (FF) Destination: result_valid (PAD) Source Clock: clk rising Data Path: state_FFd1 to result_valid Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ FDC:C->Q 4 0.374 0.629 state_FFd1 (state_FFd1) LUT2:I0->O 1 0.313 0.390 state_Out11 (result_valid_OBUF) OBUF:I->O 2.851 result_valid_OBUF (result_valid) ---------------------------------------- Total 4.557ns (3.538ns logic, 1.019ns route) (77.6% logic, 22.4% route) ========================================================================= Timing constraint: Default path analysis Total number of paths / destination ports: 145 / 145 ------------------------------------------------------------------------- Delay: 2.034ns (Levels of Logic = 1) Source: clk (PAD) Destination: analyser/i_ila_6CH:clk (PAD) Data Path: clk to analyser/i_ila_6CH:clk Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ BUFGP:I->O 718 0.462 1.572 clk_BUFGP (clk_BUFGP) ila_6CH:clk 0.000 analyser/i_ila_6CH ---------------------------------------- Total 2.034ns (0.462ns logic, 1.572ns route) (22.7% logic, 77.3% route) ========================================================================= CPU : 55.52 / 55.89 s | Elapsed : 56.00 / 56.00 s --> Total memory usage is 181584 kilobytes Number of errors : 0 ( 0 filtered) Number of warnings : 40 ( 0 filtered) Number of infos : 0 ( 0 filtered)