Release 8.1i - xst I.24
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to ./xst/projnav.tmp
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=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "C:/DESIGNS/FPGA/Custom_Libera/chipscope_analyser.vhd" in Library work.
Architecture behavioral of Entity chipscope_analyser is up to date.
Compiling vhdl file "C:/DESIGNS/FPGA/Custom_Libera/pll3.vhd" in Library work.
Entity <pll3> compiled.
Entity <pll3> (Architecture <behavioral>) compiled.
Compiling verilog file "phasetable.v" in library work
Module <phasetable> compiled
No errors in compilation
Analysis of file <"pll3.prj"> succeeded.
 
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Total memory usage is 80072 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    0 (   0 filtered)
Number of infos    :    0 (   0 filtered)