(edif test (edifVersion 2 0 0) (edifLevel 0) (keywordMap (keywordLevel 0))
(status (written (timeStamp 2006 8 16 10 47 54)
   (author "Xilinx, Inc.")
   (program "Xilinx CORE Generator" (version "Xilinx CORE Generator 8.1i"))))
   (comment "                                                                                
      This file is owned and controlled by Xilinx and must be used              
      solely for design, simulation, implementation and creation of             
      design files limited to Xilinx devices or technologies. Use               
      with non-Xilinx devices or technologies is expressly prohibited           
      and immediately terminates your license.                                  
                                                                                
      XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION 'AS IS'             
      SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR                   
      XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION           
      AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION               
      OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS                 
      IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,                   
      AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE          
      FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY                  
      WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE                   
      IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR            
      REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF           
      INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS           
      FOR A PARTICULAR PURPOSE.                                                 
                                                                                
      Xilinx products are not intended for use in life support                  
      appliances, devices, or systems. Use in such applications are             
      expressly prohibited.                                                     
                                                                                
      (c) Copyright 1995-2005 Xilinx, Inc.                                      
      All rights reserved.                                                      
                                                                                
   ")
   (comment "Core parameters: ")
       (comment "c_has_clk = 0 ")
       (comment "c_has_qdpo_clk = 0 ")
       (comment "c_has_qdpo_ce = 0 ")
       (comment "c_has_d = 0 ")
       (comment "c_elaboration_dir = C:\ADMXRC_SDK4.7.0\fpga\vhdl\CERN\_cg\ ")
       (comment "c_has_spo = 1 ")
       (comment "c_read_mif = 1 ")
       (comment "c_has_qspo = 0 ")
       (comment "c_width = 4 ")
       (comment "c_reg_a_d_inputs = 0 ")
       (comment "c_has_we = 0 ")
       (comment "c_has_qdpo_rst = 0 ")
       (comment "c_reg_dpra_input = 0 ")
       (comment "c_qualify_we = 0 ")
       (comment "InstanceName = ph_table_rom ")
       (comment "c_sync_enable = 1 ")
       (comment "c_depth = 512 ")
       (comment "c_has_qspo_srst = 0 ")
       (comment "c_has_qdpo_srst = 0 ")
       (comment "c_has_dpra = 0 ")
       (comment "c_qce_joined = 0 ")
       (comment "c_mem_type = 0 ")
       (comment "c_has_i_ce = 0 ")
       (comment "c_has_dpo = 0 ")
       (comment "c_mem_init_file = ph_table_rom.mif ")
       (comment "c_default_data = 0 ")
       (comment "c_has_spra = 0 ")
       (comment "c_has_qspo_ce = 0 ")
       (comment "c_addr_width = 9 ")
       (comment "c_has_qdpo = 0 ")
       (comment "c_has_qspo_rst = 0 ")
   (external xilinxun (edifLevel 0)
      (technology (numberDefinition))
       (cell VCC (cellType GENERIC)
           (view view_1 (viewType NETLIST)
               (interface
                   (port P (direction OUTPUT))
               )
           )
       )
       (cell GND (cellType GENERIC)
           (view view_1 (viewType NETLIST)
               (interface
                   (port G (direction OUTPUT))
               )
           )
       )
   )
   (external ph_table_rom_dist_mem_gen_v1_1_xst_1_lib (edifLevel 0)
       (technology (numberDefinition))
       (cell ph_table_rom_dist_mem_gen_v1_1_xst_1 (cellType GENERIC)
           (view view_1 (viewType NETLIST)
               (interface
                   (port ( array ( rename a "a<8:0>") 9 ) (direction INPUT))
                   (port ( array ( rename d "d<3:0>") 4 ) (direction INPUT))
                   (port ( array ( rename dpra "dpra<8:0>") 9 ) (direction INPUT))
                   (port ( array ( rename spra "spra<8:0>") 9 ) (direction INPUT))
                   (port clk (direction INPUT))
                   (port we (direction INPUT))
                   (port i_ce (direction INPUT))
                   (port qspo_ce (direction INPUT))
                   (port qdpo_ce (direction INPUT))
                   (port qdpo_clk (direction INPUT))
                   (port qspo_rst (direction INPUT))
                   (port qdpo_rst (direction INPUT))
                   (port qspo_srst (direction INPUT))
                   (port qdpo_srst (direction INPUT))
                   (port ( array ( rename spo "spo<3:0>") 4 ) (direction OUTPUT))
                   (port ( array ( rename dpo "dpo<3:0>") 4 ) (direction OUTPUT))
                   (port ( array ( rename qspo "qspo<3:0>") 4 ) (direction OUTPUT))
                   (port ( array ( rename qdpo "qdpo<3:0>") 4 ) (direction OUTPUT))
               )
           )
       )
   )
(library test_lib (edifLevel 0) (technology (numberDefinition (scale 1 (E 1 -12) (unit Time))))
(cell ph_table_rom
 (cellType GENERIC) (view view_1 (viewType NETLIST)
  (interface
   (port ( array ( rename a "a<8:0>") 9 ) (direction INPUT))
   (port ( array ( rename spo "spo<3:0>") 4 ) (direction OUTPUT))
   )
  (contents
   (instance VCC (viewRef view_1 (cellRef VCC  (libraryRef xilinxun))))
   (instance GND (viewRef view_1 (cellRef GND  (libraryRef xilinxun))))
   (instance BU2
      (viewRef view_1 (cellRef ph_table_rom_dist_mem_gen_v1_1_xst_1 (libraryRef ph_table_rom_dist_mem_gen_v1_1_xst_1_lib)))
   )
   (net N0
    (joined
      (portRef G (instanceRef GND))
      (portRef (member d 0) (instanceRef BU2))
      (portRef (member d 1) (instanceRef BU2))
      (portRef (member d 2) (instanceRef BU2))
      (portRef (member d 3) (instanceRef BU2))
      (portRef (member dpra 0) (instanceRef BU2))
      (portRef (member dpra 1) (instanceRef BU2))
      (portRef (member dpra 2) (instanceRef BU2))
      (portRef (member dpra 3) (instanceRef BU2))
      (portRef (member dpra 4) (instanceRef BU2))
      (portRef (member dpra 5) (instanceRef BU2))
      (portRef (member dpra 6) (instanceRef BU2))
      (portRef (member dpra 7) (instanceRef BU2))
      (portRef (member dpra 8) (instanceRef BU2))
      (portRef (member spra 0) (instanceRef BU2))
      (portRef (member spra 1) (instanceRef BU2))
      (portRef (member spra 2) (instanceRef BU2))
      (portRef (member spra 3) (instanceRef BU2))
      (portRef (member spra 4) (instanceRef BU2))
      (portRef (member spra 5) (instanceRef BU2))
      (portRef (member spra 6) (instanceRef BU2))
      (portRef (member spra 7) (instanceRef BU2))
      (portRef (member spra 8) (instanceRef BU2))
      (portRef clk (instanceRef BU2))
      (portRef qdpo_clk (instanceRef BU2))
      (portRef qspo_rst (instanceRef BU2))
      (portRef qdpo_rst (instanceRef BU2))
      (portRef qspo_srst (instanceRef BU2))
      (portRef qdpo_srst (instanceRef BU2))
    )
   )
   (net N1
    (joined
      (portRef P (instanceRef VCC))
      (portRef we (instanceRef BU2))
      (portRef i_ce (instanceRef BU2))
      (portRef qspo_ce (instanceRef BU2))
      (portRef qdpo_ce (instanceRef BU2))
    )
   )
   (net (rename N2115 "a<8>")
    (joined
      (portRef (member a 0))
      (portRef (member a 0) (instanceRef BU2))
    )
   )
   (net (rename N2116 "a<7>")
    (joined
      (portRef (member a 1))
      (portRef (member a 1) (instanceRef BU2))
    )
   )
   (net (rename N2117 "a<6>")
    (joined
      (portRef (member a 2))
      (portRef (member a 2) (instanceRef BU2))
    )
   )
   (net (rename N2118 "a<5>")
    (joined
      (portRef (member a 3))
      (portRef (member a 3) (instanceRef BU2))
    )
   )
   (net (rename N2119 "a<4>")
    (joined
      (portRef (member a 4))
      (portRef (member a 4) (instanceRef BU2))
    )
   )
   (net (rename N2120 "a<3>")
    (joined
      (portRef (member a 5))
      (portRef (member a 5) (instanceRef BU2))
    )
   )
   (net (rename N2121 "a<2>")
    (joined
      (portRef (member a 6))
      (portRef (member a 6) (instanceRef BU2))
    )
   )
   (net (rename N2122 "a<1>")
    (joined
      (portRef (member a 7))
      (portRef (member a 7) (instanceRef BU2))
    )
   )
   (net (rename N2123 "a<0>")
    (joined
      (portRef (member a 8))
      (portRef (member a 8) (instanceRef BU2))
    )
   )
   (net (rename N2156 "spo<3>")
    (joined
      (portRef (member spo 0))
      (portRef (member spo 0) (instanceRef BU2))
    )
   )
   (net (rename N2157 "spo<2>")
    (joined
      (portRef (member spo 1))
      (portRef (member spo 1) (instanceRef BU2))
    )
   )
   (net (rename N2158 "spo<1>")
    (joined
      (portRef (member spo 2))
      (portRef (member spo 2) (instanceRef BU2))
    )
   )
   (net (rename N2159 "spo<0>")
    (joined
      (portRef (member spo 3))
      (portRef (member spo 3) (instanceRef BU2))
    )
   )
))))
(design ph_table_rom (cellRef ph_table_rom (libraryRef test_lib))
  (property X_CORE_INFO (string "dist_mem_gen_v1_1, Coregen 8.1i"))
  (property PART (string "xc2vp30-ff896-5") (owner "Xilinx")))
)