Release 8.1i - xst I.24
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to ./xst/projnav.tmp
CPU : 0.00 / 0.36 s | Elapsed : 0.00 / 0.00 s
 
--> Parameter xsthdpdir set to ./xst
CPU : 0.00 / 0.36 s | Elapsed : 0.00 / 0.00 s
 
--> Reading design: libera_pll.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
     4.1) HDL Synthesis Report
  5) Advanced HDL Synthesis
     5.1) Advanced HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "libera_pll.prj"
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "libera_pll"
Output Format                      : NGC
Target Device                      : xc2vp30-6-ff1152

---- Source Options
Top Module Name                    : libera_pll
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
ROM Style                          : Auto
Mux Extraction                     : YES
Resource Sharing                   : YES
Multiplier Style                   : auto
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 500
Add Generic Clock Buffer(BUFG)     : 16
Register Duplication               : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto
Equivalent register Removal        : YES

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
RTL Output                         : Yes
Global Optimization                : AllClockNets
Write Timing Constraints           : NO
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : libera_pll.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
safe_implementation                : No
Optimize Instantiated Primitives   : NO
tristate2logic                     : Yes
use_clock_enable                   : Yes
use_sync_set                       : Yes
use_sync_reset                     : Yes

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "C:/DESIGNS/FPGA/Custom_Libera/PLL/BLR3.vhd" in Library work.
Entity <BLR3> compiled.
Entity <BLR3> (Architecture <Behavioral>) compiled.
Compiling vhdl file "C:/DESIGNS/FPGA/Custom_Libera/PLL/DDS.vhd" in Library work.
Entity <DDS> compiled.
Entity <DDS> (Architecture <Behavioral>) compiled.
Compiling vhdl file "C:/DESIGNS/FPGA/Custom_Libera/PLL/filter_1.vhd" in Library work.
Entity <filter_1> compiled.
Entity <filter_1> (Architecture <Behavioral>) compiled.
Compiling vhdl file "C:/DESIGNS/FPGA/Custom_Libera/PLL/integrator.vhd" in Library work.
Entity <integrator> compiled.
Entity <integrator> (Architecture <Behavioral>) compiled.
Compiling vhdl file "C:/DESIGNS/FPGA/Custom_Libera/PLL/mux.vhd" in Library work.
Entity <mux> compiled.
Entity <mux> (Architecture <Behavioral>) compiled.
Compiling vhdl file "C:/DESIGNS/FPGA/Custom_Libera/PLL/mul32_1.vhd" in Library work.
Entity <mul32_1> compiled.
Entity <mul32_1> (Architecture <Behavioral>) compiled.
Compiling vhdl file "C:/DESIGNS/FPGA/Custom_Libera/PLL/pll2.vhd" in Library work.
Entity <pll2> compiled.
Entity <pll2> (Architecture <BEHAVIORAL>) compiled.
Compiling vhdl file "C:/DESIGNS/FPGA/Custom_Libera/PLL/libera_pll.vhd" in Library work.
Entity <libera_pll> compiled.
Entity <libera_pll> (Architecture <BEHAVIORAL>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <libera_pll> (Architecture <BEHAVIORAL>).
WARNING:Xst:753 - "C:/DESIGNS/FPGA/Custom_Libera/PLL/libera_pll.vhd" line 213: Unconnected output port 'b1_out' of component 'pll2'.
WARNING:Xst:753 - "C:/DESIGNS/FPGA/Custom_Libera/PLL/libera_pll.vhd" line 213: Unconnected output port 'blr_regulator_out' of component 'pll2'.
WARNING:Xst:753 - "C:/DESIGNS/FPGA/Custom_Libera/PLL/libera_pll.vhd" line 213: Unconnected output port 'DC_OUT' of component 'pll2'.
WARNING:Xst:753 - "C:/DESIGNS/FPGA/Custom_Libera/PLL/libera_pll.vhd" line 213: Unconnected output port 'result_1' of component 'pll2'.
WARNING:Xst:753 - "C:/DESIGNS/FPGA/Custom_Libera/PLL/libera_pll.vhd" line 213: Unconnected output port 'result_2' of component 'pll2'.
WARNING:Xst:753 - "C:/DESIGNS/FPGA/Custom_Libera/PLL/libera_pll.vhd" line 213: Unconnected output port 'result_valid_1' of component 'pll2'.
WARNING:Xst:753 - "C:/DESIGNS/FPGA/Custom_Libera/PLL/libera_pll.vhd" line 213: Unconnected output port 'result_valid_2' of component 'pll2'.
WARNING:Xst:766 - "C:/DESIGNS/FPGA/Custom_Libera/PLL/libera_pll.vhd" line 331: Generating a Black Box for component <icon>.
WARNING:Xst:766 - "C:/DESIGNS/FPGA/Custom_Libera/PLL/libera_pll.vhd" line 345: Generating a Black Box for component <vio_control>.
WARNING:Xst:766 - "C:/DESIGNS/FPGA/Custom_Libera/PLL/libera_pll.vhd" line 361: Generating a Black Box for component <vio>.
WARNING:Xst:766 - "C:/DESIGNS/FPGA/Custom_Libera/PLL/libera_pll.vhd" line 375: Generating a Black Box for component <ila_4CH>.
WARNING:Xst:766 - "C:/DESIGNS/FPGA/Custom_Libera/PLL/libera_pll.vhd" line 391: Generating a Black Box for component <ila_2CH>.
WARNING:Xst:819 - "C:/DESIGNS/FPGA/Custom_Libera/PLL/libera_pll.vhd" line 409: The following signals are missing in the process sensitivity list:
   timer.
Entity <libera_pll> analyzed. Unit <libera_pll> generated.

Analyzing Entity <pll2> (Architecture <behavioral>).
WARNING:Xst:766 - "C:/DESIGNS/FPGA/Custom_Libera/PLL/pll2.vhd" line 253: Generating a Black Box for component <rom512x4>.
WARNING:Xst:753 - "C:/DESIGNS/FPGA/Custom_Libera/PLL/pll2.vhd" line 270: Unconnected output port 'b1_out' of component 'BLR3'.
WARNING:Xst:753 - "C:/DESIGNS/FPGA/Custom_Libera/PLL/pll2.vhd" line 270: Unconnected output port 'e_out' of component 'BLR3'.
WARNING:Xst:753 - "C:/DESIGNS/FPGA/Custom_Libera/PLL/pll2.vhd" line 279: Unconnected output port 'b1_out' of component 'BLR3'.
WARNING:Xst:753 - "C:/DESIGNS/FPGA/Custom_Libera/PLL/pll2.vhd" line 279: Unconnected output port 'e_out' of component 'BLR3'.
Entity <pll2> analyzed. Unit <pll2> generated.

Analyzing Entity <BLR3> (Architecture <behavioral>).
Entity <BLR3> analyzed. Unit <BLR3> generated.

Analyzing Entity <dds> (Architecture <behavioral>).
WARNING:Xst:819 - "C:/DESIGNS/FPGA/Custom_Libera/PLL/DDS.vhd" line 49: The following signals are missing in the process sensitivity list:
   f1_init.
Entity <dds> analyzed. Unit <dds> generated.

Analyzing Entity <filter_1> (Architecture <behavioral>).
Entity <filter_1> analyzed. Unit <filter_1> generated.

Analyzing Entity <integrator> (Architecture <behavioral>).
Entity <integrator> analyzed. Unit <integrator> generated.

Analyzing Entity <mux> (Architecture <behavioral>).
Entity <mux> analyzed. Unit <mux> generated.

Analyzing Entity <mul32_1> (Architecture <behavioral>).
Entity <mul32_1> analyzed. Unit <mul32_1> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <mul32_1>.
    Related source file is "C:/DESIGNS/FPGA/Custom_Libera/PLL/mul32_1.vhd".
    Found 24-bit adder for signal <neg>.
    Summary:
	inferred   1 Adder/Subtractor(s).
Unit <mul32_1> synthesized.


Synthesizing Unit <mux>.
    Related source file is "C:/DESIGNS/FPGA/Custom_Libera/PLL/mux.vhd".
Unit <mux> synthesized.


Synthesizing Unit <integrator>.
    Related source file is "C:/DESIGNS/FPGA/Custom_Libera/PLL/integrator.vhd".
    Found finite state machine <FSM_0> for signal <state>.
    -----------------------------------------------------------------------
    | States             | 4                                              |
    | Transitions        | 6                                              |
    | Inputs             | 1                                              |
    | Outputs            | 2                                              |
    | Clock              | clk (rising_edge)                              |
    | Reset              | init (positive)                                |
    | Reset type         | asynchronous                                   |
    | Reset State        | idle                                           |
    | Power Up State     | idle                                           |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 32-bit register for signal <Data_out>.
    Found 32-bit up accumulator for signal <accumulate>.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred   1 Accumulator(s).
	inferred  32 D-type flip-flop(s).
Unit <integrator> synthesized.


Synthesizing Unit <filter_1>.
    Related source file is "C:/DESIGNS/FPGA/Custom_Libera/PLL/filter_1.vhd".
WARNING:Xst:647 - Input <data_in<31:24>> is never used.
WARNING:Xst:646 - Signal <n6<6:0>> is assigned but never used.
WARNING:Xst:1780 - Signal <s3> is never used or assigned.
WARNING:Xst:1780 - Signal <s5> is never used or assigned.
    Found 24-bit subtractor for signal <$n0007> created at line 59.
    Found 24-bit subtractor for signal <$n0008> created at line 60.
    Found 24-bit subtractor for signal <$n0009> created at line 63.
    Found 24-bit subtractor for signal <$n0010> created at line 64.
    Found 24-bit subtractor for signal <$n0011> created at line 67.
    Found 24-bit subtractor for signal <$n0012> created at line 61.
    Found 24-bit subtractor for signal <$n0013> created at line 65.
    Found 24-bit adder for signal <$n0014> created at line 59.
    Found 24-bit adder for signal <$n0015> created at line 60.
    Found 24-bit adder for signal <$n0016> created at line 64.
    Found 24-bit register for signal <n2>.
    Found 24-bit register for signal <n3>.
    Found 24-bit register for signal <n4>.
    Found 24-bit register for signal <n5>.
    Found 24-bit register for signal <n6>.
    Found 24-bit register for signal <s4>.
    Found 24-bit register for signal <s6>.
    Summary:
	inferred 168 D-type flip-flop(s).
	inferred  10 Adder/Subtractor(s).
Unit <filter_1> synthesized.


Synthesizing Unit <dds>.
    Related source file is "C:/DESIGNS/FPGA/Custom_Libera/PLL/DDS.vhd".
    Found 9-bit adder for signal <mem_addr>.
    Found 32-bit down accumulator for signal <f1>.
    Found 32-bit up accumulator for signal <p1>.
    Summary:
	inferred   2 Accumulator(s).
	inferred   1 Adder/Subtractor(s).
Unit <dds> synthesized.


Synthesizing Unit <BLR3>.
    Related source file is "C:/DESIGNS/FPGA/Custom_Libera/PLL/BLR3.vhd".
    Found 24-bit subtractor for signal <$n0000> created at line 62.
    Found 24-bit adder for signal <$n0001> created at line 64.
    Found 24-bit up accumulator for signal <b1>.
    Found 24-bit up accumulator for signal <e>.
    Found 24-bit register for signal <x>.
    Found 24-bit register for signal <y>.
    Summary:
	inferred   2 Accumulator(s).
	inferred  48 D-type flip-flop(s).
	inferred   2 Adder/Subtractor(s).
Unit <BLR3> synthesized.


Synthesizing Unit <pll2>.
    Related source file is "C:/DESIGNS/FPGA/Custom_Libera/PLL/pll2.vhd".
    Found 32-bit 16-to-1 multiplexer for signal <F_ERR>.
    Summary:
	inferred  32 Multiplexer(s).
Unit <pll2> synthesized.


Synthesizing Unit <libera_pll>.
    Related source file is "C:/DESIGNS/FPGA/Custom_Libera/PLL/libera_pll.vhd".
WARNING:Xst:1306 - Output <result_Valid_0> is never assigned.
WARNING:Xst:647 - Input <adc0_rst_i> is never used.
WARNING:Xst:647 - Input <ifreq_i> is never used.
WARNING:Xst:1780 - Signal <clk_inv> is never used or assigned.
WARNING:Xst:1780 - Signal <timer_load> is never used or assigned.
WARNING:Xst:1780 - Signal <pll_init> is never used or assigned.
WARNING:Xst:1780 - Signal <pll_init_f1> is never used or assigned.
WARNING:Xst:646 - Signal <async_out_control<31:22>> is assigned but never used.
WARNING:Xst:646 - Signal <async_out_control<19:18>> is assigned but never used.
WARNING:Xst:646 - Signal <async_out_control<15:14>> is assigned but never used.
WARNING:Xst:646 - Signal <async_out_control<11:10>> is assigned but never used.
WARNING:Xst:646 - Signal <async_out_control<7:6>> is assigned but never used.
WARNING:Xst:646 - Signal <async_out_control<3:2>> is assigned but never used.
WARNING:Xst:646 - Signal <clk1> is assigned but never used.
WARNING:Xst:1780 - Signal <Phase_init> is never used or assigned.
WARNING:Xst:1780 - Signal <XLXN_260> is never used or assigned.
WARNING:Xst:1780 - Signal <XLXN_261> is never used or assigned.
WARNING:Xst:1780 - Signal <pll_mux_sel> is never used or assigned.
WARNING:Xst:1780 - Signal <pt_load<31:24>> is never used or assigned.
WARNING:Xst:646 - Signal <pt_load<23>> is assigned but never used.
WARNING:Xst:1780 - Signal <pt_load<22:20>> is never used or assigned.
WARNING:Xst:646 - Signal <pt_load<19:16>> is assigned but never used.
WARNING:Xst:1780 - Signal <pt_load<15:9>> is never used or assigned.
WARNING:Xst:646 - Signal <pt_load<8:0>> is assigned but never used.
    Found 14-bit 4-to-1 multiplexer for signal <ADC_SEL>.
    Found 32-bit 4-to-1 multiplexer for signal <ILA2_CH0>.
    Found 32-bit 4-to-1 multiplexer for signal <ILA2_CH1>.
    Found 32-bit 4-to-1 multiplexer for signal <ILA4_CH0>.
    Found 32-bit 4-to-1 multiplexer for signal <ILA4_CH1>.
    Found 8-bit 4-to-1 multiplexer for signal <ILA4_CH2>.
    Found 24-bit down counter for signal <timer>.
    Summary:
	inferred   1 Counter(s).
	inferred 150 Multiplexer(s).
Unit <libera_pll> synthesized.


=========================================================================
HDL Synthesis Report

Macro Statistics
# Adders/Subtractors                                   : 40
 24-bit adder                                          : 15
 24-bit subtractor                                     : 24
 9-bit adder                                           : 1
# Counters                                             : 1
 24-bit down counter                                   : 1
# Accumulators                                         : 11
 24-bit up accumulator                                 : 6
 32-bit down accumulator                               : 1
 32-bit up accumulator                                 : 4
# Registers                                            : 30
 24-bit register                                       : 27
 32-bit register                                       : 3
# Multiplexers                                         : 7
 14-bit 4-to-1 multiplexer                             : 1
 32-bit 16-to-1 multiplexer                            : 1
 32-bit 4-to-1 multiplexer                             : 4
 8-bit 4-to-1 multiplexer                              : 1

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Analyzing FSM <FSM_0> for best encoding.
Optimizing FSM <XLXI_18/integ/state> on signal <state[1:2]> with gray encoding.
-----------------------
 State     | Encoding
-----------------------
 idle      | 00
 integrate | 01
 ready     | 11
 reset_acc | 10
-----------------------
Reading module "icon.ngo" ( "icon.ngo" unchanged since last run )...
WARNING:Xst:1474 - Core <icon> was not loaded for <i_icon> as one or more ports did not line up with component declaration.  Declared output port <control0<3>> was not found in the core.  Please make sure that component declaration ports are consistent with the core ports including direction and bus-naming conventions.
WARNING:Xst:1291 - FF/Latch <n6_0> is unconnected in block <filter_1>.
WARNING:Xst:1291 - FF/Latch <n6_1> is unconnected in block <filter_1>.
WARNING:Xst:1291 - FF/Latch <n6_2> is unconnected in block <filter_1>.
WARNING:Xst:1291 - FF/Latch <n6_3> is unconnected in block <filter_1>.
WARNING:Xst:1291 - FF/Latch <n6_4> is unconnected in block <filter_1>.
WARNING:Xst:1291 - FF/Latch <n6_5> is unconnected in block <filter_1>.
WARNING:Xst:1291 - FF/Latch <n6_6> is unconnected in block <filter_1>.
WARNING:Xst:1291 - FF/Latch <n6_7> is unconnected in block <FIL3>.
WARNING:Xst:1291 - FF/Latch <n6_8> is unconnected in block <FIL3>.
WARNING:Xst:1291 - FF/Latch <n6_9> is unconnected in block <FIL3>.
WARNING:Xst:1291 - FF/Latch <n6_10> is unconnected in block <FIL3>.
WARNING:Xst:1291 - FF/Latch <n6_11> is unconnected in block <FIL3>.
WARNING:Xst:1291 - FF/Latch <n6_12> is unconnected in block <FIL3>.
WARNING:Xst:1291 - FF/Latch <n6_13> is unconnected in block <FIL3>.
WARNING:Xst:1291 - FF/Latch <n6_14> is unconnected in block <FIL3>.
WARNING:Xst:1291 - FF/Latch <n6_15> is unconnected in block <FIL3>.
WARNING:Xst:1291 - FF/Latch <n6_16> is unconnected in block <FIL3>.
WARNING:Xst:1291 - FF/Latch <n6_17> is unconnected in block <FIL3>.
WARNING:Xst:1291 - FF/Latch <n6_18> is unconnected in block <FIL3>.
WARNING:Xst:1291 - FF/Latch <n6_19> is unconnected in block <FIL3>.
WARNING:Xst:1291 - FF/Latch <n6_20> is unconnected in block <FIL3>.
WARNING:Xst:1291 - FF/Latch <n6_21> is unconnected in block <FIL3>.
WARNING:Xst:1291 - FF/Latch <n6_22> is unconnected in block <FIL3>.
WARNING:Xst:1291 - FF/Latch <n6_23> is unconnected in block <FIL3>.
WARNING:Xst:1291 - FF/Latch <Data_out_0> is unconnected in block <XLXI_5>.
WARNING:Xst:1291 - FF/Latch <Data_out_1> is unconnected in block <XLXI_5>.
WARNING:Xst:1291 - FF/Latch <Data_out_2> is unconnected in block <XLXI_5>.
WARNING:Xst:1291 - FF/Latch <Data_out_3> is unconnected in block <XLXI_5>.
WARNING:Xst:1291 - FF/Latch <Data_out_4> is unconnected in block <XLXI_5>.
WARNING:Xst:1291 - FF/Latch <Data_out_5> is unconnected in block <XLXI_5>.
WARNING:Xst:1291 - FF/Latch <Data_out_6> is unconnected in block <XLXI_5>.
WARNING:Xst:1291 - FF/Latch <Data_out_7> is unconnected in block <XLXI_5>.
WARNING:Xst:1291 - FF/Latch <Data_out_8> is unconnected in block <XLXI_5>.
WARNING:Xst:1291 - FF/Latch <Data_out_9> is unconnected in block <XLXI_5>.
WARNING:Xst:1291 - FF/Latch <Data_out_10> is unconnected in block <XLXI_5>.
WARNING:Xst:1291 - FF/Latch <Data_out_11> is unconnected in block <XLXI_5>.
WARNING:Xst:1291 - FF/Latch <Data_out_12> is unconnected in block <XLXI_5>.
WARNING:Xst:1291 - FF/Latch <Data_out_13> is unconnected in block <XLXI_5>.
WARNING:Xst:1291 - FF/Latch <Data_out_14> is unconnected in block <XLXI_5>.
WARNING:Xst:1291 - FF/Latch <Data_out_15> is unconnected in block <XLXI_5>.
WARNING:Xst:1291 - FF/Latch <Data_out_16> is unconnected in block <XLXI_5>.
WARNING:Xst:1291 - FF/Latch <Data_out_17> is unconnected in block <XLXI_5>.
WARNING:Xst:1291 - FF/Latch <Data_out_18> is unconnected in block <XLXI_5>.
WARNING:Xst:1291 - FF/Latch <Data_out_19> is unconnected in block <XLXI_5>.
WARNING:Xst:1291 - FF/Latch <Data_out_20> is unconnected in block <XLXI_5>.
WARNING:Xst:1291 - FF/Latch <Data_out_21> is unconnected in block <XLXI_5>.
WARNING:Xst:1291 - FF/Latch <Data_out_22> is unconnected in block <XLXI_5>.
WARNING:Xst:1291 - FF/Latch <Data_out_23> is unconnected in block <XLXI_5>.
WARNING:Xst:1291 - FF/Latch <Data_out_24> is unconnected in block <XLXI_5>.
WARNING:Xst:1291 - FF/Latch <Data_out_25> is unconnected in block <XLXI_5>.
WARNING:Xst:1291 - FF/Latch <Data_out_26> is unconnected in block <XLXI_5>.
WARNING:Xst:1291 - FF/Latch <Data_out_27> is unconnected in block <XLXI_5>.
WARNING:Xst:1291 - FF/Latch <Data_out_28> is unconnected in block <XLXI_5>.
WARNING:Xst:1291 - FF/Latch <Data_out_29> is unconnected in block <XLXI_5>.
WARNING:Xst:1291 - FF/Latch <Data_out_30> is unconnected in block <XLXI_5>.
WARNING:Xst:1291 - FF/Latch <Data_out_31> is unconnected in block <XLXI_5>.
WARNING:Xst:1291 - FF/Latch <Data_out_0> is unconnected in block <XLXI_6>.
WARNING:Xst:1291 - FF/Latch <Data_out_1> is unconnected in block <XLXI_6>.
WARNING:Xst:1291 - FF/Latch <Data_out_2> is unconnected in block <XLXI_6>.
WARNING:Xst:1291 - FF/Latch <Data_out_3> is unconnected in block <XLXI_6>.
WARNING:Xst:1291 - FF/Latch <Data_out_4> is unconnected in block <XLXI_6>.
WARNING:Xst:1291 - FF/Latch <Data_out_5> is unconnected in block <XLXI_6>.
WARNING:Xst:1291 - FF/Latch <Data_out_6> is unconnected in block <XLXI_6>.
WARNING:Xst:1291 - FF/Latch <Data_out_7> is unconnected in block <XLXI_6>.
WARNING:Xst:1291 - FF/Latch <Data_out_8> is unconnected in block <XLXI_6>.
WARNING:Xst:1291 - FF/Latch <Data_out_9> is unconnected in block <XLXI_6>.
WARNING:Xst:1291 - FF/Latch <Data_out_10> is unconnected in block <XLXI_6>.
WARNING:Xst:1291 - FF/Latch <Data_out_11> is unconnected in block <XLXI_6>.
WARNING:Xst:1291 - FF/Latch <Data_out_12> is unconnected in block <XLXI_6>.
WARNING:Xst:1291 - FF/Latch <Data_out_13> is unconnected in block <XLXI_6>.
WARNING:Xst:1291 - FF/Latch <Data_out_14> is unconnected in block <XLXI_6>.
WARNING:Xst:1291 - FF/Latch <Data_out_15> is unconnected in block <XLXI_6>.
WARNING:Xst:1291 - FF/Latch <Data_out_16> is unconnected in block <XLXI_6>.
WARNING:Xst:1291 - FF/Latch <Data_out_17> is unconnected in block <XLXI_6>.
WARNING:Xst:1291 - FF/Latch <Data_out_18> is unconnected in block <XLXI_6>.
WARNING:Xst:1291 - FF/Latch <Data_out_19> is unconnected in block <XLXI_6>.
WARNING:Xst:1291 - FF/Latch <Data_out_20> is unconnected in block <XLXI_6>.
WARNING:Xst:1291 - FF/Latch <Data_out_21> is unconnected in block <XLXI_6>.
WARNING:Xst:1291 - FF/Latch <Data_out_22> is unconnected in block <XLXI_6>.
WARNING:Xst:1291 - FF/Latch <Data_out_23> is unconnected in block <XLXI_6>.
WARNING:Xst:1291 - FF/Latch <Data_out_24> is unconnected in block <XLXI_6>.
WARNING:Xst:1291 - FF/Latch <Data_out_25> is unconnected in block <XLXI_6>.
WARNING:Xst:1291 - FF/Latch <Data_out_26> is unconnected in block <XLXI_6>.
WARNING:Xst:1291 - FF/Latch <Data_out_27> is unconnected in block <XLXI_6>.
WARNING:Xst:1291 - FF/Latch <Data_out_28> is unconnected in block <XLXI_6>.
WARNING:Xst:1291 - FF/Latch <Data_out_29> is unconnected in block <XLXI_6>.
WARNING:Xst:1291 - FF/Latch <Data_out_30> is unconnected in block <XLXI_6>.
WARNING:Xst:1291 - FF/Latch <Data_out_31> is unconnected in block <XLXI_6>.

=========================================================================
Advanced HDL Synthesis Report

Macro Statistics
# FSMs                                                 : 1
# Adders/Subtractors                                   : 40
 24-bit adder                                          : 15
 24-bit subtractor                                     : 24
 9-bit adder                                           : 1
# Counters                                             : 1
 24-bit down counter                                   : 1
# Accumulators                                         : 11
 24-bit up accumulator                                 : 6
 32-bit down accumulator                               : 1
 32-bit up accumulator                                 : 4
# Registers                                            : 244
 Flip-Flops                                            : 244
# Multiplexers                                         : 7
 14-bit 4-to-1 multiplexer                             : 1
 32-bit 16-to-1 multiplexer                            : 1
 32-bit 4-to-1 multiplexer                             : 4
 8-bit 4-to-1 multiplexer                              : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:524 - All outputs of the instance <XLXI_18/XLXI_5> of the block <integrator> are unconnected in block <libera_pll>.
   This instance will be removed from the design along with all underlying logic
WARNING:Xst:524 - All outputs of the instance <XLXI_18/XLXI_6> of the block <integrator> are unconnected in block <libera_pll>.
   This instance will be removed from the design along with all underlying logic
Loading device for application Rf_Device from file '2vp30.nph' in environment C:\Xilinx.

Optimizing unit <libera_pll> ...

Optimizing unit <integrator> ...

Optimizing unit <filter_1> ...

Optimizing unit <BLR3> ...

Mapping all equations...
WARNING:Xst:1291 - FF/Latch <XLXI_18/FIL3/n2_0> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/FIL3/n2_1> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/FIL3/n2_2> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/FIL3/n2_3> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/FIL3/n2_4> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/FIL3/n2_5> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/FIL3/n2_6> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/FIL3/n2_7> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/FIL3/n2_8> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/FIL3/n2_9> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/FIL3/n2_10> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/FIL3/n2_11> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/FIL3/n2_12> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/FIL3/n2_13> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/FIL3/n2_14> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/FIL3/n2_15> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/FIL3/n2_16> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/FIL3/n2_17> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/FIL3/n2_18> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/FIL3/n2_19> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/FIL3/n2_20> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/FIL3/n2_21> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/FIL3/n2_22> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/FIL3/n2_23> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/FIL3/n3_0> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/FIL3/n3_1> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/FIL3/n3_2> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/FIL3/n3_3> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/FIL3/n3_4> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/FIL3/n3_5> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/FIL3/n3_6> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/FIL3/n3_7> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/FIL3/n3_8> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/FIL3/n3_9> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/FIL3/n3_10> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/FIL3/n3_11> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/FIL3/n3_12> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/FIL3/n3_13> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/FIL3/n3_14> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/FIL3/n3_15> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/FIL3/n3_16> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/FIL3/n3_17> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/FIL3/n3_18> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/FIL3/n3_19> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/FIL3/n3_20> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/FIL3/n3_21> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/FIL3/n3_22> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/FIL3/n3_23> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/FIL3/s4_0> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/FIL3/s4_1> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/FIL3/s4_2> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/FIL3/s4_3> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/FIL3/s4_4> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/FIL3/s4_5> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/FIL3/s4_6> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/FIL3/s4_7> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/FIL3/s4_8> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/FIL3/s4_9> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/FIL3/s4_10> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/FIL3/s4_11> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/FIL3/s4_12> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/FIL3/s4_13> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/FIL3/s4_14> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/FIL3/s4_15> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/FIL3/s4_16> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/FIL3/s4_17> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/FIL3/s4_18> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/FIL3/s4_19> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/FIL3/s4_20> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/FIL3/s4_21> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/FIL3/s4_22> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/FIL3/s4_23> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/FIL3/n4_0> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/FIL3/n4_1> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/FIL3/n4_2> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/FIL3/n4_3> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/FIL3/n4_4> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/FIL3/n4_5> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/FIL3/n4_6> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/FIL3/n4_7> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/FIL3/n4_8> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/FIL3/n4_9> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/FIL3/n4_10> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/FIL3/n4_11> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/FIL3/n4_12> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/FIL3/n4_13> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/FIL3/n4_14> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/FIL3/n4_15> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/FIL3/n4_16> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/FIL3/n4_17> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/FIL3/n4_18> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/FIL3/n4_19> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/FIL3/n4_20> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/FIL3/n4_21> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/FIL3/n4_22> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/FIL3/n4_23> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/FIL3/n5_0> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/FIL3/n5_1> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/FIL3/n5_2> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/FIL3/n5_3> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/FIL3/n5_4> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/FIL3/n5_5> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/FIL3/n5_6> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/FIL3/n5_7> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/FIL3/n5_8> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/FIL3/n5_9> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/FIL3/n5_10> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/FIL3/n5_11> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/FIL3/n5_12> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/FIL3/n5_13> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/FIL3/n5_14> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/FIL3/n5_15> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/FIL3/n5_16> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/FIL3/n5_17> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/FIL3/n5_18> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/FIL3/n5_19> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/FIL3/n5_20> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/FIL3/n5_21> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/FIL3/n5_22> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/FIL3/n5_23> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/FIL3/s6_0> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/FIL3/s6_1> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/FIL3/s6_2> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/FIL3/s6_3> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/FIL3/s6_4> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/FIL3/s6_5> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/FIL3/s6_6> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/FIL3/s6_7> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/FIL3/s6_8> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/FIL3/s6_9> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/FIL3/s6_10> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/FIL3/s6_11> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/FIL3/s6_12> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/FIL3/s6_13> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/FIL3/s6_14> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/FIL3/s6_15> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/FIL3/s6_16> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/FIL3/s6_17> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/FIL3/s6_18> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/FIL3/s6_19> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/FIL3/s6_20> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/FIL3/s6_21> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/FIL3/s6_22> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/FIL3/s6_23> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/FIL3/n6_7> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/FIL3/n6_8> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/FIL3/n6_9> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/FIL3/n6_10> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/FIL3/n6_11> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/FIL3/n6_12> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/FIL3/n6_13> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/FIL3/n6_14> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/FIL3/n6_15> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/FIL3/n6_16> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/FIL3/n6_17> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/FIL3/n6_18> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/FIL3/n6_19> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/FIL3/n6_20> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/FIL3/n6_21> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/FIL3/n6_22> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/FIL3/n6_23> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_4/y_0> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_4/y_1> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_4/y_2> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_4/y_3> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_4/y_4> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_4/y_5> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_4/y_6> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_4/y_7> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_4/y_8> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_4/y_9> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_4/y_10> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_4/y_11> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_4/y_12> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_4/y_13> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_4/y_14> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_4/y_15> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_4/y_16> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_4/y_17> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_4/y_18> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_4/y_19> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_4/y_20> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_4/y_21> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_4/y_22> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_4/y_23> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_4/x_0> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_4/x_1> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_4/x_2> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_4/x_3> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_4/x_4> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_4/x_5> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_4/x_6> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_4/x_7> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_4/x_8> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_4/x_9> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_4/x_10> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_4/x_11> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_4/x_12> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_4/x_13> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_4/x_14> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_4/x_15> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_4/x_16> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_4/x_17> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_4/x_18> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_4/x_19> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_4/x_20> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_4/x_21> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_4/x_22> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_4/x_23> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_4/e_0> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_4/e_1> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_4/e_2> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_4/e_3> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_4/e_4> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_4/e_5> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_4/e_6> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_4/e_7> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_4/e_8> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_4/e_9> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_4/e_10> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_4/e_11> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_4/e_12> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_4/e_13> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_4/e_14> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_4/e_15> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_4/e_16> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_4/e_17> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_4/e_18> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_4/e_19> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_4/e_20> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_4/e_21> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_4/e_22> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_4/e_23> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_4/b1_0> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_4/b1_1> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_4/b1_2> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_4/b1_3> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_4/b1_4> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_4/b1_5> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_4/b1_6> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_4/b1_7> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_4/b1_8> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_4/b1_9> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_4/b1_10> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_4/b1_11> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_4/b1_12> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_4/b1_13> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_4/b1_14> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_4/b1_15> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_4/b1_16> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_4/b1_17> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_4/b1_18> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_4/b1_19> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_4/b1_20> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_4/b1_21> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_4/b1_22> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_4/b1_23> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_3/y_0> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_3/y_1> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_3/y_2> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_3/y_3> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_3/y_4> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_3/y_5> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_3/y_6> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_3/y_7> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_3/y_8> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_3/y_9> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_3/y_10> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_3/y_11> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_3/y_12> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_3/y_13> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_3/y_14> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_3/y_15> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_3/y_16> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_3/y_17> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_3/y_18> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_3/y_19> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_3/y_20> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_3/y_21> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_3/y_22> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_3/y_23> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_3/x_0> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_3/x_1> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_3/x_2> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_3/x_3> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_3/x_4> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_3/x_5> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_3/x_6> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_3/x_7> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_3/x_8> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_3/x_9> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_3/x_10> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_3/x_11> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_3/x_12> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_3/x_13> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_3/x_14> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_3/x_15> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_3/x_16> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_3/x_17> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_3/x_18> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_3/x_19> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_3/x_20> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_3/x_21> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_3/x_22> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_3/x_23> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_3/e_0> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_3/e_1> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_3/e_2> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_3/e_3> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_3/e_4> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_3/e_5> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_3/e_6> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_3/e_7> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_3/e_8> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_3/e_9> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_3/e_10> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_3/e_11> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_3/e_12> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_3/e_13> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_3/e_14> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_3/e_15> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_3/e_16> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_3/e_17> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_3/e_18> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_3/e_19> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_3/e_20> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_3/e_21> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_3/e_22> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_3/e_23> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_3/b1_0> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_3/b1_1> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_3/b1_2> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_3/b1_3> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_3/b1_4> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_3/b1_5> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_3/b1_6> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_3/b1_7> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_3/b1_8> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_3/b1_9> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_3/b1_10> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_3/b1_11> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_3/b1_12> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_3/b1_13> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_3/b1_14> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_3/b1_15> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_3/b1_16> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_3/b1_17> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_3/b1_18> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_3/b1_19> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_3/b1_20> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_3/b1_21> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_3/b1_22> is unconnected in block <libera_pll>.
WARNING:Xst:1291 - FF/Latch <XLXI_18/XLXI_3/b1_23> is unconnected in block <libera_pll>.
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block libera_pll, actual ratio is 5.
FlipFlop XLXI_18/filter1/n6_23 has been replicated 3 time(s)

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : libera_pll.ngr
Top Level Output File Name         : libera_pll
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 236

Cell Usage :
# BELS                             : 2883
#      GND                         : 1
#      INV                         : 54
#      LUT1                        : 13
#      LUT1_L                      : 1
#      LUT2                        : 367
#      LUT2_D                      : 5
#      LUT2_L                      : 252
#      LUT3                        : 337
#      LUT3_D                      : 11
#      LUT3_L                      : 16
#      LUT4                        : 186
#      LUT4_D                      : 11
#      LUT4_L                      : 112
#      MUXCY                       : 686
#      MUXF5                       : 147
#      VCC                         : 1
#      XORCY                       : 683
# FlipFlops/Latches                : 575
#      FDC                         : 106
#      FDC_1                       : 23
#      FDCE                        : 24
#      FDCPE                       : 32
#      FDE                         : 32
#      FDP_1                       : 1
#      FDR                         : 325
#      FDRE                        : 32
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 201
#      IBUF                        : 105
#      OBUF                        : 96
# Others                           : 6
#      icon                        : 1
#      ila_2CH                     : 1
#      ila_4CH                     : 1
#      rom512x4                    : 1
#      vio                         : 1
#      vio_control                 : 1
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2vp30ff1152-6 

 Number of Slices:                     705  out of  13696     5%  
 Number of Slice Flip Flops:           575  out of  27392     2%  
 Number of 4 input LUTs:              1311  out of  27392     4%  
 Number of bonded IOBs:                202  out of    644    31%  
 Number of GCLKs:                        1  out of     16     6%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
adc_clk0_i                         | BUFGP                  | 575   |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 7.331ns (Maximum Frequency: 136.416MHz)
   Minimum input arrival time before clock: 9.873ns
   Maximum output required time after clock: 4.748ns
   Maximum combinational path delay: 6.481ns

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'adc_clk0_i'
  Clock period: 7.331ns (frequency: 136.416MHz)
  Total number of paths / destination ports: 88005 / 639
-------------------------------------------------------------------------
Delay:               7.331ns (Levels of Logic = 29)
  Source:            XLXI_18/filter1/n6_16 (FF)
  Destination:       XLXI_18/DDS1/f1_31 (FF)
  Source Clock:      adc_clk0_i rising
  Destination Clock: adc_clk0_i rising

  Data Path: XLXI_18/filter1/n6_16 to XLXI_18/DDS1/f1_31
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q             14   0.374   0.765  XLXI_18/filter1/n6_16 (XLXI_18/filter1/n6_16)
     LUT3_L:I1->LO         1   0.313   0.000  config_i<5>_mmx_out1411_F (N4008)
     MUXF5:I0->O           3   0.340   0.495  config_i<5>_mmx_out1411 (mux_1_config_i<5>_mmx_out14)
     LUT3:I2->O            1   0.313   0.418  F_ERR_out<9>25 (F_ERR_out<9>_map875)
     LUT4:I2->O            3   0.313   0.583  F_ERR_out<9>81 (F_ERR_out<9>)
     LUT2_L:I1->LO         1   0.313   0.000  XLXI_18/DDS1/f1_LPM_ACCUM_3__n0000<9>lut (XLXI_18/DDS1/f1_N12)
     MUXCY:S->O            1   0.377   0.000  XLXI_18/DDS1/f1_LPM_ACCUM_3__n0000<9>cy (XLXI_18/DDS1/f1_LPM_ACCUM_3__n0000<9>_cyo)
     MUXCY:CI->O           1   0.042   0.000  XLXI_18/DDS1/f1_LPM_ACCUM_3__n0000<10>cy (XLXI_18/DDS1/f1_LPM_ACCUM_3__n0000<10>_cyo)
     MUXCY:CI->O           1   0.042   0.000  XLXI_18/DDS1/f1_LPM_ACCUM_3__n0000<11>cy (XLXI_18/DDS1/f1_LPM_ACCUM_3__n0000<11>_cyo)
     MUXCY:CI->O           1   0.042   0.000  XLXI_18/DDS1/f1_LPM_ACCUM_3__n0000<12>cy (XLXI_18/DDS1/f1_LPM_ACCUM_3__n0000<12>_cyo)
     MUXCY:CI->O           1   0.042   0.000  XLXI_18/DDS1/f1_LPM_ACCUM_3__n0000<13>cy (XLXI_18/DDS1/f1_LPM_ACCUM_3__n0000<13>_cyo)
     MUXCY:CI->O           1   0.042   0.000  XLXI_18/DDS1/f1_LPM_ACCUM_3__n0000<14>cy (XLXI_18/DDS1/f1_LPM_ACCUM_3__n0000<14>_cyo)
     MUXCY:CI->O           1   0.042   0.000  XLXI_18/DDS1/f1_LPM_ACCUM_3__n0000<15>cy (XLXI_18/DDS1/f1_LPM_ACCUM_3__n0000<15>_cyo)
     MUXCY:CI->O           1   0.042   0.000  XLXI_18/DDS1/f1_LPM_ACCUM_3__n0000<16>cy (XLXI_18/DDS1/f1_LPM_ACCUM_3__n0000<16>_cyo)
     MUXCY:CI->O           1   0.042   0.000  XLXI_18/DDS1/f1_LPM_ACCUM_3__n0000<17>cy (XLXI_18/DDS1/f1_LPM_ACCUM_3__n0000<17>_cyo)
     MUXCY:CI->O           1   0.042   0.000  XLXI_18/DDS1/f1_LPM_ACCUM_3__n0000<18>cy (XLXI_18/DDS1/f1_LPM_ACCUM_3__n0000<18>_cyo)
     MUXCY:CI->O           1   0.042   0.000  XLXI_18/DDS1/f1_LPM_ACCUM_3__n0000<19>cy (XLXI_18/DDS1/f1_LPM_ACCUM_3__n0000<19>_cyo)
     MUXCY:CI->O           1   0.042   0.000  XLXI_18/DDS1/f1_LPM_ACCUM_3__n0000<20>cy (XLXI_18/DDS1/f1_LPM_ACCUM_3__n0000<20>_cyo)
     MUXCY:CI->O           1   0.042   0.000  XLXI_18/DDS1/f1_LPM_ACCUM_3__n0000<21>cy (XLXI_18/DDS1/f1_LPM_ACCUM_3__n0000<21>_cyo)
     MUXCY:CI->O           1   0.042   0.000  XLXI_18/DDS1/f1_LPM_ACCUM_3__n0000<22>cy (XLXI_18/DDS1/f1_LPM_ACCUM_3__n0000<22>_cyo)
     MUXCY:CI->O           1   0.042   0.000  XLXI_18/DDS1/f1_LPM_ACCUM_3__n0000<23>cy (XLXI_18/DDS1/f1_LPM_ACCUM_3__n0000<23>_cyo)
     MUXCY:CI->O           1   0.042   0.000  XLXI_18/DDS1/f1_LPM_ACCUM_3__n0000<24>cy (XLXI_18/DDS1/f1_LPM_ACCUM_3__n0000<24>_cyo)
     MUXCY:CI->O           1   0.042   0.000  XLXI_18/DDS1/f1_LPM_ACCUM_3__n0000<25>cy (XLXI_18/DDS1/f1_LPM_ACCUM_3__n0000<25>_cyo)
     MUXCY:CI->O           1   0.042   0.000  XLXI_18/DDS1/f1_LPM_ACCUM_3__n0000<26>cy (XLXI_18/DDS1/f1_LPM_ACCUM_3__n0000<26>_cyo)
     MUXCY:CI->O           1   0.041   0.000  XLXI_18/DDS1/f1_LPM_ACCUM_3__n0000<27>cy (XLXI_18/DDS1/f1_LPM_ACCUM_3__n0000<27>_cyo)
     MUXCY:CI->O           1   0.041   0.000  XLXI_18/DDS1/f1_LPM_ACCUM_3__n0000<28>cy (XLXI_18/DDS1/f1_LPM_ACCUM_3__n0000<28>_cyo)
     MUXCY:CI->O           1   0.041   0.000  XLXI_18/DDS1/f1_LPM_ACCUM_3__n0000<29>cy (XLXI_18/DDS1/f1_LPM_ACCUM_3__n0000<29>_cyo)
     MUXCY:CI->O           0   0.041   0.000  XLXI_18/DDS1/f1_LPM_ACCUM_3__n0000<30>cy (XLXI_18/DDS1/f1_LPM_ACCUM_3__n0000<30>_cyo)
     XORCY:CI->O           1   0.868   0.440  XLXI_18/DDS1/f1_LPM_ACCUM_3__n0000<31>_xor (XLXI_18/DDS1/f1__n0000<31>)
     LUT4_L:I3->LO         1   0.313   0.000  XLXI_18/DDS1/f1__n0001<31>1 (XLXI_18/DDS1/f1__n0001<31>)
     FDCPE:D                   0.234          XLXI_18/DDS1/f1_31
    ----------------------------------------
    Total                      7.331ns (4.630ns logic, 2.701ns route)
                                       (63.2% logic, 36.8% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'adc_clk0_i'
  Total number of paths / destination ports: 498042 / 572
-------------------------------------------------------------------------
Offset:              9.873ns (Levels of Logic = 32)
  Source:            adc_a_i<0> (PAD)
  Destination:       XLXI_18/filter1/n2_23 (FF)
  Destination Clock: adc_clk0_i rising

  Data Path: adc_a_i<0> to XLXI_18/filter1/n2_23
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             2   0.919   0.561  adc_a_i_0_IBUF (adc_a_i_0_IBUF)
     LUT3:I1->O            1   0.313   0.000  Mmux_ADC_SEL_ADC_SEL<0>111_F (N3834)
     MUXF5:I0->O           3   0.340   0.610  Mmux_ADC_SEL_ADC_SEL<0>111 (XLXI_18/XLXN_22<0>)
     LUT1:I0->O            1   0.313   0.000  XLXI_18/XLXN_22<0>_rt (XLXI_18/XLXN_22<0>_rt)
     MUXCY:S->O            1   0.377   0.000  libera_pll_XLXI_18/mul1/neg<0>cy (libera_pll_XLXI_18/mul1/neg<0>_cyo)
     MUXCY:CI->O           1   0.042   0.000  libera_pll_XLXI_18/mul1/neg<1>cy (libera_pll_XLXI_18/mul1/neg<1>_cyo)
     MUXCY:CI->O           1   0.042   0.000  libera_pll_XLXI_18/mul1/neg<2>cy (libera_pll_XLXI_18/mul1/neg<2>_cyo)
     MUXCY:CI->O           1   0.042   0.000  libera_pll_XLXI_18/mul1/neg<3>cy (libera_pll_XLXI_18/mul1/neg<3>_cyo)
     MUXCY:CI->O           1   0.042   0.000  libera_pll_XLXI_18/mul1/neg<4>cy (libera_pll_XLXI_18/mul1/neg<4>_cyo)
     MUXCY:CI->O           1   0.042   0.000  libera_pll_XLXI_18/mul1/neg<5>cy (libera_pll_XLXI_18/mul1/neg<5>_cyo)
     MUXCY:CI->O           1   0.042   0.000  libera_pll_XLXI_18/mul1/neg<6>cy (libera_pll_XLXI_18/mul1/neg<6>_cyo)
     MUXCY:CI->O           1   0.042   0.000  libera_pll_XLXI_18/mul1/neg<7>cy (libera_pll_XLXI_18/mul1/neg<7>_cyo)
     MUXCY:CI->O           1   0.042   0.000  libera_pll_XLXI_18/mul1/neg<8>cy (libera_pll_XLXI_18/mul1/neg<8>_cyo)
     MUXCY:CI->O           1   0.042   0.000  libera_pll_XLXI_18/mul1/neg<9>cy (libera_pll_XLXI_18/mul1/neg<9>_cyo)
     MUXCY:CI->O           1   0.042   0.000  libera_pll_XLXI_18/mul1/neg<10>cy (libera_pll_XLXI_18/mul1/neg<10>_cyo)
     MUXCY:CI->O           1   0.042   0.000  libera_pll_XLXI_18/mul1/neg<11>cy (libera_pll_XLXI_18/mul1/neg<11>_cyo)
     MUXCY:CI->O           1   0.042   0.000  libera_pll_XLXI_18/mul1/neg<12>cy (libera_pll_XLXI_18/mul1/neg<12>_cyo)
     MUXCY:CI->O           0   0.042   0.000  libera_pll_XLXI_18/mul1/neg<13>cy (libera_pll_XLXI_18/mul1/neg<13>_cyo)
     XORCY:CI->O          11   0.868   0.641  libera_pll_XLXI_18/mul1/neg<14>_xor (XLXI_18/mul1/neg<14>)
     LUT3:I2->O            0   0.313   0.000  XLXI_18/XLXN_22<31>1 (XLXI_18/XLXN_22<31>)
     MUXCY:DI->O           1   0.595   0.000  XLXI_18/filter1/filter_1__n0014<14>cy (XLXI_18/filter1/filter_1__n0014<14>_cyo)
     MUXCY:CI->O           1   0.042   0.000  XLXI_18/filter1/filter_1__n0014<15>cy (XLXI_18/filter1/filter_1__n0014<15>_cyo)
     MUXCY:CI->O           1   0.042   0.000  XLXI_18/filter1/filter_1__n0014<16>cy (XLXI_18/filter1/filter_1__n0014<16>_cyo)
     MUXCY:CI->O           1   0.042   0.000  XLXI_18/filter1/filter_1__n0014<17>cy (XLXI_18/filter1/filter_1__n0014<17>_cyo)
     MUXCY:CI->O           1   0.042   0.000  XLXI_18/filter1/filter_1__n0014<18>cy (XLXI_18/filter1/filter_1__n0014<18>_cyo)
     MUXCY:CI->O           1   0.042   0.000  XLXI_18/filter1/filter_1__n0014<19>cy (XLXI_18/filter1/filter_1__n0014<19>_cyo)
     MUXCY:CI->O           1   0.042   0.000  XLXI_18/filter1/filter_1__n0014<20>cy (XLXI_18/filter1/filter_1__n0014<20>_cyo)
     MUXCY:CI->O           1   0.042   0.000  XLXI_18/filter1/filter_1__n0014<21>cy (XLXI_18/filter1/filter_1__n0014<21>_cyo)
     XORCY:CI->O           1   0.868   0.533  XLXI_18/filter1/filter_1__n0014<22>_xor (XLXI_18/filter1/_n0014<22>)
     LUT2_L:I0->LO         1   0.313   0.000  XLXI_18/filter1/filter_1__n0007<22>lut (XLXI_18/filter1/N202)
     MUXCY:S->O            0   0.377   0.000  XLXI_18/filter1/filter_1__n0007<22>cy (XLXI_18/filter1/filter_1__n0007<22>_cyo)
     XORCY:CI->O           1   0.868   0.000  XLXI_18/filter1/filter_1__n0007<23>_xor (XLXI_18/filter1/_n0007<23>)
     FDR:D                     0.234          XLXI_18/filter1/n2_23
    ----------------------------------------
    Total                      9.873ns (7.528ns logic, 2.345ns route)
                                       (76.2% logic, 23.8% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'adc_clk0_i'
  Total number of paths / destination ports: 1137 / 172
-------------------------------------------------------------------------
Offset:              4.748ns (Levels of Logic = 6)
  Source:            XLXI_18/filter1/n6_16 (FF)
  Destination:       i_ila_4CH:trig0<5> (PAD)
  Source Clock:      adc_clk0_i rising

  Data Path: XLXI_18/filter1/n6_16 to i_ila_4CH:trig0<5>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q             14   0.374   0.765  XLXI_18/filter1/n6_16 (XLXI_18/filter1/n6_16)
     LUT3_L:I1->LO         1   0.313   0.000  config_i<5>_mmx_out1411_F (N4008)
     MUXF5:I0->O           3   0.340   0.610  config_i<5>_mmx_out1411 (mux_1_config_i<5>_mmx_out14)
     LUT3:I0->O            1   0.313   0.506  F_ERR_out<5>106 (F_ERR_out<5>_map1118)
     LUT4:I1->O            2   0.313   0.561  F_ERR_out<5>115 (mux_1_F_ERR_out<5>)
     LUT3:I1->O            1   0.313   0.000  ILA4_CH0<5>29_G (N3775)
     MUXF5:I1->O           0   0.340   0.000  ILA4_CH0<5>29 (ILA4_CH0<5>)
    ila_4CH:trig0<5>           0.000          i_ila_4CH
    ----------------------------------------
    Total                      4.748ns (2.306ns logic, 2.442ns route)
                                       (48.6% logic, 51.4% route)

=========================================================================
Timing constraint: Default path analysis
  Total number of paths / destination ports: 1843 / 403
-------------------------------------------------------------------------
Delay:               6.481ns (Levels of Logic = 8)
  Source:            config_i<4> (PAD)
  Destination:       i_ila_4CH:trig0<14> (PAD)

  Data Path: config_i<4> to i_ila_4CH:trig0<14>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O            78   0.919   0.983  config_i_4_IBUF (config_i_4_IBUF)
     LUT4:I1->O           14   0.313   0.792  Ker41 (N4)
     LUT4:I0->O            1   0.313   0.440  F_ERR_out<14>4 (F_ERR_out<14>_map747)
     LUT4_L:I3->LO         1   0.313   0.128  F_ERR_out<14>7 (F_ERR_out<14>_map749)
     LUT4:I2->O            3   0.313   0.495  F_ERR_out<14>28 (F_ERR_out<14>_map756)
     LUT3:I2->O            1   0.313   0.506  F_ERR_out<14>80 (F_ERR_out<14>)
     LUT3:I1->O            1   0.313   0.000  ILA4_CH0<14>28_G (N3815)
     MUXF5:I1->O           0   0.340   0.000  ILA4_CH0<14>28 (ILA4_CH0<14>)
    ila_4CH:trig0<14>          0.000          i_ila_4CH
    ----------------------------------------
    Total                      6.481ns (3.137ns logic, 3.344ns route)
                                       (48.4% logic, 51.6% route)

=========================================================================
CPU : 64.00 / 64.41 s | Elapsed : 64.00 / 64.00 s
 
--> 

Total memory usage is 190088 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :  491 (   0 filtered)
Number of infos    :    0 (   0 filtered)