# BEGIN Project Options
SET flowvendor = Foundation_iSE
SET vhdlsim = True
SET verilogsim = True
SET workingdirectory = C:\DESIGNS\FPGA\Custom_Libera
SET speedgrade = -6
SET simulationfiles = Behavioral
SET asysymbol = True
SET addpads = False
SET device = xc2vp30
SET implementationfiletype = Edif
SET busformat = BusFormatAngleBracketNotRipped
SET foundationsym = False
SET package = ff1152
SET createndf = False
SET designentry = VHDL
SET devicefamily = virtex2p
SET formalverification = False
SET removerpms = False
# END Project Options
# BEGIN Select
SELECT Dual_Port_Block_Memory family Xilinx,_Inc. 6.2
# END Select
# BEGIN Parameters
CSET port_a_init_value=0
CSET port_b_init_pin=false
CSET port_b_enable_pin_polarity=Active_High
CSET port_a_additional_output_pipe_stages=0
CSET port_b_initialization_pin_polarity=Active_High
CSET select_primitive=16kx1
CSET port_a_init_pin=false
CSET port_a_handshaking_pins=false
CSET port_b_active_clock_edge=Rising_Edge_Triggered
CSET global_init_value=0
CSET port_a_enable_pin_polarity=Active_High
CSET port_b_init_value=0
CSET depth_a=32
CSET depth_b=32
CSET port_a_write_enable_polarity=Active_High
CSET component_name=dpram32x32
CSET write_mode_port_a=Read_After_Write
CSET configuration_port_a=Read_Only
CSET port_a_enable_pin=false
CSET write_mode_port_b=Read_After_Write
CSET configuration_port_b=Write_Only
CSET port_b_register_inputs=false
CSET primitive_selection=Optimize_For_Area
CSET width_a=32
CSET width_b=32
CSET port_a_active_clock_edge=Rising_Edge_Triggered
CSET port_b_additional_output_pipe_stages=0
CSET port_b_write_enable_polarity=Active_High
CSET port_a_register_inputs=false
CSET port_b_handshaking_pins=false
CSET port_a_initialization_pin_polarity=Active_High
CSET port_b_enable_pin=false
# END Parameters
GENERATE