Release 8.1i - Bitgen I.24
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
Loading device for application Rf_Device from file '2vp30.nph' in environment
C:\Xilinx.
   "Custom_libera_top" is an NCD, version 3.1, device xc2vp30, package ff1152,
speed -6
Opened constraints file Custom_libera_top.pcf.

Thu Nov 16 10:26:50 2006

C:\Xilinx\bin\nt\bitgen.exe -intstyle ise -w -g DebugBitstream:No -g Binary:yes -g CRC:Enable -g ConfigRate:4 -g CclkPin:PullUp -g M0Pin:PullUp -g M1Pin:PullUp -g M2Pin:PullUp -g ProgPin:PullUp -g DonePin:PullUp -g PowerdownPin:PullUp -g TckPin:PullUp -g TdiPin:PullUp -g TdoPin:PullNone -g TmsPin:PullUp -g UnusedPin:PullDown -g UserID:0x12345 -g DCMShutdown:Disable -g DisableBandgap:No -g DCIUpdateMode:AsRequired -g StartUpClk:CClk -g DONE_cycle:4 -g GTS_cycle:5 -g GWE_cycle:6 -g LCK_cycle:NoWait -g Security:None -g DonePipe:No -g DriveDone:No -g Encrypt:No Custom_libera_top.ncd 

Summary of Bitgen Options:
+----------------------+----------------------+
| Option Name          | Current Setting      |
+----------------------+----------------------+
| Compress             | (Not Specified)*     |
+----------------------+----------------------+
| Readback             | (Not Specified)*     |
+----------------------+----------------------+
| CRC                  | Enable**             |
+----------------------+----------------------+
| DebugBitstream       | No**                 |
+----------------------+----------------------+
| ConfigRate           | 4**                  |
+----------------------+----------------------+
| StartupClk           | Cclk**               |
+----------------------+----------------------+
| DCMShutdown          | Disable**            |
+----------------------+----------------------+
| DisableBandgap       | No**                 |
+----------------------+----------------------+
| CclkPin              | Pullup**             |
+----------------------+----------------------+
| DonePin              | Pullup**             |
+----------------------+----------------------+
| HswapenPin           | Pullup*              |
+----------------------+----------------------+
| M0Pin                | Pullup**             |
+----------------------+----------------------+
| M1Pin                | Pullup**             |
+----------------------+----------------------+
| M2Pin                | Pullup**             |
+----------------------+----------------------+
| PowerdownPin         | Pullup**             |
+----------------------+----------------------+
| ProgPin              | Pullup**             |
+----------------------+----------------------+
| TckPin               | Pullup**             |
+----------------------+----------------------+
| TdiPin               | Pullup**             |
+----------------------+----------------------+
| TdoPin               | Pullnone             |
+----------------------+----------------------+
| TmsPin               | Pullup**             |
+----------------------+----------------------+
| UnusedPin            | Pulldown**           |
+----------------------+----------------------+
| GWE_cycle            | 6**                  |
+----------------------+----------------------+
| GTS_cycle            | 5**                  |
+----------------------+----------------------+
| LCK_cycle            | NoWait**             |
+----------------------+----------------------+
| Match_cycle          | Auto*                |
+----------------------+----------------------+
| DONE_cycle           | 4**                  |
+----------------------+----------------------+
| Persist              | No*                  |
+----------------------+----------------------+
| DriveDone            | No**                 |
+----------------------+----------------------+
| DonePipe             | No**                 |
+----------------------+----------------------+
| Security             | None**               |
+----------------------+----------------------+
| UserID               | 0x12345              |
+----------------------+----------------------+
| ActivateGclk         | No*                  |
+----------------------+----------------------+
| ActiveReconfig       | No*                  |
+----------------------+----------------------+
| PartialMask0         | (Not Specified)*     |
+----------------------+----------------------+
| PartialMask1         | (Not Specified)*     |
+----------------------+----------------------+
| PartialMask2         | (Not Specified)*     |
+----------------------+----------------------+
| PartialGclk          | (Not Specified)*     |
+----------------------+----------------------+
| PartialLeft          | (Not Specified)*     |
+----------------------+----------------------+
| PartialRight         | (Not Specified)*     |
+----------------------+----------------------+
| Encrypt              | No**                 |
+----------------------+----------------------+
| Key0                 | pick*                |
+----------------------+----------------------+
| Key1                 | pick*                |
+----------------------+----------------------+
| Key2                 | pick*                |
+----------------------+----------------------+
| Key3                 | pick*                |
+----------------------+----------------------+
| Key4                 | pick*                |
+----------------------+----------------------+
| Key5                 | pick*                |
+----------------------+----------------------+
| Keyseq0              | M*                   |
+----------------------+----------------------+
| Keyseq1              | M*                   |
+----------------------+----------------------+
| Keyseq2              | M*                   |
+----------------------+----------------------+
| Keyseq3              | M*                   |
+----------------------+----------------------+
| Keyseq4              | M*                   |
+----------------------+----------------------+
| Keyseq5              | M*                   |
+----------------------+----------------------+
| KeyFile              | (Not Specified)*     |
+----------------------+----------------------+
| StartKey             | 0*                   |
+----------------------+----------------------+
| StartCBC             | pick*                |
+----------------------+----------------------+
| FreezeDCI            | No*                  |
+----------------------+----------------------+
| DCIUpdateMode        | AsRequired**         |
+----------------------+----------------------+
| IEEE1532             | No*                  |
+----------------------+----------------------+
| Binary               | Yes                  |
+----------------------+----------------------+
 *  Default setting.
 ** The specified setting matches the default setting.

Running DRC.
WARNING:PhysDesignRules:367 - The signal <ddr2high_ldqs_pad_io_IBUF> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <ddr2high_udqsn_pad_io_IBUF> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <ddr2high_ldqsn_pad_io_IBUF> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <adc_d_dat_pad_i<0>_IBUF> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <adc_d_dat_pad_i<1>_IBUF> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <adc_d_dat_pad_i<2>_IBUF> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <adc_d_dat_pad_i<3>_IBUF> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <adc_d_dat_pad_i<4>_IBUF> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <adc_d_dat_pad_i<5>_IBUF> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <adc_d_dat_pad_i<6>_IBUF> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <adc_d_dat_pad_i<7>_IBUF> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <adc_d_dat_pad_i<8>_IBUF> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <adc_d_dat_pad_i<9>_IBUF> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <ddr2low_udqs_pad_io_IBUF> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <ddr2high_data_pad_io<0>_IBUF> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <ddr2high_data_pad_io<1>_IBUF> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <ddr2high_data_pad_io<2>_IBUF> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <ddr2high_data_pad_io<3>_IBUF> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <ddr2high_data_pad_io<4>_IBUF> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <ddr2high_data_pad_io<5>_IBUF> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <ddr2high_data_pad_io<6>_IBUF> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <ddr2high_data_pad_io<7>_IBUF> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <ddr2high_data_pad_io<8>_IBUF> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <ddr2high_data_pad_io<9>_IBUF> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <ddr2low_ldqs_pad_io_IBUF> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <DIO<9>_IBUF> is incomplete. The signal
   does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <adc_d_dat_pad_i<10>_IBUF> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <adc_d_dat_pad_i<11>_IBUF> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <adc_d_dat_pad_i<12>_IBUF> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <adc_d_dat_pad_i<13>_IBUF> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <ddr2high_data_pad_io<10>_IBUF> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <ddr2high_data_pad_io<11>_IBUF> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <ddr2high_data_pad_io<12>_IBUF> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <ddr2high_data_pad_io<13>_IBUF> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <ddr2high_data_pad_io<14>_IBUF> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <ddr2high_data_pad_io<15>_IBUF> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <ddr2low_udqsn_pad_io_IBUF> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <ddr2low_ldqsn_pad_io_IBUF> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <DIO<10>_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <DIO<11>_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <DIO<12>_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <DIO<21>_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <DIO<13>_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <DIO<22>_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <DIO<14>_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <DIO<23>_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <DIO<15>_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <DIO<16>_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <DIO<24>_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <DIO<18>_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <ddr2low_data_pad_io<10>_IBUF> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <ddr2low_data_pad_io<11>_IBUF> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <ddr2low_data_pad_io<12>_IBUF> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <ddr2low_data_pad_io<13>_IBUF> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <ddr2low_data_pad_io<14>_IBUF> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <ddr2low_data_pad_io<15>_IBUF> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <ddr2low_data_pad_io<0>_IBUF> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <ddr2low_data_pad_io<1>_IBUF> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <ddr2low_data_pad_io<2>_IBUF> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <ddr2low_data_pad_io<3>_IBUF> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <ddr2low_data_pad_io<4>_IBUF> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <ddr2low_data_pad_io<5>_IBUF> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <ddr2low_data_pad_io<6>_IBUF> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <ddr2low_data_pad_io<7>_IBUF> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <ddr2low_data_pad_io<8>_IBUF> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <ddr2low_data_pad_io<9>_IBUF> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <ddr2high_udqs_pad_io_IBUF> is
   incomplete. The signal does not drive any load pins in the design.
DRC detected 0 errors and 67 warnings.
Creating bit map...
Saving bit stream in "custom_libera_top.bit".
Saving bit stream in "custom_libera_top.bin".
Bitstream generation is complete.