Cern - Xilinx Design Summary

Account

CUSTOM_LIBERA Project Status
Project File:	Custom_Libera.ise	Current State:	Programming File Generated
Module Name:	Custom_libera_top	Errors:	No Errors
Target Device:	xc2vp30-6ff1152	Warnings:	557 Warnings
Product Version:	ISE, 8.1i	Updated:	?r 6. gru 09:15:32 2006

Device Utilization Summary
Logic Utilization	Used	Available	Utilization	Note(s)
Number of Slice Flip Flops	2,289	27,392	8%
Number of 4 input LUTs	2,231	27,392	8%
Logic Distribution
Number of occupied Slices	2,049	13,696	14%
Number of Slices containing only related logic	2,049	2,049	100%
Number of Slices containing unrelated logic	0	2,049	0%
Total Number 4 input LUTs	2,656	27,392	9%
Number used as logic	2,231
Number used as a route-thru	175
Number used as Shift registers	250
Number of bonded IOBs	252	644	39%
IOB Flip Flops	94
IOB Master Pads	2
IOB Slave Pads	2
Number of PPC405s	0	2	0%
Number of Block RAMs	94	136	69%
Number of GCLKs	3	16	18%
Number of BSCANs	1	1	100%
Number of GTs	0	8	0%
Number of GT10s	0	0	0%
Number of RPM macros	24
Total equivalent gate count for design	6,215,263
Additional JTAG gate count for IOBs	12,096

Performance Summary
Final Timing Score:	135	Pinout Data:	Pinout Report
Routing Results:	All Signals Completely Routed	Clock Data:	Clock Report
Timing Constraints:	1 Failing Constraint