Release 8.1i Map I.24 Xilinx Mapping Report File for Design 'Custom_libera_top' Design Information ------------------ Command Line : C:\Xilinx\bin\nt\map.exe -ise C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera.ise -intstyle ise -p xc2vp30-ff1152-6 -cm speed -gf C:/DESIGNS/FPGA/Custom_Libera/Custom_libera_top_map.ncd -gm leverage -pr b -k 4 -c 100 -tx off -o Custom_libera_top_map.ncd Custom_libera_top.ngd Custom_libera_top.pcf Target Device : xc2vp30 Target Package : ff1152 Target Speed : -6 Mapper Version : virtex2p -- $Revision: 1.34 $ Mapped Date : Thu Nov 16 10:13:58 2006 Design Summary -------------- Number of errors: 0 Number of warnings: 82 Logic Utilization: Number of Slice Flip Flops: 2,289 out of 27,392 8% Number of 4 input LUTs: 2,231 out of 27,392 8% Logic Distribution: Number of occupied Slices: 2,049 out of 13,696 14% Number of Slices containing only related logic: 2,049 out of 2,049 100% Number of Slices containing unrelated logic: 0 out of 2,049 0% *See NOTES below for an explanation of the effects of unrelated logic Total Number 4 input LUTs: 2,656 out of 27,392 9% Number used as logic: 2,231 Number used as a route-thru: 175 Number used as Shift registers: 250 Number of bonded IOBs: 252 out of 644 39% IOB Flip Flops: 94 IOB Master Pads: 2 IOB Slave Pads: 2 Number of PPC405s: 0 out of 2 0% Number of Block RAMs: 94 out of 136 69% Number of GCLKs: 3 out of 16 18% Number of BSCANs: 1 out of 1 100% Number of GTs: 0 out of 8 0% Number of GT10s: 0 out of 0 0% Number of RPM macros: 24 Total equivalent gate count for design: 6,215,263 Additional JTAG gate count for IOBs: 12,096 Peak Memory Usage: 288 MB NOTES: Related logic is defined as being logic that shares connectivity - e.g. two LUTs are "related" if they share common inputs. When assembling slices, Map gives priority to combine logic that is related. Doing so results in the best timing performance. Unrelated logic shares no connectivity. Map will only begin packing unrelated logic into a slice once 99% of the slices are occupied through related logic packing. Note that once logic distribution reaches the 99% level through related logic packing, this does not mean the device is completely utilized. Unrelated logic packing will then begin, continuing until all usable LUTs and FFs are occupied. Depending on your timing budget, increased levels of unrelated logic packing may adversely affect the overall timing performance of your design. Table of Contents ----------------- Section 1 - Errors Section 2 - Warnings Section 3 - Informational Section 4 - Removed Logic Summary Section 5 - Removed Logic Section 6 - IOB Properties Section 7 - RPMs Section 8 - Guide Report Section 9 - Area Group Summary Section 10 - Modular Design Summary Section 11 - Timing Report Section 12 - Configuration String Information Section 13 - Additional Device Resource Counts Section 1 - Errors ------------------ Section 2 - Warnings -------------------- WARNING:LIT:243 - Logical network PLL/chipscope/control0<35> has no load. WARNING:LIT:395 - The above warning message base_net_load_rule is repeated 189 more times for the following (max. 5 shown): PLL/chipscope/control0<34>, PLL/chipscope/control0<33>, PLL/chipscope/control0<32>, PLL/chipscope/control0<31>, PLL/chipscope/control0<30> To see the details of these warning messages, please use the -detail switch. WARNING:MapLib:701 - Signal lemo_trig_ppad_i connected to top level port lemo_trig_ppad_i has been removed. WARNING:MapLib:701 - Signal lemo_trig_npad_i connected to top level port lemo_trig_npad_i has been removed. WARNING:MapLib:701 - Signal lemo_pm_ppad_i connected to top level port lemo_pm_ppad_i has been removed. WARNING:MapLib:701 - Signal lemo_pm_npad_i connected to top level port lemo_pm_npad_i has been removed. WARNING:MapLib:701 - Signal lemo_mclk_ppad_i connected to top level port lemo_mclk_ppad_i has been removed. WARNING:MapLib:701 - Signal lemo_mclk_npad_i connected to top level port lemo_mclk_npad_i has been removed. WARNING:MapLib:701 - Signal lemo_sclk_ppad_i connected to top level port lemo_sclk_ppad_i has been removed. WARNING:MapLib:701 - Signal lemo_sclk_npad_i connected to top level port lemo_sclk_npad_i has been removed. WARNING:LIT:176 - Clock buffer is designated to drive clock loads. BUFGMUX symbol "physical_group_sbc_csn_pad_i_BUFGP/sbc_csn_pad_i_BUFGP/BUFG" (output signal=sbc_csn_pad_i_BUFGP) has a mix of clock and non-clock loads. The non-clock loads are: Pin I1 of _n0025_INV1 WARNING:Pack:266 - The function generator PLL/Mshift_F_ERR_Result<6>161_G failed to merge with F5 multiplexer PLL/Mshift_F_ERR_Result<6>161. There is a conflict for the FXMUX. The design will exhibit suboptimal timing. WARNING:Pack:266 - The function generator PLL/Mshift_F_ERR_Result<7>161_G failed to merge with F5 multiplexer PLL/Mshift_F_ERR_Result<7>161. There is a conflict for the FXMUX. The design will exhibit suboptimal timing. WARNING:Pack:266 - The function generator PLL/Ker01_G failed to merge with F5 multiplexer PLL/Ker01. There is a conflict for the FXMUX. The design will exhibit suboptimal timing. WARNING:Pack:266 - The function generator PLL/Ker11_G failed to merge with F5 multiplexer PLL/Ker11. There is a conflict for the FXMUX. The design will exhibit suboptimal timing. WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not drive any load pins in the design. WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not drive any load pins in the design. WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not drive any load pins in the design. WARNING:PhysDesignRules:367 - The signal _IBUF> is incomplete. The signal does not drive any load pins in the design. WARNING:PhysDesignRules:367 - The signal _IBUF> is incomplete. The signal does not drive any load pins in the design. WARNING:PhysDesignRules:367 - The signal _IBUF> is incomplete. The signal does not drive any load pins in the design. WARNING:PhysDesignRules:367 - The signal _IBUF> is incomplete. The signal does not drive any load pins in the design. WARNING:PhysDesignRules:367 - The signal _IBUF> is incomplete. The signal does not drive any load pins in the design. WARNING:PhysDesignRules:367 - The signal _IBUF> is incomplete. The signal does not drive any load pins in the design. WARNING:PhysDesignRules:367 - The signal _IBUF> is incomplete. The signal does not drive any load pins in the design. WARNING:PhysDesignRules:367 - The signal _IBUF> is incomplete. The signal does not drive any load pins in the design. WARNING:PhysDesignRules:367 - The signal _IBUF> is incomplete. The signal does not drive any load pins in the design. WARNING:PhysDesignRules:367 - The signal _IBUF> is incomplete. The signal does not drive any load pins in the design. WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not drive any load pins in the design. WARNING:PhysDesignRules:367 - The signal _IBUF> is incomplete. The signal does not drive any load pins in the design. WARNING:PhysDesignRules:367 - The signal _IBUF> is incomplete. The signal does not drive any load pins in the design. WARNING:PhysDesignRules:367 - The signal _IBUF> is incomplete. The signal does not drive any load pins in the design. WARNING:PhysDesignRules:367 - The signal _IBUF> is incomplete. The signal does not drive any load pins in the design. WARNING:PhysDesignRules:367 - The signal _IBUF> is incomplete. The signal does not drive any load pins in the design. WARNING:PhysDesignRules:367 - The signal _IBUF> is incomplete. The signal does not drive any load pins in the design. WARNING:PhysDesignRules:367 - The signal _IBUF> is incomplete. The signal does not drive any load pins in the design. WARNING:PhysDesignRules:367 - The signal _IBUF> is incomplete. The signal does not drive any load pins in the design. WARNING:PhysDesignRules:367 - The signal _IBUF> is incomplete. The signal does not drive any load pins in the design. WARNING:PhysDesignRules:367 - The signal _IBUF> is incomplete. The signal does not drive any load pins in the design. WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not drive any load pins in the design. WARNING:PhysDesignRules:367 - The signal _IBUF> is incomplete. The signal does not drive any load pins in the design. WARNING:PhysDesignRules:367 - The signal _IBUF> is incomplete. The signal does not drive any load pins in the design. WARNING:PhysDesignRules:367 - The signal _IBUF> is incomplete. The signal does not drive any load pins in the design. WARNING:PhysDesignRules:367 - The signal _IBUF> is incomplete. The signal does not drive any load pins in the design. WARNING:PhysDesignRules:367 - The signal _IBUF> is incomplete. The signal does not drive any load pins in the design. WARNING:PhysDesignRules:367 - The signal _IBUF> is incomplete. The signal does not drive any load pins in the design. WARNING:PhysDesignRules:367 - The signal _IBUF> is incomplete. The signal does not drive any load pins in the design. WARNING:PhysDesignRules:367 - The signal _IBUF> is incomplete. The signal does not drive any load pins in the design. WARNING:PhysDesignRules:367 - The signal _IBUF> is incomplete. The signal does not drive any load pins in the design. WARNING:PhysDesignRules:367 - The signal _IBUF> is incomplete. The signal does not drive any load pins in the design. WARNING:PhysDesignRules:367 - The signal _IBUF> is incomplete. The signal does not drive any load pins in the design. WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not drive any load pins in the design. WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not drive any load pins in the design. WARNING:PhysDesignRules:367 - The signal _IBUF> is incomplete. The signal does not drive any load pins in the design. WARNING:PhysDesignRules:367 - The signal _IBUF> is incomplete. The signal does not drive any load pins in the design. WARNING:PhysDesignRules:367 - The signal _IBUF> is incomplete. The signal does not drive any load pins in the design. WARNING:PhysDesignRules:367 - The signal _IBUF> is incomplete. The signal does not drive any load pins in the design. WARNING:PhysDesignRules:367 - The signal _IBUF> is incomplete. The signal does not drive any load pins in the design. WARNING:PhysDesignRules:367 - The signal _IBUF> is incomplete. The signal does not drive any load pins in the design. WARNING:PhysDesignRules:367 - The signal _IBUF> is incomplete. The signal does not drive any load pins in the design. WARNING:PhysDesignRules:367 - The signal _IBUF> is incomplete. The signal does not drive any load pins in the design. WARNING:PhysDesignRules:367 - The signal _IBUF> is incomplete. The signal does not drive any load pins in the design. WARNING:PhysDesignRules:367 - The signal _IBUF> is incomplete. The signal does not drive any load pins in the design. WARNING:PhysDesignRules:367 - The signal _IBUF> is incomplete. The signal does not drive any load pins in the design. WARNING:PhysDesignRules:367 - The signal _IBUF> is incomplete. The signal does not drive any load pins in the design. WARNING:PhysDesignRules:367 - The signal _IBUF> is incomplete. The signal does not drive any load pins in the design. WARNING:PhysDesignRules:367 - The signal _IBUF> is incomplete. The signal does not drive any load pins in the design. WARNING:PhysDesignRules:367 - The signal _IBUF> is incomplete. The signal does not drive any load pins in the design. WARNING:PhysDesignRules:367 - The signal _IBUF> is incomplete. The signal does not drive any load pins in the design. WARNING:PhysDesignRules:367 - The signal _IBUF> is incomplete. The signal does not drive any load pins in the design. WARNING:PhysDesignRules:367 - The signal _IBUF> is incomplete. The signal does not drive any load pins in the design. WARNING:PhysDesignRules:367 - The signal _IBUF> is incomplete. The signal does not drive any load pins in the design. WARNING:PhysDesignRules:367 - The signal _IBUF> is incomplete. The signal does not drive any load pins in the design. WARNING:PhysDesignRules:367 - The signal _IBUF> is incomplete. The signal does not drive any load pins in the design. WARNING:PhysDesignRules:367 - The signal _IBUF> is incomplete. The signal does not drive any load pins in the design. WARNING:PhysDesignRules:367 - The signal _IBUF> is incomplete. The signal does not drive any load pins in the design. WARNING:PhysDesignRules:367 - The signal _IBUF> is incomplete. The signal does not drive any load pins in the design. WARNING:PhysDesignRules:367 - The signal _IBUF> is incomplete. The signal does not drive any load pins in the design. WARNING:PhysDesignRules:367 - The signal _IBUF> is incomplete. The signal does not drive any load pins in the design. WARNING:PhysDesignRules:367 - The signal _IBUF> is incomplete. The signal does not drive any load pins in the design. WARNING:PhysDesignRules:367 - The signal _IBUF> is incomplete. The signal does not drive any load pins in the design. WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not drive any load pins in the design. Section 3 - Informational ------------------------- INFO:MapLib:562 - No environment variables are currently set. INFO:MapLib:535 - The following Virtex BUFG(s) is/are being retargetted to Virtex2 BUFGMUX(s) with input tied to I0 and Select pin tied to constant 0: BUFG symbol "DIO_2_OBUF_BUFG" (output signal=DIO_2_OBUF), BUFG symbol "PLL/chipscope/i_icon/icon/u_icon/i_yes_bscan/u_bs/i_bufg/u_bufg" (output signal=PLL/chipscope/control0<0>), BUFGP symbol "sbc_csn_pad_i_BUFGP" (output signal=sbc_csn_pad_i_BUFGP) INFO:LIT:244 - All of the single ended outputs in this design are using slew rate limited output drivers. The delay on speed critical single ended outputs can be dramatically reduced by designating them as fast outputs in the schematic. Section 4 - Removed Logic Summary --------------------------------- 182 block(s) removed 524 block(s) optimized away 327 signal(s) removed Section 5 - Removed Logic ------------------------- The trimmed logic report below shows the logic removed from your design due to sourceless or loadless signals, and VCC or ground connections. If the removal of a signal or symbol results in the subsequent removal of an additional signal or symbol, the message explaining that second removal will be indented. This indentation will be repeated as a chain of related logic is removed. To quickly locate the original cause for the removal of a chain of logic, look above the place where that logic is listed in the trimming report, then locate the lines that are least indented (begin at the leftmost edge). Loadless block "IBUFGDS_lemo_mclk" () removed. The signal "lemo_mclk_ppad_i" is loadless and has been removed. Loadless block "lemo_mclk_ppad_i" (PAD) removed. The signal "lemo_mclk_npad_i" is loadless and has been removed. Loadless block "lemo_mclk_npad_i" (PAD) removed. Loadless block "IBUFGDS_lemo_pm" () removed. The signal "lemo_pm_ppad_i" is loadless and has been removed. Loadless block "lemo_pm_ppad_i" (PAD) removed. The signal "lemo_pm_npad_i" is loadless and has been removed. Loadless block "lemo_pm_npad_i" (PAD) removed. Loadless block "IBUFGDS_lemo_sclk" () removed. The signal "lemo_sclk_ppad_i" is loadless and has been removed. Loadless block "lemo_sclk_ppad_i" (PAD) removed. The signal "lemo_sclk_npad_i" is loadless and has been removed. Loadless block "lemo_sclk_npad_i" (PAD) removed. Loadless block "IBUFGDS_lemo_trig" () removed. The signal "lemo_trig_ppad_i" is loadless and has been removed. Loadless block "lemo_trig_ppad_i" (PAD) removed. The signal "lemo_trig_npad_i" is loadless and has been removed. Loadless block "lemo_trig_npad_i" (PAD) removed. Loadless block "PLL/C_TABLE/BU17" (ROM) removed. Loadless block "PLL/C_TABLE/BU192" (ROM) removed. Loadless block "PLL/C_TABLE/BU367" (ROM) removed. Loadless block "PLL/chipscope/i_icon/icon/u_icon/u_cmd/u_core_id_sel/i4/fi/10/u_lut" (ROM) removed. Loadless block "PLL/chipscope/i_icon/icon/u_icon/u_cmd/u_core_id_sel/i4/fi/11/u_lut" (ROM) removed. Loadless block "PLL/chipscope/i_icon/icon/u_icon/u_cmd/u_core_id_sel/i4/fi/12/u_lut" (ROM) removed. Loadless block "PLL/chipscope/i_icon/icon/u_icon/u_cmd/u_core_id_sel/i4/fi/13/u_lut" (ROM) removed. Loadless block "PLL/chipscope/i_icon/icon/u_icon/u_cmd/u_core_id_sel/i4/fi/14/u_lut" (ROM) removed. Loadless block "PLL/chipscope/i_icon/icon/u_icon/u_cmd/u_core_id_sel/i4/fi/4/u_lut" (ROM) removed. Loadless block "PLL/chipscope/i_icon/icon/u_icon/u_cmd/u_core_id_sel/i4/fi/5/u_lut" (ROM) removed. Loadless block "PLL/chipscope/i_icon/icon/u_icon/u_cmd/u_core_id_sel/i4/fi/6/u_lut" (ROM) removed. Loadless block "PLL/chipscope/i_icon/icon/u_icon/u_cmd/u_core_id_sel/i4/fi/7/u_lut" (ROM) removed. Loadless block "PLL/chipscope/i_icon/icon/u_icon/u_cmd/u_core_id_sel/i4/fi/8/u_lut" (ROM) removed. Loadless block "PLL/chipscope/i_icon/icon/u_icon/u_cmd/u_core_id_sel/i4/fi/9/u_lut" (ROM) removed. Loadless block "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_stat/u_dsr" (ROM) removed. Loadless block "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_trig/u_tc/i_storage_qual/u_cap_ b" (ROM) removed. Loadless block "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_stat/u_dsr" (ROM) removed. Loadless block "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_trig/u_tc/i_storage_qual/u_cap_ b" (ROM) removed. The signal "PLL/chipscope/control0<35>" is sourceless and has been removed. The signal "PLL/chipscope/control0<34>" is sourceless and has been removed. The signal "PLL/chipscope/control0<33>" is sourceless and has been removed. The signal "PLL/chipscope/control0<32>" is sourceless and has been removed. The signal "PLL/chipscope/control0<31>" is sourceless and has been removed. The signal "PLL/chipscope/control0<30>" is sourceless and has been removed. The signal "PLL/chipscope/control0<29>" is sourceless and has been removed. The signal "PLL/chipscope/control0<28>" is sourceless and has been removed. The signal "PLL/chipscope/control0<27>" is sourceless and has been removed. The signal "PLL/chipscope/control0<26>" is sourceless and has been removed. The signal "PLL/chipscope/control0<25>" is sourceless and has been removed. The signal "PLL/chipscope/control0<24>" is sourceless and has been removed. The signal "PLL/chipscope/control0<23>" is sourceless and has been removed. The signal "PLL/chipscope/control0<22>" is sourceless and has been removed. The signal "PLL/chipscope/control0<21>" is sourceless and has been removed. The signal "PLL/chipscope/control0<20>" is sourceless and has been removed. The signal "PLL/chipscope/control0<19>" is sourceless and has been removed. The signal "PLL/chipscope/control0<18>" is sourceless and has been removed. The signal "PLL/chipscope/control0<17>" is sourceless and has been removed. The signal "PLL/chipscope/control0<16>" is sourceless and has been removed. The signal "PLL/chipscope/control0<15>" is sourceless and has been removed. The signal "PLL/chipscope/control0<14>" is sourceless and has been removed. The signal "PLL/chipscope/control0<13>" is sourceless and has been removed. The signal "PLL/chipscope/control0<12>" is sourceless and has been removed. The signal "PLL/chipscope/control0<11>" is sourceless and has been removed. The signal "PLL/chipscope/control0<10>" is sourceless and has been removed. The signal "PLL/chipscope/control0<9>" is sourceless and has been removed. The signal "PLL/chipscope/control0<8>" is sourceless and has been removed. The signal "PLL/chipscope/control1<35>" is sourceless and has been removed. The signal "PLL/chipscope/control1<34>" is sourceless and has been removed. The signal "PLL/chipscope/control1<33>" is sourceless and has been removed. The signal "PLL/chipscope/control1<32>" is sourceless and has been removed. The signal "PLL/chipscope/control1<31>" is sourceless and has been removed. The signal "PLL/chipscope/control1<30>" is sourceless and has been removed. The signal "PLL/chipscope/control1<29>" is sourceless and has been removed. The signal "PLL/chipscope/control1<28>" is sourceless and has been removed. The signal "PLL/chipscope/control1<27>" is sourceless and has been removed. The signal "PLL/chipscope/control1<26>" is sourceless and has been removed. The signal "PLL/chipscope/control1<25>" is sourceless and has been removed. The signal "PLL/chipscope/control1<24>" is sourceless and has been removed. The signal "PLL/chipscope/control1<23>" is sourceless and has been removed. The signal "PLL/chipscope/control1<22>" is sourceless and has been removed. The signal "PLL/chipscope/control1<21>" is sourceless and has been removed. The signal "PLL/chipscope/control1<20>" is sourceless and has been removed. The signal "PLL/chipscope/control1<19>" is sourceless and has been removed. The signal "PLL/chipscope/control1<18>" is sourceless and has been removed. The signal "PLL/chipscope/control1<17>" is sourceless and has been removed. The signal "PLL/chipscope/control1<16>" is sourceless and has been removed. The signal "PLL/chipscope/control1<15>" is sourceless and has been removed. The signal "PLL/chipscope/control1<14>" is sourceless and has been removed. The signal "PLL/chipscope/control1<13>" is sourceless and has been removed. The signal "PLL/chipscope/control1<12>" is sourceless and has been removed. The signal "PLL/chipscope/control1<11>" is sourceless and has been removed. The signal "PLL/chipscope/control1<10>" is sourceless and has been removed. The signal "PLL/chipscope/control1<9>" is sourceless and has been removed. The signal "PLL/chipscope/control1<8>" is sourceless and has been removed. The signal "PLL/chipscope/control2<35>" is sourceless and has been removed. The signal "PLL/chipscope/control2<34>" is sourceless and has been removed. The signal "PLL/chipscope/control2<33>" is sourceless and has been removed. The signal "PLL/chipscope/control2<32>" is sourceless and has been removed. The signal "PLL/chipscope/control2<31>" is sourceless and has been removed. The signal "PLL/chipscope/control2<30>" is sourceless and has been removed. The signal "PLL/chipscope/control2<29>" is sourceless and has been removed. The signal "PLL/chipscope/control2<28>" is sourceless and has been removed. The signal "PLL/chipscope/control2<27>" is sourceless and has been removed. The signal "PLL/chipscope/control2<26>" is sourceless and has been removed. The signal "PLL/chipscope/control2<25>" is sourceless and has been removed. The signal "PLL/chipscope/control2<24>" is sourceless and has been removed. The signal "PLL/chipscope/control2<23>" is sourceless and has been removed. The signal "PLL/chipscope/control2<22>" is sourceless and has been removed. The signal "PLL/chipscope/control2<21>" is sourceless and has been removed. The signal "PLL/chipscope/control2<19>" is sourceless and has been removed. The signal "PLL/chipscope/control2<18>" is sourceless and has been removed. The signal "PLL/chipscope/control2<17>" is sourceless and has been removed. The signal "PLL/chipscope/control2<16>" is sourceless and has been removed. The signal "PLL/chipscope/control2<15>" is sourceless and has been removed. The signal "PLL/chipscope/control2<11>" is sourceless and has been removed. The signal "PLL/chipscope/control2<10>" is sourceless and has been removed. The signal "PLL/chipscope/control2<7>" is sourceless and has been removed. The signal "PLL/chipscope/control3<35>" is sourceless and has been removed. The signal "PLL/chipscope/control3<34>" is sourceless and has been removed. The signal "PLL/chipscope/control3<33>" is sourceless and has been removed. The signal "PLL/chipscope/control3<32>" is sourceless and has been removed. The signal "PLL/chipscope/control3<31>" is sourceless and has been removed. The signal "PLL/chipscope/control3<30>" is sourceless and has been removed. The signal "PLL/chipscope/control3<29>" is sourceless and has been removed. The signal "PLL/chipscope/control3<28>" is sourceless and has been removed. The signal "PLL/chipscope/control3<27>" is sourceless and has been removed. The signal "PLL/chipscope/control3<26>" is sourceless and has been removed. The signal "PLL/chipscope/control3<25>" is sourceless and has been removed. The signal "PLL/chipscope/control3<24>" is sourceless and has been removed. The signal "PLL/chipscope/control3<23>" is sourceless and has been removed. The signal "PLL/chipscope/control3<22>" is sourceless and has been removed. The signal "PLL/chipscope/control3<21>" is sourceless and has been removed. The signal "PLL/chipscope/control3<19>" is sourceless and has been removed. The signal "PLL/chipscope/control3<18>" is sourceless and has been removed. The signal "PLL/chipscope/control3<17>" is sourceless and has been removed. The signal "PLL/chipscope/control3<16>" is sourceless and has been removed. The signal "PLL/chipscope/control3<15>" is sourceless and has been removed. The signal "PLL/chipscope/control3<11>" is sourceless and has been removed. The signal "PLL/chipscope/control3<10>" is sourceless and has been removed. The signal "PLL/chipscope/control3<7>" is sourceless and has been removed. The signal "PLL/C_TABLE/N1163" is sourceless and has been removed. The signal "PLL/C_TABLE/N5889" is sourceless and has been removed. The signal "PLL/C_TABLE/N10615" is sourceless and has been removed. The signal "PLL/ph_table_0/doutb<3>" is sourceless and has been removed. The signal "PLL/ph_table_1/doutb<3>" is sourceless and has been removed. The signal "PLL/ph_table_1/doutb<2>" is sourceless and has been removed. The signal "PLL/ph_table_1/doutb<1>" is sourceless and has been removed. The signal "PLL/ph_table_1/doutb<0>" is sourceless and has been removed. The signal "PLL/ph_table_1/N1" is sourceless and has been removed. The signal "PLL/ph_table_1/N0" is sourceless and has been removed. The signal "PLL/chipscope/i_icon/u_icon/icommand_sel_9" is sourceless and has been removed. Sourceless block "PLL/chipscope/i_icon/icon/u_icon/u_ctrl_out/f_ncp/3/f_cmd/6/u_lce" (ROM) removed. Sourceless block "PLL/chipscope/i_icon/icon/u_icon/u_ctrl_out/f_ncp/3/f_cmd/6/u_hce" (ROM) removed. Sourceless block "PLL/chipscope/i_icon/icon/u_icon/u_ctrl_out/f_ncp/2/f_cmd/6/u_lce" (ROM) removed. Sourceless block "PLL/chipscope/i_icon/icon/u_icon/u_ctrl_out/f_ncp/2/f_cmd/6/u_hce" (ROM) removed. Sourceless block "PLL/chipscope/i_icon/icon/u_icon/u_ctrl_out/f_ncp/1/f_cmd/6/u_lce" (ROM) removed. Sourceless block "PLL/chipscope/i_icon/icon/u_icon/u_ctrl_out/f_ncp/1/f_cmd/6/u_hce" (ROM) removed. Sourceless block "PLL/chipscope/i_icon/icon/u_icon/u_ctrl_out/f_ncp/0/f_cmd/6/u_lce" (ROM) removed. Sourceless block "PLL/chipscope/i_icon/icon/u_icon/u_ctrl_out/f_ncp/0/f_cmd/6/u_hce" (ROM) removed. The signal "PLL/chipscope/i_icon/u_icon/icommand_sel_8" is sourceless and has been removed. Sourceless block "PLL/chipscope/i_icon/icon/u_icon/u_ctrl_out/f_ncp/3/f_cmd/7/u_lce" (ROM) removed. Sourceless block "PLL/chipscope/i_icon/icon/u_icon/u_ctrl_out/f_ncp/3/f_cmd/7/u_hce" (ROM) removed. Sourceless block "PLL/chipscope/i_icon/icon/u_icon/u_ctrl_out/f_ncp/2/f_cmd/7/u_lce" (ROM) removed. Sourceless block "PLL/chipscope/i_icon/icon/u_icon/u_ctrl_out/f_ncp/2/f_cmd/7/u_hce" (ROM) removed. Sourceless block "PLL/chipscope/i_icon/icon/u_icon/u_ctrl_out/f_ncp/1/f_cmd/7/u_lce" (ROM) removed. Sourceless block "PLL/chipscope/i_icon/icon/u_icon/u_ctrl_out/f_ncp/1/f_cmd/7/u_hce" (ROM) removed. Sourceless block "PLL/chipscope/i_icon/icon/u_icon/u_ctrl_out/f_ncp/0/f_cmd/7/u_lce" (ROM) removed. Sourceless block "PLL/chipscope/i_icon/icon/u_icon/u_ctrl_out/f_ncp/0/f_cmd/7/u_hce" (ROM) removed. The signal "PLL/chipscope/i_icon/u_icon/icommand_sel_4" is sourceless and has been removed. Sourceless block "PLL/chipscope/i_icon/icon/u_icon/u_ctrl_out/f_ncp/3/f_cmd/11/u_lce" (ROM) removed. Sourceless block "PLL/chipscope/i_icon/icon/u_icon/u_ctrl_out/f_ncp/3/f_cmd/11/u_hce" (ROM) removed. Sourceless block "PLL/chipscope/i_icon/icon/u_icon/u_ctrl_out/f_ncp/2/f_cmd/11/u_lce" (ROM) removed. Sourceless block "PLL/chipscope/i_icon/icon/u_icon/u_ctrl_out/f_ncp/2/f_cmd/11/u_hce" (ROM) removed. Sourceless block "PLL/chipscope/i_icon/icon/u_icon/u_ctrl_out/f_ncp/1/f_cmd/11/u_lce" (ROM) removed. Sourceless block "PLL/chipscope/i_icon/icon/u_icon/u_ctrl_out/f_ncp/1/f_cmd/11/u_hce" (ROM) removed. Sourceless block "PLL/chipscope/i_icon/icon/u_icon/u_ctrl_out/f_ncp/0/f_cmd/11/u_lce" (ROM) removed. Sourceless block "PLL/chipscope/i_icon/icon/u_icon/u_ctrl_out/f_ncp/0/f_cmd/11/u_hce" (ROM) removed. The signal "PLL/chipscope/i_icon/u_icon/icommand_sel_3" is sourceless and has been removed. Sourceless block "PLL/chipscope/i_icon/icon/u_icon/u_ctrl_out/f_ncp/3/f_cmd/12/u_lce" (ROM) removed. Sourceless block "PLL/chipscope/i_icon/icon/u_icon/u_ctrl_out/f_ncp/3/f_cmd/12/u_hce" (ROM) removed. Sourceless block "PLL/chipscope/i_icon/icon/u_icon/u_ctrl_out/f_ncp/2/f_cmd/12/u_lce" (ROM) removed. Sourceless block "PLL/chipscope/i_icon/icon/u_icon/u_ctrl_out/f_ncp/2/f_cmd/12/u_hce" (ROM) removed. Sourceless block "PLL/chipscope/i_icon/icon/u_icon/u_ctrl_out/f_ncp/1/f_cmd/12/u_lce" (ROM) removed. Sourceless block "PLL/chipscope/i_icon/icon/u_icon/u_ctrl_out/f_ncp/1/f_cmd/12/u_hce" (ROM) removed. Sourceless block "PLL/chipscope/i_icon/icon/u_icon/u_ctrl_out/f_ncp/0/f_cmd/12/u_lce" (ROM) removed. Sourceless block "PLL/chipscope/i_icon/icon/u_icon/u_ctrl_out/f_ncp/0/f_cmd/12/u_hce" (ROM) removed. The signal "PLL/chipscope/i_icon/u_icon/icommand_sel_2" is sourceless and has been removed. Sourceless block "PLL/chipscope/i_icon/icon/u_icon/u_ctrl_out/f_ncp/3/f_cmd/13/u_lce" (ROM) removed. Sourceless block "PLL/chipscope/i_icon/icon/u_icon/u_ctrl_out/f_ncp/3/f_cmd/13/u_hce" (ROM) removed. Sourceless block "PLL/chipscope/i_icon/icon/u_icon/u_ctrl_out/f_ncp/2/f_cmd/13/u_lce" (ROM) removed. Sourceless block "PLL/chipscope/i_icon/icon/u_icon/u_ctrl_out/f_ncp/2/f_cmd/13/u_hce" (ROM) removed. Sourceless block "PLL/chipscope/i_icon/icon/u_icon/u_ctrl_out/f_ncp/1/f_cmd/13/u_lce" (ROM) removed. Sourceless block "PLL/chipscope/i_icon/icon/u_icon/u_ctrl_out/f_ncp/1/f_cmd/13/u_hce" (ROM) removed. Sourceless block "PLL/chipscope/i_icon/icon/u_icon/u_ctrl_out/f_ncp/0/f_cmd/13/u_lce" (ROM) removed. Sourceless block "PLL/chipscope/i_icon/icon/u_icon/u_ctrl_out/f_ncp/0/f_cmd/13/u_hce" (ROM) removed. The signal "PLL/chipscope/i_icon/u_icon/icommand_sel_1" is sourceless and has been removed. Sourceless block "PLL/chipscope/i_icon/icon/u_icon/u_ctrl_out/f_ncp/3/f_cmd/14/u_lce" (ROM) removed. Sourceless block "PLL/chipscope/i_icon/icon/u_icon/u_ctrl_out/f_ncp/3/f_cmd/14/u_hce" (ROM) removed. Sourceless block "PLL/chipscope/i_icon/icon/u_icon/u_ctrl_out/f_ncp/2/f_cmd/14/u_lce" (ROM) removed. Sourceless block "PLL/chipscope/i_icon/icon/u_icon/u_ctrl_out/f_ncp/2/f_cmd/14/u_hce" (ROM) removed. Sourceless block "PLL/chipscope/i_icon/icon/u_icon/u_ctrl_out/f_ncp/1/f_cmd/14/u_lce" (ROM) removed. Sourceless block "PLL/chipscope/i_icon/icon/u_icon/u_ctrl_out/f_ncp/1/f_cmd/14/u_hce" (ROM) removed. Sourceless block "PLL/chipscope/i_icon/icon/u_icon/u_ctrl_out/f_ncp/0/f_cmd/14/u_lce" (ROM) removed. Sourceless block "PLL/chipscope/i_icon/icon/u_icon/u_ctrl_out/f_ncp/0/f_cmd/14/u_hce" (ROM) removed. The signal "PLL/chipscope/i_icon/u_icon/icommand_sel_0" is sourceless and has been removed. Sourceless block "PLL/chipscope/i_icon/icon/u_icon/u_ctrl_out/f_ncp/3/f_cmd/15/u_lce" (ROM) removed. Sourceless block "PLL/chipscope/i_icon/icon/u_icon/u_ctrl_out/f_ncp/3/f_cmd/15/u_hce" (ROM) removed. Sourceless block "PLL/chipscope/i_icon/icon/u_icon/u_ctrl_out/f_ncp/2/f_cmd/15/u_lce" (ROM) removed. Sourceless block "PLL/chipscope/i_icon/icon/u_icon/u_ctrl_out/f_ncp/2/f_cmd/15/u_hce" (ROM) removed. Sourceless block "PLL/chipscope/i_icon/icon/u_icon/u_ctrl_out/f_ncp/1/f_cmd/15/u_lce" (ROM) removed. Sourceless block "PLL/chipscope/i_icon/icon/u_icon/u_ctrl_out/f_ncp/1/f_cmd/15/u_hce" (ROM) removed. Sourceless block "PLL/chipscope/i_icon/icon/u_icon/u_ctrl_out/f_ncp/0/f_cmd/15/u_lce" (ROM) removed. Sourceless block "PLL/chipscope/i_icon/icon/u_icon/u_ctrl_out/f_ncp/0/f_cmd/15/u_hce" (ROM) removed. The signal "PLL/chipscope/i_vio_control/async_out<24>" is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/async_out<25>" is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/async_out<26>" is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/async_out<27>" is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/async_out<30>" is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/async_out<28>" is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/async_out<31>" is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/async_out<29>" is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/i_vio/update_8" is sourceless and has been removed. Sourceless block "PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_out/24/async_out_cell/u ser_reg" (FF) removed. The signal "PLL/chipscope/i_vio_control/i_vio/update_7" is sourceless and has been removed. Sourceless block "PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_out/25/async_out_cell/u ser_reg" (FF) removed. The signal "PLL/chipscope/i_vio_control/i_vio/update_6" is sourceless and has been removed. Sourceless block "PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_out/26/async_out_cell/u ser_reg" (FF) removed. The signal "PLL/chipscope/i_vio_control/i_vio/update_5" is sourceless and has been removed. Sourceless block "PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_out/27/async_out_cell/u ser_reg" (FF) removed. The signal "PLL/chipscope/i_vio_control/i_vio/update_4" is sourceless and has been removed. Sourceless block "PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_out/28/async_out_cell/u ser_reg" (FF) removed. The signal "PLL/chipscope/i_vio_control/i_vio/update_3" is sourceless and has been removed. Sourceless block "PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_out/29/async_out_cell/u ser_reg" (FF) removed. The signal "PLL/chipscope/i_vio_control/i_vio/update_2" is sourceless and has been removed. Sourceless block "PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_out/30/async_out_cell/u ser_reg" (FF) removed. The signal "PLL/chipscope/i_vio_control/i_vio/update_1" is sourceless and has been removed. Sourceless block "PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_out/31/async_out_cell/u ser_reg" (FF) removed. The signal "PLL/chipscope/i_vio_control/i_vio/output_shift_7" is sourceless and has been removed. Sourceless block "PLL/chipscope/i_vio_control/vio_control/i_vio/gen_update_out/56/update_cell/gen _no_clk/user_reg" (SFF) removed. Sourceless block "PLL/chipscope/i_vio_control/vio_control/i_vio/gen_update_out/57/update_cell/shi ft_reg" (FF) removed. The signal "PLL/chipscope/i_vio_control/i_vio/output_shift_6" is sourceless and has been removed. Sourceless block "PLL/chipscope/i_vio_control/vio_control/i_vio/gen_update_out/57/update_cell/gen _no_clk/user_reg" (SFF) removed. Sourceless block "PLL/chipscope/i_vio_control/vio_control/i_vio/gen_update_out/58/update_cell/shi ft_reg" (FF) removed. The signal "PLL/chipscope/i_vio_control/i_vio/output_shift_5" is sourceless and has been removed. Sourceless block "PLL/chipscope/i_vio_control/vio_control/i_vio/gen_update_out/58/update_cell/gen _no_clk/user_reg" (SFF) removed. Sourceless block "PLL/chipscope/i_vio_control/vio_control/i_vio/gen_update_out/59/update_cell/shi ft_reg" (FF) removed. The signal "PLL/chipscope/i_vio_control/i_vio/output_shift_4" is sourceless and has been removed. Sourceless block "PLL/chipscope/i_vio_control/vio_control/i_vio/gen_update_out/59/update_cell/gen _no_clk/user_reg" (SFF) removed. Sourceless block "PLL/chipscope/i_vio_control/vio_control/i_vio/gen_update_out/60/update_cell/shi ft_reg" (FF) removed. The signal "PLL/chipscope/i_vio_control/i_vio/output_shift_3" is sourceless and has been removed. Sourceless block "PLL/chipscope/i_vio_control/vio_control/i_vio/gen_update_out/60/update_cell/gen _no_clk/user_reg" (SFF) removed. Sourceless block "PLL/chipscope/i_vio_control/vio_control/i_vio/gen_update_out/61/update_cell/shi ft_reg" (FF) removed. The signal "PLL/chipscope/i_vio_control/i_vio/output_shift_2" is sourceless and has been removed. Sourceless block "PLL/chipscope/i_vio_control/vio_control/i_vio/gen_update_out/61/update_cell/gen _no_clk/user_reg" (SFF) removed. Sourceless block "PLL/chipscope/i_vio_control/vio_control/i_vio/gen_update_out/62/update_cell/shi ft_reg" (FF) removed. The signal "PLL/chipscope/i_vio_control/i_vio/output_shift_1" is sourceless and has been removed. Sourceless block "PLL/chipscope/i_vio_control/vio_control/i_vio/gen_update_out/62/update_cell/gen _no_clk/user_reg" (SFF) removed. Sourceless block "PLL/chipscope/i_vio_control/vio_control/i_vio/gen_update_out/63/update_cell/shi ft_reg" (FF) removed. The signal "PLL/chipscope/i_vio_control/i_vio/output_shift_0" is sourceless and has been removed. Sourceless block "PLL/chipscope/i_vio_control/vio_control/i_vio/gen_update_out/63/update_cell/gen _no_clk/user_reg" (SFF) removed. The signal "PLL/chipscope/i_vio_control/i_vio/reset_f_edge/idout_1" is sourceless and has been removed. Sourceless block "PLL/chipscope/i_vio_control/vio_control/i_vio/reset_f_edge/u_dout1" (FF) removed. The signal "PLL/chipscope/i_vio_control/i_vio/reset_f_edge/idout_0" is sourceless and has been removed. Sourceless block "PLL/chipscope/i_vio_control/vio_control/i_vio/reset_f_edge/i_h2l/u_dout" (SFF) removed. The signal "PLL/chipscope/i_vio_control/i_vio/reset" is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/i_vio/gen_async_in/0/async_in_cell/mux1_out" is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/i_vio/gen_async_in/0/async_in_cell/user_in_n" is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/i_vio/gen_async_in/0/async_in_cell/async_mux_r_out" is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/i_vio/gen_async_in/0/async_in_cell/async_mux_f_out" is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/i_vio/gen_async_in/0/async_in_cell/fd3_out" is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/i_vio/gen_async_in/1/async_in_cell/mux1_out" is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/i_vio/gen_async_in/1/async_in_cell/user_in_n" is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/i_vio/gen_async_in/1/async_in_cell/async_mux_r_out" is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/i_vio/gen_async_in/1/async_in_cell/async_mux_f_out" is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/i_vio/gen_async_in/1/async_in_cell/fd3_out" is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/i_vio/gen_async_in/2/async_in_cell/mux1_out" is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/i_vio/gen_async_in/2/async_in_cell/user_in_n" is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/i_vio/gen_async_in/2/async_in_cell/async_mux_r_out" is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/i_vio/gen_async_in/2/async_in_cell/async_mux_f_out" is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/i_vio/gen_async_in/2/async_in_cell/fd3_out" is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/i_vio/gen_async_in/3/async_in_cell/mux1_out" is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/i_vio/gen_async_in/3/async_in_cell/user_in_n" is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/i_vio/gen_async_in/3/async_in_cell/async_mux_r_out" is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/i_vio/gen_async_in/3/async_in_cell/async_mux_f_out" is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/i_vio/gen_async_in/3/async_in_cell/fd3_out" is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/i_vio/gen_async_in/4/async_in_cell/mux1_out" is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/i_vio/gen_async_in/4/async_in_cell/user_in_n" is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/i_vio/gen_async_in/4/async_in_cell/async_mux_r_out" is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/i_vio/gen_async_in/4/async_in_cell/async_mux_f_out" is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/i_vio/gen_async_in/4/async_in_cell/fd3_out" is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/i_vio/gen_async_in/5/async_in_cell/mux1_out" is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/i_vio/gen_async_in/5/async_in_cell/user_in_n" is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/i_vio/gen_async_in/5/async_in_cell/async_mux_r_out" is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/i_vio/gen_async_in/5/async_in_cell/async_mux_f_out" is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/i_vio/gen_async_in/5/async_in_cell/fd3_out" is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/i_vio/gen_async_in/6/async_in_cell/mux1_out" is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/i_vio/gen_async_in/6/async_in_cell/user_in_n" is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/i_vio/gen_async_in/6/async_in_cell/async_mux_r_out" is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/i_vio/gen_async_in/6/async_in_cell/async_mux_f_out" is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/i_vio/gen_async_in/6/async_in_cell/fd3_out" is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/i_vio/gen_async_in/7/async_in_cell/mux1_out" is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/i_vio/gen_async_in/7/async_in_cell/user_in_n" is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/i_vio/gen_async_in/7/async_in_cell/async_mux_r_out" is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/i_vio/gen_async_in/7/async_in_cell/async_mux_f_out" is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/i_vio/gen_async_in/7/async_in_cell/fd3_out" is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/i_vio/gen_async_in/8/async_in_cell/mux1_out" is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/i_vio/gen_async_in/8/async_in_cell/user_in_n" is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/i_vio/gen_async_in/8/async_in_cell/async_mux_r_out" is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/i_vio/gen_async_in/8/async_in_cell/async_mux_f_out" is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/i_vio/gen_async_in/8/async_in_cell/fd3_out" is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/i_vio/gen_async_in/9/async_in_cell/mux1_out" is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/i_vio/gen_async_in/9/async_in_cell/user_in_n" is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/i_vio/gen_async_in/9/async_in_cell/async_mux_r_out" is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/i_vio/gen_async_in/9/async_in_cell/async_mux_f_out" is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/i_vio/gen_async_in/9/async_in_cell/fd3_out" is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/i_vio/gen_async_in/10/async_in_cell/mux1_out" is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/i_vio/gen_async_in/10/async_in_cell/user_in_n" is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/i_vio/gen_async_in/10/async_in_cell/async_mux_r_out " is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/i_vio/gen_async_in/10/async_in_cell/async_mux_f_out " is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/i_vio/gen_async_in/10/async_in_cell/fd3_out" is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/i_vio/gen_async_in/11/async_in_cell/mux1_out" is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/i_vio/gen_async_in/11/async_in_cell/user_in_n" is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/i_vio/gen_async_in/11/async_in_cell/async_mux_r_out " is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/i_vio/gen_async_in/11/async_in_cell/async_mux_f_out " is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/i_vio/gen_async_in/11/async_in_cell/fd3_out" is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/i_vio/gen_async_in/12/async_in_cell/mux1_out" is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/i_vio/gen_async_in/12/async_in_cell/user_in_n" is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/i_vio/gen_async_in/12/async_in_cell/async_mux_r_out " is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/i_vio/gen_async_in/12/async_in_cell/async_mux_f_out " is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/i_vio/gen_async_in/12/async_in_cell/fd3_out" is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/i_vio/gen_async_in/13/async_in_cell/mux1_out" is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/i_vio/gen_async_in/13/async_in_cell/user_in_n" is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/i_vio/gen_async_in/13/async_in_cell/async_mux_r_out " is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/i_vio/gen_async_in/13/async_in_cell/async_mux_f_out " is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/i_vio/gen_async_in/13/async_in_cell/fd3_out" is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/i_vio/gen_async_in/14/async_in_cell/mux1_out" is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/i_vio/gen_async_in/14/async_in_cell/user_in_n" is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/i_vio/gen_async_in/14/async_in_cell/async_mux_r_out " is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/i_vio/gen_async_in/14/async_in_cell/async_mux_f_out " is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/i_vio/gen_async_in/14/async_in_cell/fd3_out" is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/i_vio/gen_async_in/15/async_in_cell/mux1_out" is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/i_vio/gen_async_in/15/async_in_cell/user_in_n" is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/i_vio/gen_async_in/15/async_in_cell/async_mux_r_out " is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/i_vio/gen_async_in/15/async_in_cell/async_mux_f_out " is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/i_vio/gen_async_in/15/async_in_cell/fd3_out" is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/i_vio/gen_async_in/16/async_in_cell/mux1_out" is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/i_vio/gen_async_in/16/async_in_cell/user_in_n" is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/i_vio/gen_async_in/16/async_in_cell/async_mux_r_out " is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/i_vio/gen_async_in/16/async_in_cell/async_mux_f_out " is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/i_vio/gen_async_in/16/async_in_cell/fd3_out" is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/i_vio/gen_async_in/17/async_in_cell/mux1_out" is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/i_vio/gen_async_in/17/async_in_cell/user_in_n" is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/i_vio/gen_async_in/17/async_in_cell/async_mux_r_out " is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/i_vio/gen_async_in/17/async_in_cell/async_mux_f_out " is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/i_vio/gen_async_in/17/async_in_cell/fd3_out" is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/i_vio/gen_async_in/18/async_in_cell/mux1_out" is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/i_vio/gen_async_in/18/async_in_cell/user_in_n" is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/i_vio/gen_async_in/18/async_in_cell/async_mux_r_out " is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/i_vio/gen_async_in/18/async_in_cell/async_mux_f_out " is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/i_vio/gen_async_in/18/async_in_cell/fd3_out" is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/i_vio/gen_async_in/19/async_in_cell/mux1_out" is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/i_vio/gen_async_in/19/async_in_cell/user_in_n" is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/i_vio/gen_async_in/19/async_in_cell/async_mux_r_out " is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/i_vio/gen_async_in/19/async_in_cell/async_mux_f_out " is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/i_vio/gen_async_in/19/async_in_cell/fd3_out" is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/i_vio/gen_async_in/20/async_in_cell/mux1_out" is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/i_vio/gen_async_in/20/async_in_cell/user_in_n" is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/i_vio/gen_async_in/20/async_in_cell/async_mux_r_out " is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/i_vio/gen_async_in/20/async_in_cell/async_mux_f_out " is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/i_vio/gen_async_in/20/async_in_cell/fd3_out" is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/i_vio/gen_async_in/21/async_in_cell/mux1_out" is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/i_vio/gen_async_in/21/async_in_cell/user_in_n" is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/i_vio/gen_async_in/21/async_in_cell/async_mux_r_out " is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/i_vio/gen_async_in/21/async_in_cell/async_mux_f_out " is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/i_vio/gen_async_in/21/async_in_cell/fd3_out" is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/i_vio/gen_async_in/22/async_in_cell/mux1_out" is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/i_vio/gen_async_in/22/async_in_cell/user_in_n" is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/i_vio/gen_async_in/22/async_in_cell/async_mux_r_out " is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/i_vio/gen_async_in/22/async_in_cell/async_mux_f_out " is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/i_vio/gen_async_in/22/async_in_cell/fd3_out" is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/i_vio/gen_async_in/23/async_in_cell/mux1_out" is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/i_vio/gen_async_in/23/async_in_cell/user_in_n" is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/i_vio/gen_async_in/23/async_in_cell/async_mux_r_out " is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/i_vio/gen_async_in/23/async_in_cell/async_mux_f_out " is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/i_vio/gen_async_in/23/async_in_cell/fd3_out" is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/i_vio/gen_async_in/24/async_in_cell/mux1_out" is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/i_vio/gen_async_in/24/async_in_cell/user_in_n" is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/i_vio/gen_async_in/24/async_in_cell/async_mux_r_out " is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/i_vio/gen_async_in/24/async_in_cell/async_mux_f_out " is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/i_vio/gen_async_in/24/async_in_cell/fd3_out" is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/i_vio/gen_async_in/25/async_in_cell/mux1_out" is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/i_vio/gen_async_in/25/async_in_cell/user_in_n" is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/i_vio/gen_async_in/25/async_in_cell/async_mux_r_out " is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/i_vio/gen_async_in/25/async_in_cell/async_mux_f_out " is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/i_vio/gen_async_in/25/async_in_cell/fd3_out" is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/i_vio/gen_async_in/26/async_in_cell/mux1_out" is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/i_vio/gen_async_in/26/async_in_cell/user_in_n" is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/i_vio/gen_async_in/26/async_in_cell/async_mux_r_out " is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/i_vio/gen_async_in/26/async_in_cell/async_mux_f_out " is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/i_vio/gen_async_in/26/async_in_cell/fd3_out" is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/i_vio/gen_async_in/27/async_in_cell/mux1_out" is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/i_vio/gen_async_in/27/async_in_cell/user_in_n" is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/i_vio/gen_async_in/27/async_in_cell/async_mux_r_out " is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/i_vio/gen_async_in/27/async_in_cell/async_mux_f_out " is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/i_vio/gen_async_in/27/async_in_cell/fd3_out" is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/i_vio/gen_async_in/28/async_in_cell/mux1_out" is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/i_vio/gen_async_in/28/async_in_cell/user_in_n" is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/i_vio/gen_async_in/28/async_in_cell/async_mux_r_out " is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/i_vio/gen_async_in/28/async_in_cell/async_mux_f_out " is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/i_vio/gen_async_in/28/async_in_cell/fd3_out" is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/i_vio/gen_async_in/29/async_in_cell/mux1_out" is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/i_vio/gen_async_in/29/async_in_cell/user_in_n" is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/i_vio/gen_async_in/29/async_in_cell/async_mux_r_out " is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/i_vio/gen_async_in/29/async_in_cell/async_mux_f_out " is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/i_vio/gen_async_in/29/async_in_cell/fd3_out" is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/i_vio/gen_async_in/30/async_in_cell/mux1_out" is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/i_vio/gen_async_in/30/async_in_cell/user_in_n" is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/i_vio/gen_async_in/30/async_in_cell/async_mux_r_out " is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/i_vio/gen_async_in/30/async_in_cell/async_mux_f_out " is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/i_vio/gen_async_in/30/async_in_cell/fd3_out" is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/i_vio/gen_async_in/31/async_in_cell/mux1_out" is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/i_vio/gen_async_in/31/async_in_cell/user_in_n" is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/i_vio/gen_async_in/31/async_in_cell/async_mux_r_out " is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/i_vio/gen_async_in/31/async_in_cell/async_mux_f_out " is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/i_vio/gen_async_in/31/async_in_cell/fd3_out" is sourceless and has been removed. The signal "PLL/chipscope/i_vio_control/i_vio/input_shift_0" is sourceless and has been removed. The signal "PLL/chipscope/i_vio/async_out<30>" is sourceless and has been removed. The signal "PLL/chipscope/i_vio/async_out<28>" is sourceless and has been removed. The signal "PLL/chipscope/i_vio/async_out<31>" is sourceless and has been removed. The signal "PLL/chipscope/i_vio/async_out<29>" is sourceless and has been removed. The signal "PLL/chipscope/i_vio/i_vio/update_4" is sourceless and has been removed. Sourceless block "PLL/chipscope/i_vio/vio/i_vio/gen_async_out/28/async_out_cell/user_reg" (FF) removed. The signal "PLL/chipscope/i_vio/i_vio/update_3" is sourceless and has been removed. Sourceless block "PLL/chipscope/i_vio/vio/i_vio/gen_async_out/29/async_out_cell/user_reg" (FF) removed. The signal "PLL/chipscope/i_vio/i_vio/update_2" is sourceless and has been removed. Sourceless block "PLL/chipscope/i_vio/vio/i_vio/gen_async_out/30/async_out_cell/user_reg" (FF) removed. The signal "PLL/chipscope/i_vio/i_vio/update_1" is sourceless and has been removed. Sourceless block "PLL/chipscope/i_vio/vio/i_vio/gen_async_out/31/async_out_cell/user_reg" (FF) removed. The signal "PLL/chipscope/i_vio/i_vio/output_shift_3" is sourceless and has been removed. Sourceless block "PLL/chipscope/i_vio/vio/i_vio/gen_update_out/60/update_cell/gen_no_clk/user_reg " (SFF) removed. Sourceless block "PLL/chipscope/i_vio/vio/i_vio/gen_update_out/61/update_cell/shift_reg" (FF) removed. The signal "PLL/chipscope/i_vio/i_vio/output_shift_2" is sourceless and has been removed. Sourceless block "PLL/chipscope/i_vio/vio/i_vio/gen_update_out/61/update_cell/gen_no_clk/user_reg " (SFF) removed. Sourceless block "PLL/chipscope/i_vio/vio/i_vio/gen_update_out/62/update_cell/shift_reg" (FF) removed. The signal "PLL/chipscope/i_vio/i_vio/output_shift_1" is sourceless and has been removed. Sourceless block "PLL/chipscope/i_vio/vio/i_vio/gen_update_out/62/update_cell/gen_no_clk/user_reg " (SFF) removed. Sourceless block "PLL/chipscope/i_vio/vio/i_vio/gen_update_out/63/update_cell/shift_reg" (FF) removed. The signal "PLL/chipscope/i_vio/i_vio/output_shift_0" is sourceless and has been removed. Sourceless block "PLL/chipscope/i_vio/vio/i_vio/gen_update_out/63/update_cell/gen_no_clk/user_reg " (SFF) removed. Unused block "PLL/chipscope/i_icon/icon/u_icon/u_cmd/u_command_sel/i4/fi/11/u_lut" (ROM) removed. Unused block "PLL/chipscope/i_icon/icon/u_icon/u_cmd/u_command_sel/i4/fi/12/u_lut" (ROM) removed. Unused block "PLL/chipscope/i_icon/icon/u_icon/u_cmd/u_command_sel/i4/fi/13/u_lut" (ROM) removed. Unused block "PLL/chipscope/i_icon/icon/u_icon/u_cmd/u_command_sel/i4/fi/14/u_lut" (ROM) removed. Unused block "PLL/chipscope/i_icon/icon/u_icon/u_cmd/u_command_sel/i4/fi/15/u_lut" (ROM) removed. Unused block "PLL/chipscope/i_icon/icon/u_icon/u_cmd/u_command_sel/i4/fi/6/u_lut" (ROM) removed. Unused block "PLL/chipscope/i_icon/icon/u_icon/u_cmd/u_command_sel/i4/fi/7/u_lut" (ROM) removed. Unused block "PLL/chipscope/i_icon/icon/u_icon/u_ctrl_out/f_ncp/0/f_cmd/0/u_hce" (ROM) removed. Unused block "PLL/chipscope/i_icon/icon/u_icon/u_ctrl_out/f_ncp/0/f_cmd/1/u_hce" (ROM) removed. Unused block "PLL/chipscope/i_icon/icon/u_icon/u_ctrl_out/f_ncp/0/f_cmd/10/u_hce" (ROM) removed. Unused block "PLL/chipscope/i_icon/icon/u_icon/u_ctrl_out/f_ncp/0/f_cmd/10/u_lce" (ROM) removed. Unused block "PLL/chipscope/i_icon/icon/u_icon/u_ctrl_out/f_ncp/0/f_cmd/2/u_hce" (ROM) removed. Unused block "PLL/chipscope/i_icon/icon/u_icon/u_ctrl_out/f_ncp/0/f_cmd/3/u_hce" (ROM) removed. Unused block "PLL/chipscope/i_icon/icon/u_icon/u_ctrl_out/f_ncp/0/f_cmd/4/u_hce" (ROM) removed. Unused block "PLL/chipscope/i_icon/icon/u_icon/u_ctrl_out/f_ncp/0/f_cmd/4/u_lce" (ROM) removed. Unused block "PLL/chipscope/i_icon/icon/u_icon/u_ctrl_out/f_ncp/0/f_cmd/5/u_hce" (ROM) removed. Unused block "PLL/chipscope/i_icon/icon/u_icon/u_ctrl_out/f_ncp/0/f_cmd/5/u_lce" (ROM) removed. Unused block "PLL/chipscope/i_icon/icon/u_icon/u_ctrl_out/f_ncp/0/f_cmd/8/u_hce" (ROM) removed. Unused block "PLL/chipscope/i_icon/icon/u_icon/u_ctrl_out/f_ncp/0/f_cmd/8/u_lce" (ROM) removed. Unused block "PLL/chipscope/i_icon/icon/u_icon/u_ctrl_out/f_ncp/0/f_cmd/9/u_hce" (ROM) removed. Unused block "PLL/chipscope/i_icon/icon/u_icon/u_ctrl_out/f_ncp/0/f_cmd/9/u_lce" (ROM) removed. Unused block "PLL/chipscope/i_icon/icon/u_icon/u_ctrl_out/f_ncp/1/f_cmd/0/u_hce" (ROM) removed. Unused block "PLL/chipscope/i_icon/icon/u_icon/u_ctrl_out/f_ncp/1/f_cmd/1/u_hce" (ROM) removed. Unused block "PLL/chipscope/i_icon/icon/u_icon/u_ctrl_out/f_ncp/1/f_cmd/10/u_hce" (ROM) removed. Unused block "PLL/chipscope/i_icon/icon/u_icon/u_ctrl_out/f_ncp/1/f_cmd/10/u_lce" (ROM) removed. Unused block "PLL/chipscope/i_icon/icon/u_icon/u_ctrl_out/f_ncp/1/f_cmd/2/u_hce" (ROM) removed. Unused block "PLL/chipscope/i_icon/icon/u_icon/u_ctrl_out/f_ncp/1/f_cmd/3/u_hce" (ROM) removed. Unused block "PLL/chipscope/i_icon/icon/u_icon/u_ctrl_out/f_ncp/1/f_cmd/4/u_hce" (ROM) removed. Unused block "PLL/chipscope/i_icon/icon/u_icon/u_ctrl_out/f_ncp/1/f_cmd/4/u_lce" (ROM) removed. Unused block "PLL/chipscope/i_icon/icon/u_icon/u_ctrl_out/f_ncp/1/f_cmd/5/u_hce" (ROM) removed. Unused block "PLL/chipscope/i_icon/icon/u_icon/u_ctrl_out/f_ncp/1/f_cmd/5/u_lce" (ROM) removed. Unused block "PLL/chipscope/i_icon/icon/u_icon/u_ctrl_out/f_ncp/1/f_cmd/8/u_hce" (ROM) removed. Unused block "PLL/chipscope/i_icon/icon/u_icon/u_ctrl_out/f_ncp/1/f_cmd/8/u_lce" (ROM) removed. Unused block "PLL/chipscope/i_icon/icon/u_icon/u_ctrl_out/f_ncp/1/f_cmd/9/u_hce" (ROM) removed. Unused block "PLL/chipscope/i_icon/icon/u_icon/u_ctrl_out/f_ncp/1/f_cmd/9/u_lce" (ROM) removed. Unused block "PLL/chipscope/i_icon/icon/u_icon/u_ctrl_out/f_ncp/2/f_cmd/1/u_hce" (ROM) removed. Unused block "PLL/chipscope/i_icon/icon/u_icon/u_ctrl_out/f_ncp/2/f_cmd/10/u_hce" (ROM) removed. Unused block "PLL/chipscope/i_icon/icon/u_icon/u_ctrl_out/f_ncp/2/f_cmd/2/u_hce" (ROM) removed. Unused block "PLL/chipscope/i_icon/icon/u_icon/u_ctrl_out/f_ncp/2/f_cmd/3/u_hce" (ROM) removed. Unused block "PLL/chipscope/i_icon/icon/u_icon/u_ctrl_out/f_ncp/2/f_cmd/3/u_lce" (ROM) removed. Unused block "PLL/chipscope/i_icon/icon/u_icon/u_ctrl_out/f_ncp/2/f_cmd/4/u_hce" (ROM) removed. Unused block "PLL/chipscope/i_icon/icon/u_icon/u_ctrl_out/f_ncp/2/f_cmd/5/u_hce" (ROM) removed. Unused block "PLL/chipscope/i_icon/icon/u_icon/u_ctrl_out/f_ncp/2/f_cmd/8/u_hce" (ROM) removed. Unused block "PLL/chipscope/i_icon/icon/u_icon/u_ctrl_out/f_ncp/2/f_cmd/9/u_hce" (ROM) removed. Unused block "PLL/chipscope/i_icon/icon/u_icon/u_ctrl_out/f_ncp/3/f_cmd/1/u_hce" (ROM) removed. Unused block "PLL/chipscope/i_icon/icon/u_icon/u_ctrl_out/f_ncp/3/f_cmd/10/u_hce" (ROM) removed. Unused block "PLL/chipscope/i_icon/icon/u_icon/u_ctrl_out/f_ncp/3/f_cmd/2/u_hce" (ROM) removed. Unused block "PLL/chipscope/i_icon/icon/u_icon/u_ctrl_out/f_ncp/3/f_cmd/3/u_hce" (ROM) removed. Unused block "PLL/chipscope/i_icon/icon/u_icon/u_ctrl_out/f_ncp/3/f_cmd/3/u_lce" (ROM) removed. Unused block "PLL/chipscope/i_icon/icon/u_icon/u_ctrl_out/f_ncp/3/f_cmd/4/u_hce" (ROM) removed. Unused block "PLL/chipscope/i_icon/icon/u_icon/u_ctrl_out/f_ncp/3/f_cmd/5/u_hce" (ROM) removed. Unused block "PLL/chipscope/i_icon/icon/u_icon/u_ctrl_out/f_ncp/3/f_cmd/8/u_hce" (ROM) removed. Unused block "PLL/chipscope/i_icon/icon/u_icon/u_ctrl_out/f_ncp/3/f_cmd/9/u_hce" (ROM) removed. Unused block "PLL/chipscope/i_vio/vio/i_vio/gen_update_out/60/update_cell/shift_reg" (FF) removed. Unused block "PLL/chipscope/i_vio_control/vio_control/i_vio/gen_update_out/56/update_cell/shi ft_reg" (FF) removed. Unused block "PLL/chipscope/i_vio_control/vio_control/i_vio/reset_f_edge/u_dout0" (FF) removed. Unused block "PLL/ph_table_1/B10" () removed. Unused block "PLL/ph_table_1/B6" () removed. Unused block "PLL/ph_table_1/GND" (ZERO) removed. Unused block "PLL/ph_table_1/VCC" (ONE) removed. Optimized Block(s): TYPE BLOCK LUT1 DIR_1_OBUF_rt LUT1 DIR_1_OBUF_rt1 LUT3 PLL/C_TABLE/BU16 LUT3 PLL/C_TABLE/BU191 LUT3 PLL/C_TABLE/BU366 GND PLL/C_TABLE/GND VCC PLL/C_TABLE/VCC GND PLL/HC_TABLE/GND VCC PLL/HC_TABLE/VCC GND PLL/INJ_TABLE/GND VCC PLL/INJ_TABLE/VCC GND PLL/ST_TABLE/GND VCC PLL/ST_TABLE/VCC GND PLL/chipscope/i_icon/GND VCC PLL/chipscope/i_icon/VCC LUT4 PLL/chipscope/i_icon/icon/u_icon/u_stat/f_stat/3/u_stat LUT3 PLL/chipscope/i_icon/icon/u_icon/u_tdo_mux/i4/fj/4/u_lut3 LUT3 PLL/chipscope/i_icon/icon/u_icon/u_tdo_mux/i4/fj/5/u_lut3 LUT3 PLL/chipscope/i_icon/icon/u_icon/u_tdo_mux/i4/fj/6/u_lut3 GND PLL/chipscope/i_ila_2CH/GND VCC PLL/chipscope/i_ila_2CH/VCC LUT4 PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_stat/f_sstat/7/i_stat/u_stat LUT4 PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_stat/f_sstat/9/i_stat/u_stat LUT3 PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_stat/u_smux/i5/fj/10/u_lut3 LUT3 PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_stat/u_smux/i5/fj/11/u_lut3 LUT3 PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_stat/u_smux/i5/fj/12/u_lut3 LUT3 PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_stat/u_smux/i5/fj/13/u_lut3 LUT3 PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_stat/u_smux/i5/fj/14/u_lut3 LUT3 PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_stat/u_smux/i5/fj/15/u_lut3 LUT3 PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_stat/u_smux/i5/fj/7/u_lut3 GND PLL/chipscope/i_ila_6CH/GND VCC PLL/chipscope/i_ila_6CH/VCC LUT4 PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_stat/f_sstat/7/i_stat/u_stat LUT4 PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_stat/f_sstat/9/i_stat/u_stat LUT3 PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_stat/u_smux/i5/fj/10/u_lut3 LUT3 PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_stat/u_smux/i5/fj/11/u_lut3 LUT3 PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_stat/u_smux/i5/fj/12/u_lut3 LUT3 PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_stat/u_smux/i5/fj/13/u_lut3 LUT3 PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_stat/u_smux/i5/fj/14/u_lut3 LUT3 PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_stat/u_smux/i5/fj/15/u_lut3 LUT3 PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_stat/u_smux/i5/fj/7/u_lut3 GND PLL/chipscope/i_vio/GND VCC PLL/chipscope/i_vio/VCC LUT4 PLL/chipscope/i_vio/vio/i_vio/u_status/f_stat/3/u_stat LUT4 PLL/chipscope/i_vio/vio/i_vio/u_status/f_stat/5/u_stat LUT4 PLL/chipscope/i_vio/vio/i_vio/u_status/f_stat/6/u_stat LUT4 PLL/chipscope/i_vio/vio/i_vio/u_status/f_stat/7/u_stat LUT3 PLL/chipscope/i_vio/vio/i_vio/u_status/u_smux/i3/fj/3/u_lut3 GND PLL/chipscope/i_vio_control/GND VCC PLL/chipscope/i_vio_control/VCC LUT3 PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/0/async_in_cell/asy nc_f_mux LUT3 PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/0/async_in_cell/asy nc_r_mux FDE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/0/async_in_cell/s_a sync_f_reg optimized to 0 FDE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/0/async_in_cell/s_a sync_r_reg optimized to 0 FDE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/0/async_in_cell/s_a sync_reg optimized to 0 FDE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/0/async_in_cell/s_u ser_reg optimized to 0 FDCE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/0/async_in_cell/u_f alling optimized to 0 FDCE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/0/async_in_cell/u_r ising optimized to 0 INV PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/0/async_in_cell/u_s tatcmd_n LUT3 PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/0/async_in_cell/use r_mux LUT3 PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/1/async_in_cell/asy nc_f_mux LUT3 PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/1/async_in_cell/asy nc_r_mux FDE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/1/async_in_cell/s_a sync_f_reg optimized to 0 FDE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/1/async_in_cell/s_a sync_r_reg optimized to 0 FDE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/1/async_in_cell/s_a sync_reg optimized to 0 FDE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/1/async_in_cell/s_u ser_reg optimized to 0 FDCE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/1/async_in_cell/u_f alling optimized to 0 FDCE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/1/async_in_cell/u_r ising optimized to 0 INV PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/1/async_in_cell/u_s tatcmd_n LUT3 PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/1/async_in_cell/use r_mux LUT3 PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/10/async_in_cell/as ync_f_mux LUT3 PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/10/async_in_cell/as ync_r_mux FDE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/10/async_in_cell/s_ async_f_reg optimized to 0 FDE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/10/async_in_cell/s_ async_r_reg optimized to 0 FDE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/10/async_in_cell/s_ async_reg optimized to 0 FDE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/10/async_in_cell/s_ user_reg optimized to 0 FDCE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/10/async_in_cell/u_ falling optimized to 0 FDCE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/10/async_in_cell/u_ rising optimized to 0 INV PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/10/async_in_cell/u_ statcmd_n LUT3 PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/10/async_in_cell/us er_mux LUT3 PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/11/async_in_cell/as ync_f_mux LUT3 PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/11/async_in_cell/as ync_r_mux FDE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/11/async_in_cell/s_ async_f_reg optimized to 0 FDE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/11/async_in_cell/s_ async_r_reg optimized to 0 FDE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/11/async_in_cell/s_ async_reg optimized to 0 FDE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/11/async_in_cell/s_ user_reg optimized to 0 FDCE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/11/async_in_cell/u_ falling optimized to 0 FDCE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/11/async_in_cell/u_ rising optimized to 0 INV PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/11/async_in_cell/u_ statcmd_n LUT3 PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/11/async_in_cell/us er_mux LUT3 PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/12/async_in_cell/as ync_f_mux LUT3 PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/12/async_in_cell/as ync_r_mux FDE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/12/async_in_cell/s_ async_f_reg optimized to 0 FDE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/12/async_in_cell/s_ async_r_reg optimized to 0 FDE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/12/async_in_cell/s_ async_reg optimized to 0 FDE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/12/async_in_cell/s_ user_reg optimized to 0 FDCE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/12/async_in_cell/u_ falling optimized to 0 FDCE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/12/async_in_cell/u_ rising optimized to 0 INV PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/12/async_in_cell/u_ statcmd_n LUT3 PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/12/async_in_cell/us er_mux LUT3 PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/13/async_in_cell/as ync_f_mux LUT3 PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/13/async_in_cell/as ync_r_mux FDE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/13/async_in_cell/s_ async_f_reg optimized to 0 FDE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/13/async_in_cell/s_ async_r_reg optimized to 0 FDE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/13/async_in_cell/s_ async_reg optimized to 0 FDE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/13/async_in_cell/s_ user_reg optimized to 0 FDCE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/13/async_in_cell/u_ falling optimized to 0 FDCE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/13/async_in_cell/u_ rising optimized to 0 INV PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/13/async_in_cell/u_ statcmd_n LUT3 PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/13/async_in_cell/us er_mux LUT3 PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/14/async_in_cell/as ync_f_mux LUT3 PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/14/async_in_cell/as ync_r_mux FDE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/14/async_in_cell/s_ async_f_reg optimized to 0 FDE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/14/async_in_cell/s_ async_r_reg optimized to 0 FDE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/14/async_in_cell/s_ async_reg optimized to 0 FDE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/14/async_in_cell/s_ user_reg optimized to 0 FDCE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/14/async_in_cell/u_ falling optimized to 0 FDCE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/14/async_in_cell/u_ rising optimized to 0 INV PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/14/async_in_cell/u_ statcmd_n LUT3 PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/14/async_in_cell/us er_mux LUT3 PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/15/async_in_cell/as ync_f_mux LUT3 PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/15/async_in_cell/as ync_r_mux FDE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/15/async_in_cell/s_ async_f_reg optimized to 0 FDE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/15/async_in_cell/s_ async_r_reg optimized to 0 FDE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/15/async_in_cell/s_ async_reg optimized to 0 FDE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/15/async_in_cell/s_ user_reg optimized to 0 FDCE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/15/async_in_cell/u_ falling optimized to 0 FDCE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/15/async_in_cell/u_ rising optimized to 0 INV PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/15/async_in_cell/u_ statcmd_n LUT3 PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/15/async_in_cell/us er_mux LUT3 PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/16/async_in_cell/as ync_f_mux LUT3 PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/16/async_in_cell/as ync_r_mux FDE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/16/async_in_cell/s_ async_f_reg optimized to 0 FDE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/16/async_in_cell/s_ async_r_reg optimized to 0 FDE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/16/async_in_cell/s_ async_reg optimized to 0 FDE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/16/async_in_cell/s_ user_reg optimized to 0 FDCE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/16/async_in_cell/u_ falling optimized to 0 FDCE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/16/async_in_cell/u_ rising optimized to 0 INV PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/16/async_in_cell/u_ statcmd_n LUT3 PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/16/async_in_cell/us er_mux LUT3 PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/17/async_in_cell/as ync_f_mux LUT3 PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/17/async_in_cell/as ync_r_mux FDE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/17/async_in_cell/s_ async_f_reg optimized to 0 FDE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/17/async_in_cell/s_ async_r_reg optimized to 0 FDE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/17/async_in_cell/s_ async_reg optimized to 0 FDE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/17/async_in_cell/s_ user_reg optimized to 0 FDCE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/17/async_in_cell/u_ falling optimized to 0 FDCE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/17/async_in_cell/u_ rising optimized to 0 INV PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/17/async_in_cell/u_ statcmd_n LUT3 PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/17/async_in_cell/us er_mux LUT3 PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/18/async_in_cell/as ync_f_mux LUT3 PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/18/async_in_cell/as ync_r_mux FDE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/18/async_in_cell/s_ async_f_reg optimized to 0 FDE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/18/async_in_cell/s_ async_r_reg optimized to 0 FDE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/18/async_in_cell/s_ async_reg optimized to 0 FDE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/18/async_in_cell/s_ user_reg optimized to 0 FDCE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/18/async_in_cell/u_ falling optimized to 0 FDCE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/18/async_in_cell/u_ rising optimized to 0 INV PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/18/async_in_cell/u_ statcmd_n LUT3 PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/18/async_in_cell/us er_mux LUT3 PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/19/async_in_cell/as ync_f_mux LUT3 PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/19/async_in_cell/as ync_r_mux FDE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/19/async_in_cell/s_ async_f_reg optimized to 0 FDE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/19/async_in_cell/s_ async_r_reg optimized to 0 FDE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/19/async_in_cell/s_ async_reg optimized to 0 FDE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/19/async_in_cell/s_ user_reg optimized to 0 FDCE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/19/async_in_cell/u_ falling optimized to 0 FDCE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/19/async_in_cell/u_ rising optimized to 0 INV PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/19/async_in_cell/u_ statcmd_n LUT3 PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/19/async_in_cell/us er_mux LUT3 PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/2/async_in_cell/asy nc_f_mux LUT3 PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/2/async_in_cell/asy nc_r_mux FDE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/2/async_in_cell/s_a sync_f_reg optimized to 0 FDE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/2/async_in_cell/s_a sync_r_reg optimized to 0 FDE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/2/async_in_cell/s_a sync_reg optimized to 0 FDE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/2/async_in_cell/s_u ser_reg optimized to 0 FDCE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/2/async_in_cell/u_f alling optimized to 0 FDCE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/2/async_in_cell/u_r ising optimized to 0 INV PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/2/async_in_cell/u_s tatcmd_n LUT3 PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/2/async_in_cell/use r_mux LUT3 PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/20/async_in_cell/as ync_f_mux LUT3 PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/20/async_in_cell/as ync_r_mux FDE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/20/async_in_cell/s_ async_f_reg optimized to 0 FDE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/20/async_in_cell/s_ async_r_reg optimized to 0 FDE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/20/async_in_cell/s_ async_reg optimized to 0 FDE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/20/async_in_cell/s_ user_reg optimized to 0 FDCE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/20/async_in_cell/u_ falling optimized to 0 FDCE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/20/async_in_cell/u_ rising optimized to 0 INV PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/20/async_in_cell/u_ statcmd_n LUT3 PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/20/async_in_cell/us er_mux LUT3 PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/21/async_in_cell/as ync_f_mux LUT3 PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/21/async_in_cell/as ync_r_mux FDE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/21/async_in_cell/s_ async_f_reg optimized to 0 FDE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/21/async_in_cell/s_ async_r_reg optimized to 0 FDE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/21/async_in_cell/s_ async_reg optimized to 0 FDE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/21/async_in_cell/s_ user_reg optimized to 0 FDCE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/21/async_in_cell/u_ falling optimized to 0 FDCE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/21/async_in_cell/u_ rising optimized to 0 INV PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/21/async_in_cell/u_ statcmd_n LUT3 PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/21/async_in_cell/us er_mux LUT3 PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/22/async_in_cell/as ync_f_mux LUT3 PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/22/async_in_cell/as ync_r_mux FDE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/22/async_in_cell/s_ async_f_reg optimized to 0 FDE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/22/async_in_cell/s_ async_r_reg optimized to 0 FDE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/22/async_in_cell/s_ async_reg optimized to 0 FDE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/22/async_in_cell/s_ user_reg optimized to 0 FDCE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/22/async_in_cell/u_ falling optimized to 0 FDCE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/22/async_in_cell/u_ rising optimized to 0 INV PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/22/async_in_cell/u_ statcmd_n LUT3 PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/22/async_in_cell/us er_mux LUT3 PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/23/async_in_cell/as ync_f_mux LUT3 PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/23/async_in_cell/as ync_r_mux FDE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/23/async_in_cell/s_ async_f_reg optimized to 0 FDE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/23/async_in_cell/s_ async_r_reg optimized to 0 FDE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/23/async_in_cell/s_ async_reg optimized to 0 FDE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/23/async_in_cell/s_ user_reg optimized to 0 FDCE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/23/async_in_cell/u_ falling optimized to 0 FDCE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/23/async_in_cell/u_ rising optimized to 0 INV PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/23/async_in_cell/u_ statcmd_n LUT3 PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/23/async_in_cell/us er_mux LUT3 PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/24/async_in_cell/as ync_f_mux LUT3 PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/24/async_in_cell/as ync_r_mux FDE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/24/async_in_cell/s_ async_f_reg optimized to 0 FDE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/24/async_in_cell/s_ async_r_reg optimized to 0 FDE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/24/async_in_cell/s_ async_reg optimized to 0 FDE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/24/async_in_cell/s_ user_reg optimized to 0 FDCE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/24/async_in_cell/u_ falling optimized to 0 FDCE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/24/async_in_cell/u_ rising optimized to 0 INV PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/24/async_in_cell/u_ statcmd_n LUT3 PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/24/async_in_cell/us er_mux LUT3 PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/25/async_in_cell/as ync_f_mux LUT3 PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/25/async_in_cell/as ync_r_mux FDE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/25/async_in_cell/s_ async_f_reg optimized to 0 FDE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/25/async_in_cell/s_ async_r_reg optimized to 0 FDE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/25/async_in_cell/s_ async_reg optimized to 0 FDE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/25/async_in_cell/s_ user_reg optimized to 0 FDCE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/25/async_in_cell/u_ falling optimized to 0 FDCE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/25/async_in_cell/u_ rising optimized to 0 INV PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/25/async_in_cell/u_ statcmd_n LUT3 PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/25/async_in_cell/us er_mux LUT3 PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/26/async_in_cell/as ync_f_mux LUT3 PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/26/async_in_cell/as ync_r_mux FDE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/26/async_in_cell/s_ async_f_reg optimized to 0 FDE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/26/async_in_cell/s_ async_r_reg optimized to 0 FDE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/26/async_in_cell/s_ async_reg optimized to 0 FDE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/26/async_in_cell/s_ user_reg optimized to 0 FDCE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/26/async_in_cell/u_ falling optimized to 0 FDCE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/26/async_in_cell/u_ rising optimized to 0 INV PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/26/async_in_cell/u_ statcmd_n LUT3 PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/26/async_in_cell/us er_mux LUT3 PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/27/async_in_cell/as ync_f_mux LUT3 PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/27/async_in_cell/as ync_r_mux FDE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/27/async_in_cell/s_ async_f_reg optimized to 0 FDE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/27/async_in_cell/s_ async_r_reg optimized to 0 FDE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/27/async_in_cell/s_ async_reg optimized to 0 FDE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/27/async_in_cell/s_ user_reg optimized to 0 FDCE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/27/async_in_cell/u_ falling optimized to 0 FDCE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/27/async_in_cell/u_ rising optimized to 0 INV PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/27/async_in_cell/u_ statcmd_n LUT3 PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/27/async_in_cell/us er_mux LUT3 PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/28/async_in_cell/as ync_f_mux LUT3 PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/28/async_in_cell/as ync_r_mux FDE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/28/async_in_cell/s_ async_f_reg optimized to 0 FDE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/28/async_in_cell/s_ async_r_reg optimized to 0 FDE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/28/async_in_cell/s_ async_reg optimized to 0 FDE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/28/async_in_cell/s_ user_reg optimized to 0 FDCE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/28/async_in_cell/u_ falling optimized to 0 FDCE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/28/async_in_cell/u_ rising optimized to 0 INV PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/28/async_in_cell/u_ statcmd_n LUT3 PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/28/async_in_cell/us er_mux LUT3 PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/29/async_in_cell/as ync_f_mux LUT3 PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/29/async_in_cell/as ync_r_mux FDE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/29/async_in_cell/s_ async_f_reg optimized to 0 FDE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/29/async_in_cell/s_ async_r_reg optimized to 0 FDE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/29/async_in_cell/s_ async_reg optimized to 0 FDE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/29/async_in_cell/s_ user_reg optimized to 0 FDCE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/29/async_in_cell/u_ falling optimized to 0 FDCE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/29/async_in_cell/u_ rising optimized to 0 INV PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/29/async_in_cell/u_ statcmd_n LUT3 PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/29/async_in_cell/us er_mux LUT3 PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/3/async_in_cell/asy nc_f_mux LUT3 PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/3/async_in_cell/asy nc_r_mux FDE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/3/async_in_cell/s_a sync_f_reg optimized to 0 FDE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/3/async_in_cell/s_a sync_r_reg optimized to 0 FDE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/3/async_in_cell/s_a sync_reg optimized to 0 FDE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/3/async_in_cell/s_u ser_reg optimized to 0 FDCE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/3/async_in_cell/u_f alling optimized to 0 FDCE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/3/async_in_cell/u_r ising optimized to 0 INV PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/3/async_in_cell/u_s tatcmd_n LUT3 PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/3/async_in_cell/use r_mux LUT3 PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/30/async_in_cell/as ync_f_mux LUT3 PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/30/async_in_cell/as ync_r_mux FDE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/30/async_in_cell/s_ async_f_reg optimized to 0 FDE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/30/async_in_cell/s_ async_r_reg optimized to 0 FDE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/30/async_in_cell/s_ async_reg optimized to 0 FDE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/30/async_in_cell/s_ user_reg optimized to 0 FDCE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/30/async_in_cell/u_ falling optimized to 0 FDCE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/30/async_in_cell/u_ rising optimized to 0 INV PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/30/async_in_cell/u_ statcmd_n LUT3 PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/30/async_in_cell/us er_mux LUT3 PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/31/async_in_cell/as ync_f_mux LUT3 PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/31/async_in_cell/as ync_r_mux FDE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/31/async_in_cell/s_ async_f_reg optimized to 0 FDE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/31/async_in_cell/s_ async_r_reg optimized to 0 FDE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/31/async_in_cell/s_ async_reg optimized to 0 FDE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/31/async_in_cell/s_ user_reg optimized to 0 FDCE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/31/async_in_cell/u_ falling optimized to 0 FDCE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/31/async_in_cell/u_ rising optimized to 0 INV PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/31/async_in_cell/u_ statcmd_n LUT3 PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/31/async_in_cell/us er_mux LUT3 PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/4/async_in_cell/asy nc_f_mux LUT3 PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/4/async_in_cell/asy nc_r_mux FDE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/4/async_in_cell/s_a sync_f_reg optimized to 0 FDE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/4/async_in_cell/s_a sync_r_reg optimized to 0 FDE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/4/async_in_cell/s_a sync_reg optimized to 0 FDE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/4/async_in_cell/s_u ser_reg optimized to 0 FDCE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/4/async_in_cell/u_f alling optimized to 0 FDCE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/4/async_in_cell/u_r ising optimized to 0 INV PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/4/async_in_cell/u_s tatcmd_n LUT3 PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/4/async_in_cell/use r_mux LUT3 PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/5/async_in_cell/asy nc_f_mux LUT3 PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/5/async_in_cell/asy nc_r_mux FDE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/5/async_in_cell/s_a sync_f_reg optimized to 0 FDE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/5/async_in_cell/s_a sync_r_reg optimized to 0 FDE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/5/async_in_cell/s_a sync_reg optimized to 0 FDE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/5/async_in_cell/s_u ser_reg optimized to 0 FDCE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/5/async_in_cell/u_f alling optimized to 0 FDCE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/5/async_in_cell/u_r ising optimized to 0 INV PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/5/async_in_cell/u_s tatcmd_n LUT3 PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/5/async_in_cell/use r_mux LUT3 PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/6/async_in_cell/asy nc_f_mux LUT3 PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/6/async_in_cell/asy nc_r_mux FDE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/6/async_in_cell/s_a sync_f_reg optimized to 0 FDE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/6/async_in_cell/s_a sync_r_reg optimized to 0 FDE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/6/async_in_cell/s_a sync_reg optimized to 0 FDE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/6/async_in_cell/s_u ser_reg optimized to 0 FDCE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/6/async_in_cell/u_f alling optimized to 0 FDCE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/6/async_in_cell/u_r ising optimized to 0 INV PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/6/async_in_cell/u_s tatcmd_n LUT3 PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/6/async_in_cell/use r_mux LUT3 PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/7/async_in_cell/asy nc_f_mux LUT3 PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/7/async_in_cell/asy nc_r_mux FDE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/7/async_in_cell/s_a sync_f_reg optimized to 0 FDE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/7/async_in_cell/s_a sync_r_reg optimized to 0 FDE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/7/async_in_cell/s_a sync_reg optimized to 0 FDE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/7/async_in_cell/s_u ser_reg optimized to 0 FDCE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/7/async_in_cell/u_f alling optimized to 0 FDCE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/7/async_in_cell/u_r ising optimized to 0 INV PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/7/async_in_cell/u_s tatcmd_n LUT3 PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/7/async_in_cell/use r_mux LUT3 PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/8/async_in_cell/asy nc_f_mux LUT3 PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/8/async_in_cell/asy nc_r_mux FDE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/8/async_in_cell/s_a sync_f_reg optimized to 0 FDE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/8/async_in_cell/s_a sync_r_reg optimized to 0 FDE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/8/async_in_cell/s_a sync_reg optimized to 0 FDE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/8/async_in_cell/s_u ser_reg optimized to 0 FDCE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/8/async_in_cell/u_f alling optimized to 0 FDCE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/8/async_in_cell/u_r ising optimized to 0 INV PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/8/async_in_cell/u_s tatcmd_n LUT3 PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/8/async_in_cell/use r_mux LUT3 PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/9/async_in_cell/asy nc_f_mux LUT3 PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/9/async_in_cell/asy nc_r_mux FDE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/9/async_in_cell/s_a sync_f_reg optimized to 0 FDE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/9/async_in_cell/s_a sync_r_reg optimized to 0 FDE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/9/async_in_cell/s_a sync_reg optimized to 0 FDE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/9/async_in_cell/s_u ser_reg optimized to 0 FDCE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/9/async_in_cell/u_f alling optimized to 0 FDCE PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/9/async_in_cell/u_r ising optimized to 0 INV PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/9/async_in_cell/u_s tatcmd_n LUT3 PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_in/9/async_in_cell/use r_mux FDE PLL/chipscope/i_vio_control/vio_control/i_vio/u_data_out optimized to 0 LUT4 PLL/chipscope/i_vio_control/vio_control/i_vio/u_status/f_stat/3/u_stat LUT4 PLL/chipscope/i_vio_control/vio_control/i_vio/u_status/f_stat/5/u_stat LUT4 PLL/chipscope/i_vio_control/vio_control/i_vio/u_status/f_stat/6/u_stat LUT4 PLL/chipscope/i_vio_control/vio_control/i_vio/u_status/f_stat/7/u_stat LUT3 PLL/chipscope/i_vio_control/vio_control/i_vio/u_status/u_smux/i3/fj/3/u_lut3 GND PLL/ph_table_0/GND VCC PLL/ph_table_0/VCC GND XST_GND VCC XST_VCC To enable printing of redundant blocks removed and signals merged, set the detailed map report option and rerun map. Section 6 - IOB Properties -------------------------- +------------------------------------------------------------------------------------------------------------------------+ | IOB Name | Type | Direction | IO Standard | Drive | Slew | Reg (s) | Resistor | IOB | | | | | | Strength | Rate | | | Delay | +------------------------------------------------------------------------------------------------------------------------+ | adc_clk_ppad_i | DIFFM | INPUT | LVPECL_25 | | | | | | | clk125_ppad_i | DIFFM | INPUT | LVPECL_25 | | | | | | | ADC_CLK_A_i | IOB | INPUT | LVCMOS25 | | | | | | | ADC_CLK_B_i | IOB | INPUT | LVCMOS25 | | | | | | | ADC_CLK_C_i | IOB | INPUT | LVCMOS25 | | | | | | | ADC_CLK_D_i | IOB | INPUT | LVCMOS25 | | | | | | | ADC_RESET_o | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | OFF1 | | | | DIO<1> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | DIO<2> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | DIO<3> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | DIO<4> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | DIO<5> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | DIO<6> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | DIO<7> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | DIO<8> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | DIO<9> | IOB | BIDIR | LVCMOS25 | | | | | | | DIO<10> | IOB | BIDIR | LVCMOS25 | | | | | | | DIO<11> | IOB | BIDIR | LVCMOS25 | | | | | | | DIO<12> | IOB | BIDIR | LVCMOS25 | | | | | | | DIO<13> | IOB | BIDIR | LVCMOS25 | | | | | | | DIO<14> | IOB | BIDIR | LVCMOS25 | | | | | | | DIO<15> | IOB | BIDIR | LVCMOS25 | | | | | | | DIO<16> | IOB | BIDIR | LVCMOS25 | | | | | | | DIO<17> | IOB | INPUT | LVCMOS25 | | | INFF1 | | IFD | | DIO<18> | IOB | BIDIR | LVCMOS25 | | | | | | | DIO<19> | IOB | INPUT | LVCMOS25 | | | INFF1 | | IFD | | DIO<20> | IOB | INPUT | LVCMOS25 | | | INFF1 | | IFD | | DIO<21> | IOB | BIDIR | LVCMOS25 | | | | | | | DIO<22> | IOB | BIDIR | LVCMOS25 | | | | | | | DIO<23> | IOB | BIDIR | LVCMOS25 | | | | | | | DIO<24> | IOB | BIDIR | LVCMOS25 | | | | | | | DIR<0> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | DIR<1> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | DIR<2> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | DIR<3> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | DIR<4> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | DIR<5> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | adc_a_dat_pad_i<0> | IOB | INPUT | LVCMOS25 | | | INFF1 | | IFD | | adc_a_dat_pad_i<1> | IOB | INPUT | LVCMOS25 | | | INFF1 | | IFD | | adc_a_dat_pad_i<2> | IOB | INPUT | LVCMOS25 | | | INFF1 | | IFD | | adc_a_dat_pad_i<3> | IOB | INPUT | LVCMOS25 | | | INFF1 | | IFD | | adc_a_dat_pad_i<4> | IOB | INPUT | LVCMOS25 | | | INFF1 | | IFD | | adc_a_dat_pad_i<5> | IOB | INPUT | LVCMOS25 | | | INFF1 | | IFD | | adc_a_dat_pad_i<6> | IOB | INPUT | LVCMOS25 | | | INFF1 | | IFD | | adc_a_dat_pad_i<7> | IOB | INPUT | LVCMOS25 | | | INFF1 | | IFD | | adc_a_dat_pad_i<8> | IOB | INPUT | LVCMOS25 | | | INFF1 | | IFD | | adc_a_dat_pad_i<9> | IOB | INPUT | LVCMOS25 | | | INFF1 | | IFD | | adc_a_dat_pad_i<10> | IOB | INPUT | LVCMOS25 | | | INFF1 | | IFD | | adc_a_dat_pad_i<11> | IOB | INPUT | LVCMOS25 | | | INFF1 | | IFD | | adc_a_dat_pad_i<12> | IOB | INPUT | LVCMOS25 | | | INFF1 | | IFD | | adc_a_dat_pad_i<13> | IOB | INPUT | LVCMOS25 | | | | | | | adc_b_dat_pad_i<0> | IOB | INPUT | LVCMOS25 | | | INFF1 | | IFD | | adc_b_dat_pad_i<1> | IOB | INPUT | LVCMOS25 | | | INFF1 | | IFD | | adc_b_dat_pad_i<2> | IOB | INPUT | LVCMOS25 | | | INFF1 | | IFD | | adc_b_dat_pad_i<3> | IOB | INPUT | LVCMOS25 | | | INFF1 | | IFD | | adc_b_dat_pad_i<4> | IOB | INPUT | LVCMOS25 | | | INFF1 | | IFD | | adc_b_dat_pad_i<5> | IOB | INPUT | LVCMOS25 | | | INFF1 | | IFD | | adc_b_dat_pad_i<6> | IOB | INPUT | LVCMOS25 | | | INFF1 | | IFD | | adc_b_dat_pad_i<7> | IOB | INPUT | LVCMOS25 | | | INFF1 | | IFD | | adc_b_dat_pad_i<8> | IOB | INPUT | LVCMOS25 | | | INFF1 | | IFD | | adc_b_dat_pad_i<9> | IOB | INPUT | LVCMOS25 | | | INFF1 | | IFD | | adc_b_dat_pad_i<10> | IOB | INPUT | LVCMOS25 | | | INFF1 | | IFD | | adc_b_dat_pad_i<11> | IOB | INPUT | LVCMOS25 | | | INFF1 | | IFD | | adc_b_dat_pad_i<12> | IOB | INPUT | LVCMOS25 | | | INFF1 | | IFD | | adc_b_dat_pad_i<13> | IOB | INPUT | LVCMOS25 | | | | | | | adc_c_dat_pad_i<0> | IOB | INPUT | LVCMOS25 | | | INFF1 | | IFD | | adc_c_dat_pad_i<1> | IOB | INPUT | LVCMOS25 | | | INFF1 | | IFD | | adc_c_dat_pad_i<2> | IOB | INPUT | LVCMOS25 | | | INFF1 | | IFD | | adc_c_dat_pad_i<3> | IOB | INPUT | LVCMOS25 | | | INFF1 | | IFD | | adc_c_dat_pad_i<4> | IOB | INPUT | LVCMOS25 | | | INFF1 | | IFD | | adc_c_dat_pad_i<5> | IOB | INPUT | LVCMOS25 | | | INFF1 | | IFD | | adc_c_dat_pad_i<6> | IOB | INPUT | LVCMOS25 | | | INFF1 | | IFD | | adc_c_dat_pad_i<7> | IOB | INPUT | LVCMOS25 | | | INFF1 | | IFD | | adc_c_dat_pad_i<8> | IOB | INPUT | LVCMOS25 | | | INFF1 | | IFD | | adc_c_dat_pad_i<9> | IOB | INPUT | LVCMOS25 | | | INFF1 | | IFD | | adc_c_dat_pad_i<10> | IOB | INPUT | LVCMOS25 | | | INFF1 | | IFD | | adc_c_dat_pad_i<11> | IOB | INPUT | LVCMOS25 | | | INFF1 | | IFD | | adc_c_dat_pad_i<12> | IOB | INPUT | LVCMOS25 | | | INFF1 | | IFD | | adc_c_dat_pad_i<13> | IOB | INPUT | LVCMOS25 | | | | | | | adc_d_dat_pad_i<0> | IOB | INPUT | LVCMOS25 | | | | | | | adc_d_dat_pad_i<1> | IOB | INPUT | LVCMOS25 | | | | | | | adc_d_dat_pad_i<2> | IOB | INPUT | LVCMOS25 | | | | | | | adc_d_dat_pad_i<3> | IOB | INPUT | LVCMOS25 | | | | | | | adc_d_dat_pad_i<4> | IOB | INPUT | LVCMOS25 | | | | | | | adc_d_dat_pad_i<5> | IOB | INPUT | LVCMOS25 | | | | | | | adc_d_dat_pad_i<6> | IOB | INPUT | LVCMOS25 | | | | | | | adc_d_dat_pad_i<7> | IOB | INPUT | LVCMOS25 | | | | | | | adc_d_dat_pad_i<8> | IOB | INPUT | LVCMOS25 | | | | | | | adc_d_dat_pad_i<9> | IOB | INPUT | LVCMOS25 | | | | | | | adc_d_dat_pad_i<10> | IOB | INPUT | LVCMOS25 | | | | | | | adc_d_dat_pad_i<11> | IOB | INPUT | LVCMOS25 | | | | | | | adc_d_dat_pad_i<12> | IOB | INPUT | LVCMOS25 | | | | | | | adc_d_dat_pad_i<13> | IOB | INPUT | LVCMOS25 | | | | | | | bp_led0_pad_o | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | OFF1 | | | | bp_led1_pad_o | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | OFF1 | | | | bp_led2_pad_o | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | OFF1 | | | | ddr2high_addr_pad_o<0> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | ddr2high_addr_pad_o<1> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | ddr2high_addr_pad_o<2> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | ddr2high_addr_pad_o<3> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | ddr2high_addr_pad_o<4> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | ddr2high_addr_pad_o<5> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | ddr2high_addr_pad_o<6> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | ddr2high_addr_pad_o<7> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | ddr2high_addr_pad_o<8> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | ddr2high_addr_pad_o<9> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | ddr2high_addr_pad_o<10> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | ddr2high_addr_pad_o<11> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | ddr2high_addr_pad_o<12> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | ddr2high_bank_pad_o<0> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | ddr2high_bank_pad_o<1> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | ddr2high_casn_pad_o | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | ddr2high_cke_pad_o | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | ddr2high_clk_pad_o | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | ddr2high_clkn_pad_o | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | ddr2high_csn_pad_o | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | ddr2high_data_pad_io<0> | IOB | BIDIR | SSTL18_II | | | | | | | ddr2high_data_pad_io<1> | IOB | BIDIR | SSTL18_II | | | | | | | ddr2high_data_pad_io<2> | IOB | BIDIR | SSTL18_II | | | | | | | ddr2high_data_pad_io<3> | IOB | BIDIR | SSTL18_II | | | | | | | ddr2high_data_pad_io<4> | IOB | BIDIR | SSTL18_II | | | | | | | ddr2high_data_pad_io<5> | IOB | BIDIR | SSTL18_II | | | | | | | ddr2high_data_pad_io<6> | IOB | BIDIR | SSTL18_II | | | | | | | ddr2high_data_pad_io<7> | IOB | BIDIR | SSTL18_II | | | | | | | ddr2high_data_pad_io<8> | IOB | BIDIR | SSTL18_II | | | | | | | ddr2high_data_pad_io<9> | IOB | BIDIR | SSTL18_II | | | | | | | ddr2high_data_pad_io<10> | IOB | BIDIR | SSTL18_II | | | | | | | ddr2high_data_pad_io<11> | IOB | BIDIR | SSTL18_II | | | | | | | ddr2high_data_pad_io<12> | IOB | BIDIR | SSTL18_II | | | | | | | ddr2high_data_pad_io<13> | IOB | BIDIR | SSTL18_II | | | | | | | ddr2high_data_pad_io<14> | IOB | BIDIR | SSTL18_II | | | | | | | ddr2high_data_pad_io<15> | IOB | BIDIR | SSTL18_II | | | | | | | ddr2high_ldm_pad_o | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | ddr2high_ldqs_pad_io | IOB | BIDIR | SSTL18_II | | | | | | | ddr2high_ldqsn_pad_io | IOB | BIDIR | SSTL18_II | | | | | | | ddr2high_odt_pad_o | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | ddr2high_rasn_pad_o | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | ddr2high_udm_pad_o | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | ddr2high_udqs_pad_io | IOB | BIDIR | SSTL18_II | | | | | | | ddr2high_udqsn_pad_io | IOB | BIDIR | SSTL18_II | | | | | | | ddr2high_wen_pad_o | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | ddr2low_addr_pad_o<0> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | ddr2low_addr_pad_o<1> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | ddr2low_addr_pad_o<2> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | ddr2low_addr_pad_o<3> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | ddr2low_addr_pad_o<4> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | ddr2low_addr_pad_o<5> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | ddr2low_addr_pad_o<6> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | ddr2low_addr_pad_o<7> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | ddr2low_addr_pad_o<8> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | ddr2low_addr_pad_o<9> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | ddr2low_addr_pad_o<10> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | ddr2low_addr_pad_o<11> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | ddr2low_addr_pad_o<12> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | ddr2low_bank_pad_o<0> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | ddr2low_bank_pad_o<1> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | ddr2low_casn_pad_o | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | ddr2low_cke_pad_o | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | ddr2low_clk_pad_o | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | ddr2low_clkn_pad_o | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | ddr2low_data_pad_io<0> | IOB | BIDIR | SSTL18_II | | | | | | | ddr2low_data_pad_io<1> | IOB | BIDIR | SSTL18_II | | | | | | | ddr2low_data_pad_io<2> | IOB | BIDIR | SSTL18_II | | | | | | | ddr2low_data_pad_io<3> | IOB | BIDIR | SSTL18_II | | | | | | | ddr2low_data_pad_io<4> | IOB | BIDIR | SSTL18_II | | | | | | | ddr2low_data_pad_io<5> | IOB | BIDIR | SSTL18_II | | | | | | | ddr2low_data_pad_io<6> | IOB | BIDIR | SSTL18_II | | | | | | | ddr2low_data_pad_io<7> | IOB | BIDIR | SSTL18_II | | | | | | | ddr2low_data_pad_io<8> | IOB | BIDIR | SSTL18_II | | | | | | | ddr2low_data_pad_io<9> | IOB | BIDIR | SSTL18_II | | | | | | | ddr2low_data_pad_io<10> | IOB | BIDIR | SSTL18_II | | | | | | | ddr2low_data_pad_io<11> | IOB | BIDIR | SSTL18_II | | | | | | | ddr2low_data_pad_io<12> | IOB | BIDIR | SSTL18_II | | | | | | | ddr2low_data_pad_io<13> | IOB | BIDIR | SSTL18_II | | | | | | | ddr2low_data_pad_io<14> | IOB | BIDIR | SSTL18_II | | | | | | | ddr2low_data_pad_io<15> | IOB | BIDIR | SSTL18_II | | | | | | | ddr2low_ldm_pad_o | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | ddr2low_ldqs_pad_io | IOB | BIDIR | SSTL18_II | | | | | | | ddr2low_ldqsn_pad_io | IOB | BIDIR | SSTL18_II | | | | | | | ddr2low_odt_pad_o | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | ddr2low_rasn_pad_o | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | ddr2low_udm_pad_o | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | ddr2low_udqs_pad_io | IOB | BIDIR | SSTL18_II | | | | | | | ddr2low_udqsn_pad_io | IOB | BIDIR | SSTL18_II | | | | | | | ddr2low_wen_pad_o | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | fp_led_pad_o | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | lemo_il_pad_o | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | sbc_adr_pad_i<2> | IOB | INPUT | LVCMOS33 | | | | | | | sbc_adr_pad_i<3> | IOB | INPUT | LVCMOS33 | | | | | | | sbc_adr_pad_i<4> | IOB | INPUT | LVCMOS33 | | | | | | | sbc_adr_pad_i<5> | IOB | INPUT | LVCMOS33 | | | | | | | sbc_adr_pad_i<6> | IOB | INPUT | LVCMOS33 | | | | | | | sbc_adr_pad_i<7> | IOB | INPUT | LVCMOS33 | | | | | | | sbc_adr_pad_i<8> | IOB | INPUT | LVCMOS33 | | | | | | | sbc_adr_pad_i<9> | IOB | INPUT | LVCMOS33 | | | | | | | sbc_adr_pad_i<10> | IOB | INPUT | LVCMOS33 | | | | | | | sbc_adr_pad_i<11> | IOB | INPUT | LVCMOS33 | | | | | | | sbc_adr_pad_i<12> | IOB | INPUT | LVCMOS33 | | | | | | | sbc_adr_pad_i<13> | IOB | INPUT | LVCMOS33 | | | INFF1 | | IFD | | | | | | | | INFF2 | | | | sbc_adr_pad_i<14> | IOB | INPUT | LVCMOS33 | | | INFF1 | | IFD | | | | | | | | INFF2 | | | | sbc_adr_pad_i<15> | IOB | INPUT | LVCMOS33 | | | | | | | sbc_adr_pad_i<16> | IOB | INPUT | LVCMOS33 | | | | | | | sbc_adr_pad_i<17> | IOB | INPUT | LVCMOS33 | | | | | | | sbc_csn_pad_i | IOB | INPUT | LVCMOS33 | | | | | | | sbc_dat_pad_io<0> | IOB | BIDIR | LVCMOS33 | 12 | SLOW | INFF1 | | IFD | | sbc_dat_pad_io<1> | IOB | BIDIR | LVCMOS33 | 12 | SLOW | INFF1 | | IFD | | sbc_dat_pad_io<2> | IOB | BIDIR | LVCMOS33 | 12 | SLOW | INFF1 | | IFD | | | | | | | | INFF2 | | | | sbc_dat_pad_io<3> | IOB | BIDIR | LVCMOS33 | 12 | SLOW | INFF1 | | IFD | | sbc_dat_pad_io<4> | IOB | BIDIR | LVCMOS33 | 12 | SLOW | INFF1 | | IFD | | | | | | | | INFF2 | | | | sbc_dat_pad_io<5> | IOB | BIDIR | LVCMOS33 | 12 | SLOW | INFF1 | | IFD | | sbc_dat_pad_io<6> | IOB | BIDIR | LVCMOS33 | 12 | SLOW | INFF1 | | IFD | | sbc_dat_pad_io<7> | IOB | BIDIR | LVCMOS33 | 12 | SLOW | INFF1 | | IFD | | sbc_dat_pad_io<8> | IOB | BIDIR | LVCMOS33 | 12 | SLOW | INFF1 | | IFD | | sbc_dat_pad_io<9> | IOB | BIDIR | LVCMOS33 | 12 | SLOW | INFF1 | | IFD | | sbc_dat_pad_io<10> | IOB | BIDIR | LVCMOS33 | 12 | SLOW | INFF1 | | IFD | | | | | | | | INFF2 | | | | sbc_dat_pad_io<11> | IOB | BIDIR | LVCMOS33 | 12 | SLOW | INFF1 | | IFD | | sbc_dat_pad_io<12> | IOB | BIDIR | LVCMOS33 | 12 | SLOW | INFF1 | | IFD | | sbc_dat_pad_io<13> | IOB | BIDIR | LVCMOS33 | 12 | SLOW | INFF1 | | IFD | | sbc_dat_pad_io<14> | IOB | BIDIR | LVCMOS33 | 12 | SLOW | INFF1 | | IFD | | sbc_dat_pad_io<15> | IOB | BIDIR | LVCMOS33 | 12 | SLOW | INFF1 | | IFD | | sbc_dat_pad_io<16> | IOB | BIDIR | LVCMOS33 | 12 | SLOW | INFF1 | | IFD | | | | | | | | INFF2 | | | | sbc_dat_pad_io<17> | IOB | BIDIR | LVCMOS33 | 12 | SLOW | INFF1 | | IFD | | sbc_dat_pad_io<18> | IOB | BIDIR | LVCMOS33 | 12 | SLOW | INFF1 | | IFD | | sbc_dat_pad_io<19> | IOB | BIDIR | LVCMOS33 | 12 | SLOW | INFF1 | | IFD | | sbc_dat_pad_io<20> | IOB | BIDIR | LVCMOS33 | 12 | SLOW | INFF1 | | IFD | | sbc_dat_pad_io<21> | IOB | BIDIR | LVCMOS33 | 12 | SLOW | INFF1 | | IFD | | sbc_dat_pad_io<22> | IOB | BIDIR | LVCMOS33 | 12 | SLOW | INFF1 | | IFD | | sbc_dat_pad_io<23> | IOB | BIDIR | LVCMOS33 | 12 | SLOW | INFF1 | | IFD | | sbc_dat_pad_io<24> | IOB | BIDIR | LVCMOS33 | 12 | SLOW | INFF1 | | IFD | | sbc_dat_pad_io<25> | IOB | BIDIR | LVCMOS33 | 12 | SLOW | INFF1 | | IFD | | sbc_dat_pad_io<26> | IOB | BIDIR | LVCMOS33 | 12 | SLOW | INFF1 | | IFD | | sbc_dat_pad_io<27> | IOB | BIDIR | LVCMOS33 | 12 | SLOW | INFF1 | | IFD | | sbc_dat_pad_io<28> | IOB | BIDIR | LVCMOS33 | 12 | SLOW | INFF1 | | IFD | | sbc_dat_pad_io<29> | IOB | BIDIR | LVCMOS33 | 12 | SLOW | INFF1 | | IFD | | sbc_dat_pad_io<30> | IOB | BIDIR | LVCMOS33 | 12 | SLOW | INFF1 | | IFD | | sbc_dat_pad_io<31> | IOB | BIDIR | LVCMOS33 | 12 | SLOW | INFF1 | | IFD | | sbc_irq_pad_o | IOB | OUTPUT | LVCMOS33 | 12 | SLOW | | | | | sbc_rst_pad_o | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | sbc_wrn_pad_i | IOB | INPUT | LVCMOS33 | | | | | | | spi_clk_pad_o | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | spi_cs_adc1_pad_o | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | OFF1 | | | | spi_cs_adc2_pad_o | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | OFF1 | | | | spi_cs_adc3_pad_o | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | OFF1 | | | | spi_cs_adc4_pad_o | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | OFF1 | | | | spi_cs_ckm_pad_o | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | spi_data_pad_o | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | OFF1 | | | | spi_func_pad_o | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | OFF1 | | | | sys_clk106_en_pad_o | IOB | OUTPUT | LVCMOS33 | 12 | SLOW | OFF1 | | | | sys_clk125_en_pad_o | IOB | OUTPUT | LVCMOS33 | 12 | SLOW | | | | | vcxo | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | OFF1 | | | +------------------------------------------------------------------------------------------------------------------------+ Section 7 - RPMs ---------------- PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_trig/u_tm/g_nmu/0/u_m/u_mu/i_mut_gand/u_match/pd_rpm PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/u_wcnt_lcmp/pd_rpm PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/u_wcnt_hcmp/pd_rpm PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/u_scnt_cmp/pd_rpm PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_wlcmpce/pd_rpm PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_whcmpce/pd_rpm PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_scrst/pd_rpm PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_scmpce/pd_rpm PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_ns1/pd_rpm PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_ns0/pd_rpm PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_cmpreset/pd_rpm PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_cdone/pd_rpm PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_trig/u_tm/g_nmu/0/u_m/u_mu/i_mut_gand/u_match/pd_rpm PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/u_wcnt_lcmp/pd_rpm PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/u_wcnt_hcmp/pd_rpm PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/u_scnt_cmp/pd_rpm PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_wlcmpce/pd_rpm PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_whcmpce/pd_rpm PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_scrst/pd_rpm PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_scmpce/pd_rpm PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_ns1/pd_rpm PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_ns0/pd_rpm PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_cmpreset/pd_rpm PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_cdone/pd_rpm Section 8 - Guide Report ------------------------ NCD slice data_out<29> was NOT guided. NCD slice reg0<9> was NOT guided. NCD slice reg2<1> was NOT guided. NCD slice data_out<31>_map3 was NOT guided. NCD slice PLL/_n0040<20>_map2113 was NOT guided. NCD slice reg4<15> was NOT guided. NCD slice reg4<23> was NOT guided. NCD slice reg4<31> was NOT guided. NCD slice regC<29> was NOT guided. NCD slice regD<13> was NOT guided. NCD slice regD<21> was NOT guided. NCD slice PLL/Mcompar__n0064_xnor_cyo11 was NOT guided. NCD slice reg2<3> was NOT guided. NCD slice reg4<17> was NOT guided. NCD slice reg4<25> was NOT guided. NCD slice regD<15> was NOT guided. NCD slice regD<23> was NOT guided. NCD slice regD<31> was NOT guided. NCD slice PLL/Mcompar__n0064_xnor_cyo13 was NOT guided. NCD slice PLL/Mcompar__n0064_xnor_cyo21 was NOT guided. NCD slice PLL/_n0040<13>_map2005 was NOT guided. NCD slice data_out<0> was NOT guided. NCD slice PLL/Mcompar__n0064_xnor_cyo15 was NOT guided. NCD slice PLL/Mcompar__n0064_xnor_cyo23 was NOT guided. NCD slice reg2<5> was NOT guided. NCD slice reg3<1> was NOT guided. NCD slice reg4<19> was NOT guided. NCD slice reg4<27> was NOT guided. NCD slice reg5<11> was NOT guided. NCD slice PLL/_n0040<8>_map1945 was NOT guided. NCD slice data_out<1> was NOT guided. NCD slice regD<17> was NOT guided. NCD slice regD<25> was NOT guided. NCD slice PLL/HC_tab_addr_cnt<4> was NOT guided. NCD slice PLL/Mcompar__n0064_xnor_cyo17 was NOT guided. NCD slice PLL/Mcompar__n0064_xnor_cyo25 was NOT guided. NCD slice data_out<2> was NOT guided. NCD slice PLL/chipscope/trig_del1<1> was NOT guided. NCD slice PLL/s4<10> was NOT guided. NCD slice PLL/Mcompar__n0064_xnor_cyo19 was NOT guided. NCD slice PLL/Mcompar__n0064_xnor_cyo27 was NOT guided. NCD slice reg2<7> was NOT guided. NCD slice reg3<3> was NOT guided. NCD slice reg4<29> was NOT guided. NCD slice reg5<13> was NOT guided. NCD slice reg5<21> was NOT guided. NCD slice data_out<3> was NOT guided. NCD slice regD<19> was NOT guided. NCD slice regD<27> was NOT guided. NCD slice PLL/Mcompar__n0064_xnor_cyo29 was NOT guided. NCD slice data_out<4> was NOT guided. NCD slice PLL/s4<12> was NOT guided. NCD slice PLL/s4<20> was NOT guided. NCD slice reg2<9> was NOT guided. NCD slice reg3<5> was NOT guided. NCD slice reg4<1> was NOT guided. NCD slice reg5<15> was NOT guided. NCD slice reg5<23> was NOT guided. NCD slice reg5<31> was NOT guided. NCD slice data_out<5> was NOT guided. NCD slice PLL/N332 was NOT guided. NCD slice PLL/N308 was NOT guided. NCD slice regD<29> was NOT guided. NCD slice PLL/Mcompar__n0061_xnor_cyo1 was NOT guided. NCD slice PLL/_n0040<21>_map2137 was NOT guided. NCD slice PLL/Mcompar__n0061_xnor_cyo3 was NOT guided. NCD slice PLL/HC_timing_rising was NOT guided. NCD slice data_out<6> was NOT guided. NCD slice PLL/s4<14> was NOT guided. NCD slice PLL/s4<22> was NOT guided. NCD slice reg3<7> was NOT guided. NCD slice reg4<3> was NOT guided. NCD slice PLL/_n0040<14>_map2017 was NOT guided. NCD slice PLL/_n0040<10>_map1969 was NOT guided. NCD slice reg5<17> was NOT guided. NCD slice reg5<25> was NOT guided. NCD slice PLL/Mcompar__n0061_xnor_cyo5 was NOT guided. NCD slice data_out<7> was NOT guided. NCD slice PLL/_n0040<9>_map1957 was NOT guided. NCD slice PLL/Mcompar__n0061_xnor_cyo7 was NOT guided. NCD slice data_out<8> was NOT guided. NCD slice PLL/s4<16> was NOT guided. NCD slice data_out<20>_map1070 was NOT guided. NCD slice reg3<9> was NOT guided. NCD slice reg4<5> was NOT guided. NCD slice reg5<1> was NOT guided. NCD slice reg5<19> was NOT guided. NCD slice reg5<27> was NOT guided. NCD slice reg6<11> was NOT guided. NCD slice PLL/Mcompar__n0061_xnor_cyo9 was NOT guided. NCD slice data_out<9> was NOT guided. NCD slice PLL/N284 was NOT guided. NCD slice PLL/_n0040<11>_map1981 was NOT guided. NCD slice data_out<21>_map1007 was NOT guided. NCD slice PLL/s4<18> was NOT guided. NCD slice data_out<20>_map1058 was NOT guided. NCD slice reg4<7> was NOT guided. NCD slice reg5<3> was NOT guided. NCD slice PLL/inj_trig_rising was NOT guided. NCD slice PLL/_n0040<22>_map2161 was NOT guided. NCD slice reg5<29> was NOT guided. NCD slice reg6<13> was NOT guided. NCD slice reg6<21> was NOT guided. NCD slice regF<11> was NOT guided. NCD slice data_out<21>_map1019 was NOT guided. NCD slice data_out<4>154_2 was NOT guided. NCD slice reg4<9> was NOT guided. NCD slice reg5<5> was NOT guided. NCD slice reg6<1> was NOT guided. NCD slice reg6<15> was NOT guided. NCD slice reg6<23> was NOT guided. NCD slice reg6<31> was NOT guided. NCD slice regF<13> was NOT guided. NCD slice regF<21> was NOT guided. NCD slice PLL/_n0040<15>_map2029 was NOT guided. NCD slice reg5<7> was NOT guided. NCD slice reg6<3> was NOT guided. NCD slice PLL/_n0040<30>_map2441 was NOT guided. NCD slice reg6<17> was NOT guided. NCD slice reg6<25> was NOT guided. NCD slice data_out<8>154_2 was NOT guided. NCD slice regF<15> was NOT guided. NCD slice regF<23> was NOT guided. NCD slice regF<31> was NOT guided. NCD slice PLL/_n0040<30>_map2442 was NOT guided. NCD slice data_out<10>154_2 was NOT guided. NCD slice PLL/_n0040<30>_map2444 was NOT guided. NCD slice reg5<9> was NOT guided. NCD slice reg6<5> was NOT guided. NCD slice PLL/_n0040<16>_map2041 was NOT guided. NCD slice PLL/_n0040<12>_map1993 was NOT guided. NCD slice reg6<19> was NOT guided. NCD slice reg6<27> was NOT guided. NCD slice regF<17> was NOT guided. NCD slice regF<25> was NOT guided. NCD slice PLL/s6<10> was NOT guided. NCD slice reg6<7> was NOT guided. NCD slice PLL/_n0040<24>_map2221 was NOT guided. NCD slice reg6<29> was NOT guided. NCD slice data_out<22>_map1320 was NOT guided. NCD slice regF<19> was NOT guided. NCD slice regF<27> was NOT guided. NCD slice PLL/_n0040<23>_map2185 was NOT guided. NCD slice PLL/s6<12> was NOT guided. NCD slice PLL/s6<20> was NOT guided. NCD slice reg6<9> was NOT guided. NCD slice regF<29> was NOT guided. NCD slice PLL/chipscope/_n0037 was NOT guided. NCD slice PLL/s6<14> was NOT guided. NCD slice PLL/s6<22> was NOT guided. NCD slice data_out<22>_map1343 was NOT guided. NCD slice PLL/_n0040<17>_map2053 was NOT guided. NCD slice PLL/_n0040<31>_map2481 was NOT guided. NCD slice PLL/n2<0> was NOT guided. NCD slice PLL/s6<16> was NOT guided. NCD slice PLL/_n0040<31>_map2482 was NOT guided. NCD slice data_out<13>_map1733 was NOT guided. NCD slice data_out<22>_map1355 was NOT guided. NCD slice PLL/_n0040<31>_map2484 was NOT guided. NCD slice data_out<13>_map1743 was NOT guided. NCD slice PLL/Mshift_F_ERR_Result<6>_map2252 was NOT guided. NCD slice PLL/n2<2> was NOT guided. NCD slice data_out<24>_map1202 was NOT guided. NCD slice PLL/s6<18> was NOT guided. NCD slice data_out<23>_map1261 was NOT guided. NCD slice PLL/mult_out<2> was NOT guided. NCD slice PLL/dds_freq_UR was NOT guided. NCD slice PLL/n2<4> was NOT guided. NCD slice PLL/n3<0> was NOT guided. NCD slice PLL/Mshift_F_ERR_Result<7>_map2216 was NOT guided. NCD slice PLL/F_ERR<5> was NOT guided. NCD slice PLL/mult_out<4> was NOT guided. NCD slice PLL/_n0040<25>_map2257 was NOT guided. NCD slice PLL/n2<6> was NOT guided. NCD slice PLL/n3<2> was NOT guided. NCD slice PLL/_n0040<18>_map2065 was NOT guided. NCD slice PLL/mult_out<6> was NOT guided. NCD slice data_out<15>_map1614 was NOT guided. NCD slice data_out<15>_map1615 was NOT guided. NCD slice PLL/F_ERR<8> was NOT guided. NCD slice PLL/n4<0> was NOT guided. NCD slice PLL/n2<8> was NOT guided. NCD slice PLL/n3<4> was NOT guided. NCD slice PLL/n2<10> was NOT guided. NCD slice data_out<15>_map1631 was NOT guided. NCD slice data_out<14>_map1674 was NOT guided. NCD slice data_out<15>_map1625 was NOT guided. NCD slice PLL/mult_out<8> was NOT guided. NCD slice data_out<14>_map1684 was NOT guided. NCD slice PLL/F_ERR<12> was NOT guided. NCD slice PLL/n4<2> was NOT guided. NCD slice PLL/n3<6> was NOT guided. NCD slice PLL/n2<12> was NOT guided. NCD slice PLL/n2<20> was NOT guided. NCD slice PLL/mult_out<10> was NOT guided. NCD slice PLL/chipscope/i_ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/wcnt_lcmp_q was NOT guided. NCD slice PLL/chipscope/i_ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/wcnt_hcmp_q was NOT guided. NCD slice PLL/chipscope/i_ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/scnt_cmp_q was NOT guided. NCD slice PLL/chipscope/i_ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/wcnt_lcmp_q was NOT guided. NCD slice PLL/chipscope/i_ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/wcnt_hcmp_q was NOT guided. NCD slice PLL/chipscope/i_ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/scnt_cmp_q was NOT guided. NCD slice PLL/_n0053<12> was NOT guided. NCD slice Ker32_2 was NOT guided. NCD slice PLL/HC_synch was NOT guided. NCD slice data_out<20>_map1047 was NOT guided. NCD slice data_out<21>_map996 was NOT guided. NCD slice data_out<25>_map945 was NOT guided. NCD slice data_out<26>_map101 was NOT guided. NCD slice PLL/HC_temp was NOT guided. NCD slice PLL/change_PT was NOT guided. NCD slice PLL/C_timer_stop was NOT guided. NCD slice PLL/_n0052 was NOT guided. NCD slice PLL/_n0029 was NOT guided. NCD slice PLL/n6_23_2 was NOT guided. NCD slice PLL/n6_23_3 was NOT guided. NCD slice data_out<5>_map1155 was NOT guided. NCD slice data_out<8>_map216 was NOT guided. NCD slice data_out<8>_map227 was NOT guided. NCD slice PLL/dds_freq_2__n0000 was NOT guided. NCD slice PLL/dds_freq_3__n0000 was NOT guided. NCD slice ADC_A_buf_13_1 was NOT guided. NCD slice PLL/dds_freq_4__n0000 was NOT guided. NCD slice PLL/dds_freq_5__n0000 was NOT guided. NCD slice PLL/dds_freq_8__n0000 was NOT guided. NCD slice PLL/n6<23> was NOT guided. NCD slice N6386 was NOT guided. NCD slice PLL/dds_ph<0> was NOT guided. NCD slice PLL/Mcompar__n0064_xnor_cyo1 was NOT guided. NCD slice PLL/mult_out<12> was NOT guided. NCD slice PLL/dds_freq<0> was NOT guided. NCD slice PLL/n4<4> was NOT guided. NCD slice PLL/n3<8> was NOT guided. NCD slice PLL/n5<0> was NOT guided. NCD slice PLL/n2<14> was NOT guided. NCD slice PLL/n2<22> was NOT guided. NCD slice PLL/Mcompar__n0064_xnor_cyo3 was NOT guided. NCD slice PLL/_n0040<26>_map2293 was NOT guided. NCD slice PLL/dds_freq<1> was NOT guided. NCD slice PLL/mult_out<13> was NOT guided. NCD slice PLL/dds_ph<2> was NOT guided. NCD slice PLL/Mcompar__n0064_xnor_cyo5 was NOT guided. NCD slice PLL/_n0040<27>_map2332 was NOT guided. NCD slice PLL/_n0077_wg_cy1 was NOT guided. NCD slice data_out<16>_map1561 was NOT guided. NCD slice PLL/dds_freq<2> was NOT guided. NCD slice PLL/n4<6> was NOT guided. NCD slice PLL/n5<2> was NOT guided. NCD slice PLL/n2<16> was NOT guided. NCD slice PLL/Mcompar__n0064_xnor_cyo7 was NOT guided. NCD slice PLL/N0 was NOT guided. NCD slice PLL/_n0077_wg_cy3 was NOT guided. NCD slice PLL/N1 was NOT guided. NCD slice PLL/dds_freq<3> was NOT guided. NCD slice PLL/dds_ph<4> was NOT guided. NCD slice PLL/_n0077_wg_cy4 was NOT guided. NCD slice PLL/Mcompar__n0064_xnor_cyo9 was NOT guided. NCD slice data_out<16>_map1556 was NOT guided. NCD slice PLL/_n0040<27>_map2329 was NOT guided. NCD slice PLL/_n0040<19>_map2089 was NOT guided. NCD slice data_out<17>_map1507 was NOT guided. NCD slice PLL/dds_freq<4> was NOT guided. NCD slice PLL/n4<8> was NOT guided. NCD slice PLL/n6<0> was NOT guided. NCD slice PLL/n5<4> was NOT guided. NCD slice PLL/n2<18> was NOT guided. NCD slice PLL/n3<10> was NOT guided. NCD slice data_out<16>_map1566 was NOT guided. NCD slice data_out<18>_map1402 was NOT guided. NCD slice PLL/dds_freq<5> was NOT guided. NCD slice PLL/dds_ph<6> was NOT guided. NCD slice PLL/dds_freq<6> was NOT guided. NCD slice PLL/n6<2> was NOT guided. NCD slice PLL/n5<6> was NOT guided. NCD slice PLL/n3<12> was NOT guided. NCD slice PLL/n3<20> was NOT guided. NCD slice data_out<1>154_2 was NOT guided. NCD slice PLL/C_timer_count<0> was NOT guided. NCD slice N5055 was NOT guided. NCD slice data_out<18>_map1414 was NOT guided. NCD slice PLL/dds_freq<7> was NOT guided. NCD slice PLL/dds_ph<8> was NOT guided. NCD slice PLL/dds_freq<8> was NOT guided. NCD slice PLL/n6<4> was NOT guided. NCD slice PLL/n5<8> was NOT guided. NCD slice PLL/n3<14> was NOT guided. NCD slice PLL/n3<22> was NOT guided. NCD slice PLL/C_timer_count<2> was NOT guided. NCD slice PLL/dds_freq<9> was NOT guided. NCD slice PLL/chipscope/i_ila_6CH/i_dt0/1/data_dly1_80 was NOT guided. NCD slice PLL/_n0040<29>_map2401 was NOT guided. NCD slice PLL/n6<6> was NOT guided. NCD slice PLL/n3<16> was NOT guided. NCD slice N6310 was NOT guided. NCD slice PLL/_n0040<29>_map2402 was NOT guided. NCD slice PLL/C_timer_count<4> was NOT guided. NCD slice N6304 was NOT guided. NCD slice PLL/_n0040<28>_map2365 was NOT guided. NCD slice data_out<17>_map1497 was NOT guided. NCD slice data_out<9>154_2 was NOT guided. NCD slice PLL/_n0040<28>_map2366 was NOT guided. NCD slice PLL/_n0040<29>_map2404 was NOT guided. NCD slice data_out<18>_map1384 was NOT guided. NCD slice PLL/_n0053<10> was NOT guided. NCD slice N6402 was NOT guided. NCD slice data_out<30>_map61 was NOT guided. NCD slice PLL/chipscope/i_ila_6CH/i_dt0/1/data_dly1_85 was NOT guided. NCD slice PLL/n6<8> was NOT guided. NCD slice PLL/n4<10> was NOT guided. NCD slice PLL/n3<18> was NOT guided. NCD slice data_out<11>154_2 was NOT guided. NCD slice PLL/_n0040<28>_map2368 was NOT guided. NCD slice PLL/chipscope/i_ila_6CH/i_dt0/1/data_dly1_86 was NOT guided. NCD slice PLL/C_timer_count<6> was NOT guided. NCD slice N6404 was NOT guided. NCD slice data_out<18>_map1379 was NOT guided. NCD slice PLL/chipscope/i_ila_6CH/i_dt0/1/data_dly1_87 was NOT guided. NCD slice PLL/chipscope/i_ila_6CH/i_dt0/1/data_dly1_79 was NOT guided. NCD slice N6316 was NOT guided. NCD slice PLL/_n0053<20> was NOT guided. NCD slice N6406 was NOT guided. NCD slice data_out<19>_map1443 was NOT guided. NCD slice PLL/n4<12> was NOT guided. NCD slice PLL/n4<20> was NOT guided. NCD slice PLL/C_timer_count<8> was NOT guided. NCD slice PLL/x0<10> was NOT guided. NCD slice N6520 was NOT guided. NCD slice data_out<19>_map1437 was NOT guided. NCD slice data_out<19>_map1461 was NOT guided. NCD slice data_out<19>_map1438 was NOT guided. NCD slice PLL/_n0053<14> was NOT guided. NCD slice PLL/_n0053<22> was NOT guided. NCD slice data_out<19>_map1454 was NOT guided. NCD slice PLL/n4<14> was NOT guided. NCD slice PLL/n4<22> was NOT guided. NCD slice N6523 was NOT guided. NCD slice data_out<19>_map1448 was NOT guided. NCD slice PLL/x0<12> was NOT guided. NCD slice PLL/x0<20> was NOT guided. NCD slice N6532 was NOT guided. NCD slice data_out<19>_map1473 was NOT guided. NCD slice N6517 was NOT guided. NCD slice PLL/_n0053<16> was NOT guided. NCD slice N6526 was NOT guided. NCD slice PLL/n4<16> was NOT guided. NCD slice PLL/dds_ph<10> was NOT guided. NCD slice PLL/x0<14> was NOT guided. NCD slice PLL/x0<22> was NOT guided. NCD slice N6560 was NOT guided. NCD slice data_out<2>_map600 was NOT guided. NCD slice data_out<1>_map509 was NOT guided. NCD slice N6529 was NOT guided. NCD slice PLL/_n0053<18> was NOT guided. NCD slice PLL/_n0054<10> was NOT guided. NCD slice PLL/dds_freq<10> was NOT guided. NCD slice PLL/n4<18> was NOT guided. NCD slice PLL/n5<10> was NOT guided. NCD slice data_out<4>_map320 was NOT guided. NCD slice N6554 was NOT guided. NCD slice PLL/dds_ph<12> was NOT guided. NCD slice PLL/dds_ph<20> was NOT guided. NCD slice PLL/x0<16> was NOT guided. NCD slice N6388 was NOT guided. NCD slice regA<1> was NOT guided. NCD slice N6580 was NOT guided. NCD slice PLL/dds_freq<11> was NOT guided. NCD slice N6557 was NOT guided. NCD slice data_out<1>_map474 was NOT guided. NCD slice N6581 was NOT guided. NCD slice data_out<2>_map605 was NOT guided. NCD slice PLL/_n0054<12> was NOT guided. NCD slice PLL/_n0054<20> was NOT guided. NCD slice N6566 was NOT guided. NCD slice PLL/dds_ph<30> was NOT guided. NCD slice N6718 was NOT guided. NCD slice PLL/n5<12> was NOT guided. NCD slice PLL/n5<20> was NOT guided. NCD slice PLL/dds_freq<20> was NOT guided. NCD slice PLL/dds_freq<12> was NOT guided. NCD slice PLL/dds_ph<14> was NOT guided. NCD slice PLL/dds_ph<22> was NOT guided. NCD slice N6575 was NOT guided. NCD slice N6583 was NOT guided. NCD slice PLL/x1<10> was NOT guided. NCD slice PLL/x0<18> was NOT guided. NCD slice data_out<26>_map97 was NOT guided. NCD slice regA<3> was NOT guided. NCD slice N6568 was NOT guided. NCD slice N6584 was NOT guided. NCD slice data_out<1>_map469 was NOT guided. NCD slice PLL/dds_freq<21> was NOT guided. NCD slice PLL/dds_freq<13> was NOT guided. NCD slice N6569 was NOT guided. NCD slice PLL/_n0054<14> was NOT guided. NCD slice PLL/_n0054<22> was NOT guided. NCD slice data_out<3>_map532 was NOT guided. NCD slice PLL/dds_freq<30> was NOT guided. NCD slice data_out<4>_map280 was NOT guided. NCD slice PLL/n5<14> was NOT guided. NCD slice PLL/n5<22> was NOT guided. NCD slice PLL/dds_freq<22> was NOT guided. NCD slice PLL/dds_freq<14> was NOT guided. NCD slice PLL/dds_ph<24> was NOT guided. NCD slice PLL/dds_ph<16> was NOT guided. NCD slice data_out<3>_map542 was NOT guided. NCD slice PLL/x1<12> was NOT guided. NCD slice PLL/x1<20> was NOT guided. NCD slice data_out<2>_map635 was NOT guided. NCD slice regA<5> was NOT guided. NCD slice PLL/dds_freq<31> was NOT guided. NCD slice PLL/dds_freq<23> was NOT guided. NCD slice PLL/dds_freq<15> was NOT guided. NCD slice PLL/_n0054<16> was NOT guided. NCD slice PLL/dds_ph<26> was NOT guided. NCD slice PLL/n5<16> was NOT guided. NCD slice PLL/dds_freq<24> was NOT guided. NCD slice PLL/dds_freq<16> was NOT guided. NCD slice PLL/dds_ph<18> was NOT guided. NCD slice PLL/x1<14> was NOT guided. NCD slice PLL/x1<22> was NOT guided. NCD slice regA<7> was NOT guided. NCD slice PLL/dds_freq<25> was NOT guided. NCD slice PLL/dds_freq<17> was NOT guided. NCD slice PLL/_n0054<18> was NOT guided. NCD slice PLL/_n0055<10> was NOT guided. NCD slice data_out<3>_map572 was NOT guided. NCD slice data_out<2>_map594 was NOT guided. NCD slice PLL/dds_ph<28> was NOT guided. NCD slice PLL/n6<10> was NOT guided. NCD slice PLL/n5<18> was NOT guided. NCD slice PLL/dds_freq<18> was NOT guided. NCD slice PLL/dds_freq<26> was NOT guided. NCD slice PLL/Mcompar__n0061_xnor_cyo11 was NOT guided. NCD slice PLL/x1<16> was NOT guided. NCD slice data_out<2>_map595 was NOT guided. NCD slice regA<9> was NOT guided. NCD slice regC<1> was NOT guided. NCD slice PLL/dds_freq<19> was NOT guided. NCD slice PLL/dds_freq<27> was NOT guided. NCD slice PLL/Mcompar__n0061_xnor_cyo21 was NOT guided. NCD slice PLL/Mcompar__n0061_xnor_cyo13 was NOT guided. NCD slice PLL/_n0055<12> was NOT guided. NCD slice PLL/_n0055<20> was NOT guided. NCD slice PLL/n6<12> was NOT guided. NCD slice PLL/n6<20> was NOT guided. NCD slice PLL/dds_freq<28> was NOT guided. NCD slice data_out<7>_map342 was NOT guided. NCD slice PLL/Mcompar__n0061_xnor_cyo15 was NOT guided. NCD slice PLL/Mcompar__n0061_xnor_cyo23 was NOT guided. NCD slice data_out<8>_map217 was NOT guided. NCD slice PLL/y0<10> was NOT guided. NCD slice PLL/x1<18> was NOT guided. NCD slice PLL/x2<10> was NOT guided. NCD slice regC<3> was NOT guided. NCD slice data_out<7>_map343 was NOT guided. NCD slice PLL/dds_freq<29> was NOT guided. NCD slice PLL/_n0055<14> was NOT guided. NCD slice PLL/Mcompar__n0061_xnor_cyo17 was NOT guided. NCD slice PLL/Mcompar__n0061_xnor_cyo25 was NOT guided. NCD slice PLL/_n0055<22> was NOT guided. NCD slice PLL/n6<14> was NOT guided. NCD slice PLL/n6<22> was NOT guided. NCD slice PLL/N21 was NOT guided. NCD slice PLL/Mcompar__n0061_xnor_cyo19 was NOT guided. NCD slice PLL/Mcompar__n0061_xnor_cyo27 was NOT guided. NCD slice PLL/y0<12> was NOT guided. NCD slice PLL/y0<20> was NOT guided. NCD slice PLL/x2<12> was NOT guided. NCD slice PLL/x2<20> was NOT guided. NCD slice regC<5> was NOT guided. NCD slice regD<1> was NOT guided. NCD slice PLL/C_timer_count<10> was NOT guided. NCD slice data_out<7>_map348 was NOT guided. NCD slice PLL/N31 was NOT guided. NCD slice PLL/Mcompar__n0061_xnor_cyo29 was NOT guided. NCD slice PLL/_n0055<16> was NOT guided. NCD slice data_out<9>_map411 was NOT guided. NCD slice PLL/n6<16> was NOT guided. NCD slice PLL/y0<14> was NOT guided. NCD slice PLL/y0<22> was NOT guided. NCD slice PLL/x2<14> was NOT guided. NCD slice PLL/x2<22> was NOT guided. NCD slice data_out<8>_map257 was NOT guided. NCD slice data_out<9>_map405 was NOT guided. NCD slice regC<7> was NOT guided. NCD slice regD<3> was NOT guided. NCD slice data_out<10>_map154 was NOT guided. NCD slice PLL/C_timer_count<12> was NOT guided. NCD slice data_out<7>_map383 was NOT guided. NCD slice data_out<9>_map406 was NOT guided. NCD slice PLL/_n0056<10> was NOT guided. NCD slice PLL/_n0055<18> was NOT guided. NCD slice PLL/n6<18> was NOT guided. NCD slice PLL/s4<0> was NOT guided. NCD slice data_out<9>_map416 was NOT guided. NCD slice PLL/y0<16> was NOT guided. NCD slice PLL/x2<16> was NOT guided. NCD slice PLL/init_INV was NOT guided. NCD slice regC<9> was NOT guided. NCD slice regD<5> was NOT guided. NCD slice PLL/C_timer_count<14> was NOT guided. NCD slice PLL/_n0056<20> was NOT guided. NCD slice PLL/_n0056<12> was NOT guided. NCD slice PLL/s4<2> was NOT guided. NCD slice data_out<2>154_2 was NOT guided. NCD slice PLL/y0<18> was NOT guided. NCD slice PLL/y1<10> was NOT guided. NCD slice PLL/x2<18> was NOT guided. NCD slice regD<7> was NOT guided. NCD slice PLL/C_timer_count<16> was NOT guided. NCD slice data_out<10>_map194 was NOT guided. NCD slice PLL/_n0056<22> was NOT guided. NCD slice PLL/_n0056<30> was NOT guided. NCD slice data_out<9>_map446 was NOT guided. NCD slice PLL/_n0056<14> was NOT guided. NCD slice PLL/s4<4> was NOT guided. NCD slice PLL/y1<12> was NOT guided. NCD slice PLL/y1<20> was NOT guided. NCD slice regF<1> was NOT guided. NCD slice regD<9> was NOT guided. NCD slice PLL/_n0056<16> was NOT guided. NCD slice PLL/_n0056<24> was NOT guided. NCD slice PLL/s4<6> was NOT guided. NCD slice PLL/y1<14> was NOT guided. NCD slice PLL/y1<22> was NOT guided. NCD slice regF<3> was NOT guided. NCD slice PLL/Mcompar__n0061_ge_cyo was NOT guided. NCD slice PLL/_n0056<26> was NOT guided. NCD slice PLL/_n0056<18> was NOT guided. NCD slice PLL/s4<8> was NOT guided. NCD slice PLL/s6<0> was NOT guided. NCD slice data_out<12>154_2 was NOT guided. NCD slice PLL/y1<16> was NOT guided. NCD slice regF<5> was NOT guided. NCD slice PLL/_n0056<28> was NOT guided. NCD slice PLL/s6<2> was NOT guided. NCD slice PLL/y1<18> was NOT guided. NCD slice PLL/y2<10> was NOT guided. NCD slice regF<7> was NOT guided. NCD slice data_out<12>_map720 was NOT guided. NCD slice data_out<12>_map721 was NOT guided. NCD slice PLL/Mshift_F_ERR_Result<2>16/O was NOT guided. NCD slice PLL/s6<4> was NOT guided. NCD slice PLL/_n0040<0>_map1835 was NOT guided. NCD slice PLL/y2<12> was NOT guided. NCD slice PLL/y2<20> was NOT guided. NCD slice regF<9> was NOT guided. NCD slice data_out<11>_map658 was NOT guided. NCD slice PLL/s6<6> was NOT guided. NCD slice data_out<0>_map1803 was NOT guided. NCD slice PLL/y2<14> was NOT guided. NCD slice PLL/y2<22> was NOT guided. NCD slice reg0<11> was NOT guided. NCD slice data_out<12>_map761 was NOT guided. NCD slice data_out<26>_map108 was NOT guided. NCD slice PLL/s6<8> was NOT guided. NCD slice PLL/y2<16> was NOT guided. NCD slice reg0<13> was NOT guided. NCD slice reg0<21> was NOT guided. NCD slice data_out<0>_map1808 was NOT guided. NCD slice data_out<11>_map698 was NOT guided. NCD slice PLL/mult_neg_data_in<12> was NOT guided. NCD slice PLL/Mshift_F_ERR_Sh<50> was NOT guided. NCD slice PLL/y2<18> was NOT guided. NCD slice reg0<15> was NOT guided. NCD slice reg0<23> was NOT guided. NCD slice reg0<31> was NOT guided. NCD slice data_out<0>_map1780 was NOT guided. NCD slice reg0<17> was NOT guided. NCD slice reg0<25> was NOT guided. NCD slice PLL/_n0040<1>_map1858 was NOT guided. NCD slice PLL/chipscope/trig_timer<23> was NOT guided. NCD slice reg0<19> was NOT guided. NCD slice reg0<27> was NOT guided. NCD slice PLL/x0<0> was NOT guided. NCD slice reg0<29> was NOT guided. NCD slice PLL/_n0053<2> was NOT guided. NCD slice PLL/ST_timing_rising was NOT guided. NCD slice regA<11> was NOT guided. NCD slice PLL/Mshift_F_ERR_Sh<49> was NOT guided. NCD slice PLL/_n0040<2>_map1881 was NOT guided. NCD slice PLL/_n0064 was NOT guided. NCD slice PLL/x0<2> was NOT guided. NCD slice data_out<21>_map994 was NOT guided. NCD slice PLL/_n0053<4> was NOT guided. NCD slice PLL/_n0075 was NOT guided. NCD slice regA<13> was NOT guided. NCD slice regA<21> was NOT guided. NCD slice PLL/PT_MSB_rising was NOT guided. NCD slice PLL/Mshift_F_ERR_Result<3>16/O was NOT guided. NCD slice PLL/x1<0> was NOT guided. NCD slice PLL/x0<4> was NOT guided. NCD slice PLL/_n0053<6> was NOT guided. NCD slice PLL/_n0054<2> was NOT guided. NCD slice data_out<5>_map1142 was NOT guided. NCD slice regA<15> was NOT guided. NCD slice regA<23> was NOT guided. NCD slice regA<31> was NOT guided. NCD slice PLL/_n0088 was NOT guided. NCD slice data_out<5>_map1136 was NOT guided. NCD slice PLL/x1<2> was NOT guided. NCD slice PLL/x0<6> was NOT guided. NCD slice PLL/_n0053<8> was NOT guided. NCD slice PLL/_n0054<4> was NOT guided. NCD slice reg2<11> was NOT guided. NCD slice data_out<25>_map943 was NOT guided. NCD slice regA<17> was NOT guided. NCD slice regA<25> was NOT guided. NCD slice PLL/_n0040<4>_map1905 was NOT guided. NCD slice PLL/y0<0> was NOT guided. NCD slice PLL/x1<4> was NOT guided. NCD slice PLL/x0<8> was NOT guided. NCD slice PLL/x2<0> was NOT guided. NCD slice PLL/_n0040<3>_map1893 was NOT guided. NCD slice reg2<13> was NOT guided. NCD slice reg2<21> was NOT guided. NCD slice PLL/_n0054<6> was NOT guided. NCD slice PLL/_n0055<2> was NOT guided. NCD slice regA<19> was NOT guided. NCD slice regA<27> was NOT guided. NCD slice data_out<29>_map800 was NOT guided. NCD slice PLL/y0<2> was NOT guided. NCD slice PLL/x1<6> was NOT guided. NCD slice PLL/x2<2> was NOT guided. NCD slice data_out<3>154_2 was NOT guided. NCD slice PLL/_n0054<8> was NOT guided. NCD slice PLL/_n0055<4> was NOT guided. NCD slice PLL/_n0056<0> was NOT guided. NCD slice reg2<15> was NOT guided. NCD slice reg2<23> was NOT guided. NCD slice reg2<31> was NOT guided. NCD slice regA<29> was NOT guided. NCD slice data_out<29>_map812 was NOT guided. NCD slice PLL/y0<4> was NOT guided. NCD slice PLL/y1<0> was NOT guided. NCD slice PLL/x1<8> was NOT guided. NCD slice PLL/x2<4> was NOT guided. NCD slice data_out<31>_map14 was NOT guided. NCD slice reg2<17> was NOT guided. NCD slice reg2<25> was NOT guided. NCD slice PLL/_n0056<2> was NOT guided. NCD slice PLL/_n0055<6> was NOT guided. NCD slice data_out<7>154_2 was NOT guided. NCD slice PLL/y0<6> was NOT guided. NCD slice PLL/y1<2> was NOT guided. NCD slice PLL/x2<6> was NOT guided. NCD slice PLL/_n0040<5>_map1917 was NOT guided. NCD slice reg2<19> was NOT guided. NCD slice reg2<27> was NOT guided. NCD slice reg3<11> was NOT guided. NCD slice PLL/_n0056<4> was NOT guided. NCD slice PLL/_n0055<8> was NOT guided. NCD slice data_out<10> was NOT guided. NCD slice data_out<6>_map1088 was NOT guided. NCD slice data_out<11> was NOT guided. NCD slice PLL/y0<8> was NOT guided. NCD slice PLL/y1<4> was NOT guided. NCD slice PLL/y2<0> was NOT guided. NCD slice PLL/x2<8> was NOT guided. NCD slice data_out<29>_map773 was NOT guided. NCD slice data_out<6>_map1099 was NOT guided. NCD slice PLL/_n0056<6> was NOT guided. NCD slice reg2<29> was NOT guided. NCD slice reg3<13> was NOT guided. NCD slice reg3<21> was NOT guided. NCD slice data_out<20> was NOT guided. NCD slice data_out<12> was NOT guided. NCD slice PLL/_n0040<6>_map1921 was NOT guided. NCD slice regC<11> was NOT guided. NCD slice reg0<0> was NOT guided. NCD slice data_out<21> was NOT guided. NCD slice data_out<13> was NOT guided. NCD slice PLL/y1<6> was NOT guided. NCD slice PLL/y2<2> was NOT guided. NCD slice reg0<1> was NOT guided. NCD slice reg3<15> was NOT guided. NCD slice reg3<23> was NOT guided. NCD slice reg3<31> was NOT guided. NCD slice PLL/_n0056<8> was NOT guided. NCD slice data_out<30> was NOT guided. NCD slice data_out<22> was NOT guided. NCD slice data_out<14> was NOT guided. NCD slice data_out<29>_map787 was NOT guided. NCD slice regC<13> was NOT guided. NCD slice regC<21> was NOT guided. NCD slice data_out<31> was NOT guided. NCD slice data_out<23> was NOT guided. NCD slice data_out<15> was NOT guided. NCD slice data_out<29>_map789 was NOT guided. NCD slice PLL/y1<8> was NOT guided. NCD slice PLL/y2<4> was NOT guided. NCD slice reg0<3> was NOT guided. NCD slice reg3<17> was NOT guided. NCD slice reg3<25> was NOT guided. NCD slice data_out<24> was NOT guided. NCD slice data_out<16> was NOT guided. NCD slice regC<15> was NOT guided. NCD slice regC<23> was NOT guided. NCD slice regC<31> was NOT guided. NCD slice data_out<25> was NOT guided. NCD slice data_out<17> was NOT guided. NCD slice PLL/y2<6> was NOT guided. NCD slice reg0<5> was NOT guided. NCD slice reg3<19> was NOT guided. NCD slice reg3<27> was NOT guided. NCD slice reg4<11> was NOT guided. NCD slice data_out<26> was NOT guided. NCD slice data_out<18> was NOT guided. NCD slice regC<17> was NOT guided. NCD slice regC<25> was NOT guided. NCD slice data_out<27> was NOT guided. NCD slice data_out<19> was NOT guided. NCD slice PLL/_n0040<7>_map1933 was NOT guided. NCD slice PLL/y2<8> was NOT guided. NCD slice reg0<7> was NOT guided. NCD slice reg3<29> was NOT guided. NCD slice reg4<13> was NOT guided. NCD slice reg4<21> was NOT guided. NCD slice data_out<28> was NOT guided. NCD slice regC<19> was NOT guided. NCD slice regC<27> was NOT guided. NCD slice regD<11> was NOT guided. Guided Mapping Summary Info --------------------------- Total number of slices in guide NCDs = 2024. Total number of guided slices = 1303. 64.4 % of guide NCD slices were guided. Section 9 - Area Group Summary ------------------------------ No area groups were found in this design. Section 10 - Modular Design Summary ----------------------------------- Modular Design not used for this design. Section 11 - Timing Report -------------------------- This design was not run using timing mode. Section 12 - Configuration String Details -------------------------- Use the "-detail" map option to print out Configuration Strings Section 13 - Additional Device Resource Counts ---------------------------------------------- Number of JTAG Gates for IOBs = 252 Number of Equivalent Gates for Design = 6,215,263 Number of RPM Macros = 24 Number of Hard Macros = 0 GT10 = 0 GT = 0 CAPTUREs = 0 BSCANs = 1 STARTUPs = 0 PCILOGICs = 0 DCMs = 0 GCLKs = 3 ICAPs = 0 18X18 Multipliers = 0 Block RAMs = 94 TBUFs = 0 JTAGPPCs = 0 CLK_Ps = 0 CLK_Ns = 0 GTOPADs = 0 GTIPADs = 0 PPC405s = 0 Total Registers (Flops & Latches in Slices & IOBs) not driven by LUTs = 1723 IOB Dual-Rate Flops not driven by LUTs = 0 IOB Dual-Rate Flops = 0 IOB Slave Pads = 2 IOB Master Pads = 2 IOB Latches not driven by LUTs = 0 IOB Latches = 0 IOB Flip Flops not driven by LUTs = 94 IOB Flip Flops = 94 Unbonded IOBs = 0 Bonded IOBs = 252 ORCYs = 0 XORs = 882 CARRY_INITs = 515 CARRY_SKIPs = 0 CARRY_MUXes = 958 Total Shift Registers = 250 Static Shift Registers = 148 Dynamic Shift Registers = 102 16x1 ROMs = 0 16x1 RAMs = 0 32x1 RAMs = 0 Dual Port RAMs = 0 MUXFs = 252 MULT_ANDs = 9 4 input LUTs used as Route-Thrus = 175 4 input LUTs = 2231 Slice Latches not driven by LUTs = 0 Slice Latches = 0 Slice Flip Flops not driven by LUTs = 1629 Slice Flip Flops = 2289 Slices = 2049 F6 Muxes = 47 F5 Muxes = 189 F8 Muxes = 5 F7 Muxes = 11 Xilinx Core null = 5 Xilinx Core blkmemdp_v6_2, Coregen 8.1i = 6 Number of LUT signals with 4 loads = 19 Number of LUT signals with 3 loads = 11 Number of LUT signals with 2 loads = 833 Number of LUT signals with 1 load = 1293 NGM Average fanout of LUT = 2.54 NGM Maximum fanout of LUT = 454 NGM Average fanin for LUT = 2.7934 Number of LUT symbols = 2231