Release 8.1i - xst I.24 Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved. --> Parameter TMPDIR set to ./xst/projnav.tmp CPU : 0.00 / 0.28 s | Elapsed : 0.00 / 1.00 s --> Parameter xsthdpdir set to ./xst CPU : 0.00 / 0.28 s | Elapsed : 0.00 / 1.00 s --> Reading design: Custom_libera_top.prj TABLE OF CONTENTS 1) Synthesis Options Summary 2) HDL Compilation 3) HDL Analysis 4) HDL Synthesis 4.1) HDL Synthesis Report 5) Advanced HDL Synthesis 5.1) Advanced HDL Synthesis Report 6) Low Level Synthesis 7) Final Report 7.1) Device utilization summary 7.2) TIMING REPORT ========================================================================= * Synthesis Options Summary * ========================================================================= ---- Source Parameters Input File Name : "Custom_libera_top.prj" Input Format : mixed Ignore Synthesis Constraint File : NO ---- Target Parameters Output File Name : "Custom_libera_top" Output Format : NGC Target Device : xc2vp30-6-ff1152 ---- Source Options Top Module Name : Custom_libera_top Automatic FSM Extraction : YES FSM Encoding Algorithm : Auto FSM Style : lut RAM Extraction : Yes RAM Style : Auto ROM Extraction : Yes Mux Style : Auto Decoder Extraction : YES Priority Encoder Extraction : YES Shift Register Extraction : YES Logical Shifter Extraction : YES XOR Collapsing : YES ROM Style : Auto Mux Extraction : YES Resource Sharing : YES Multiplier Style : auto Automatic Register Balancing : No ---- Target Options Add IO Buffers : YES Global Maximum Fanout : 500 Add Generic Clock Buffer(BUFG) : 16 Register Duplication : YES Slice Packing : YES Pack IO Registers into IOBs : auto Equivalent register Removal : YES ---- General Options Optimization Goal : Speed Optimization Effort : 2 Keep Hierarchy : NO RTL Output : Yes Global Optimization : AllClockNets Write Timing Constraints : NO Hierarchy Separator : / Bus Delimiter : <> Case Specifier : maintain Slice Utilization Ratio : 100 Slice Utilization Ratio Delta : 5 ---- Other Options lso : Custom_libera_top.lso Read Cores : YES cross_clock_analysis : NO verilog2001 : YES safe_implementation : No Optimize Instantiated Primitives : NO tristate2logic : Yes use_clock_enable : Yes use_sync_set : Yes use_sync_reset : Yes ========================================================================= ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file "C:/DESIGNS/FPGA/Custom_Libera/chipscope_analyser.vhd" in Library work. Architecture behavioral of Entity chipscope_analyser is up to date. Compiling vhdl file "C:/DESIGNS/FPGA/Custom_Libera/pll3.vhd" in Library work. Entity compiled. Entity (Architecture ) compiled. Compiling vhdl file "C:/DESIGNS/FPGA/Custom_Libera/Custom_libera_top.vhd" in Library work. Architecture behavioral of Entity custom_libera_top is up to date. Compiling verilog file "phasetable.v" in library work Compiling verilog file "dpram8x32.v" in library work Module compiled Compiling verilog file "dpram8192x32.v" in library work Module compiled Compiling verilog file "dpram32x32.v" in library work Module compiled Module compiled No errors in compilation Analysis of file <"Custom_libera_top.prj"> succeeded. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity (Architecture ). WARNING:Xst:753 - "C:/DESIGNS/FPGA/Custom_Libera/Custom_libera_top.vhd" line 550: Unconnected output port 'LO_sel' of component 'PLL3'. WARNING:Xst:753 - "C:/DESIGNS/FPGA/Custom_Libera/Custom_libera_top.vhd" line 550: Unconnected output port 'INJ_cnt_o' of component 'PLL3'. WARNING:Xst:753 - "C:/DESIGNS/FPGA/Custom_Libera/Custom_libera_top.vhd" line 550: Unconnected output port 'SDRAM_ADDR_OUT' of component 'PLL3'. WARNING:Xst:753 - "C:/DESIGNS/FPGA/Custom_Libera/Custom_libera_top.vhd" line 550: Unconnected output port 'write_SDRAM' of component 'PLL3'. WARNING:Xst:753 - "C:/DESIGNS/FPGA/Custom_Libera/Custom_libera_top.vhd" line 550: Unconnected output port 'result_0' of component 'PLL3'. WARNING:Xst:753 - "C:/DESIGNS/FPGA/Custom_Libera/Custom_libera_top.vhd" line 550: Unconnected output port 'result_1' of component 'PLL3'. WARNING:Xst:753 - "C:/DESIGNS/FPGA/Custom_Libera/Custom_libera_top.vhd" line 550: Unconnected output port 'result_2' of component 'PLL3'. Entity analyzed. Unit generated. Analyzing Entity (Architecture ). WARNING:Xst:753 - "C:/DESIGNS/FPGA/Custom_Libera/pll3.vhd" line 1120: Unconnected output port 'control_port_o' of component 'chipscope_analyser'. Entity analyzed. Unit generated. Analyzing module . WARNING:Xst:37 - Unknown property "fpga_dont_touch". Analyzing module . WARNING:Xst:37 - Unknown property "fpga_dont_touch". Analyzing module . WARNING:Xst:37 - Unknown property "fpga_dont_touch". Analyzing module . WARNING:Xst:37 - Unknown property "fpga_dont_touch". Analyzing Entity (Architecture ). WARNING:Xst:766 - "C:/DESIGNS/FPGA/Custom_Libera/chipscope_analyser.vhd" line 161: Generating a Black Box for component . WARNING:Xst:766 - "C:/DESIGNS/FPGA/Custom_Libera/chipscope_analyser.vhd" line 175: Generating a Black Box for component . WARNING:Xst:766 - "C:/DESIGNS/FPGA/Custom_Libera/chipscope_analyser.vhd" line 191: Generating a Black Box for component . WARNING:Xst:766 - "C:/DESIGNS/FPGA/Custom_Libera/chipscope_analyser.vhd" line 210: Generating a Black Box for component . WARNING:Xst:766 - "C:/DESIGNS/FPGA/Custom_Libera/chipscope_analyser.vhd" line 227: Generating a Black Box for component . Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is "C:/DESIGNS/FPGA/Custom_Libera/chipscope_analyser.vhd". WARNING:Xst:646 - Signal > is assigned but never used. Found 1-bit register for signal . Found 5-bit register for signal . Found 24-bit down counter for signal . Found 1-bit register for signal . Found 4-bit register for signal . Found 4-bit register for signal . Found 4-bit register for signal . Found 24-bit down counter for signal . Found 1-bit register for signal . Summary: inferred 2 Counter(s). inferred 20 D-type flip-flop(s). Unit synthesized. Synthesizing Unit . Related source file is "C:/DESIGNS/FPGA/Custom_Libera/pll3.vhd". WARNING:Xst:1305 - Output is never assigned. Tied to value 0. WARNING:Xst:647 - Input is never used. WARNING:Xst:647 - Input is never used. WARNING:Xst:647 - Input is never used. WARNING:Xst:647 - Input is never used. WARNING:Xst:1305 - Output is never assigned. Tied to value 00000000000000000000000000000000. WARNING:Xst:647 - Input is never used. WARNING:Xst:647 - Input is never used. WARNING:Xst:1305 - Output is never assigned. Tied to value 0000. WARNING:Xst:1305 - Output is never assigned. Tied to value 0. WARNING:Xst:1305 - Output is never assigned. Tied to value 0000000000000. WARNING:Xst:647 - Input is never used. WARNING:Xst:1305 - Output is never assigned. Tied to value 0. WARNING:Xst:647 - Input is never used. WARNING:Xst:1305 - Output is never assigned. Tied to value 0. WARNING:Xst:647 - Input is never used. WARNING:Xst:647 - Input is never used. WARNING:Xst:1780 - Signal is never used or assigned. WARNING:Xst:646 - Signal is assigned but never used. WARNING:Xst:646 - Signal is assigned but never used. WARNING:Xst:646 - Signal is assigned but never used. WARNING:Xst:646 - Signal is assigned but never used. WARNING:Xst:646 - Signal is assigned but never used. WARNING:Xst:646 - Signal is assigned but never used. WARNING:Xst:646 - Signal is assigned but never used. WARNING:Xst:646 - Signal is assigned but never used. WARNING:Xst:1780 - Signal is never used or assigned. WARNING:Xst:646 - Signal is assigned but never used. WARNING:Xst:646 - Signal is assigned but never used. WARNING:Xst:1780 - Signal is never used or assigned. WARNING:Xst:653 - Signal is used but never assigned. Tied to value 11110100001001000. WARNING:Xst:653 - Signal is used but never assigned. Tied to value 00000000000000000000000000000000. WARNING:Xst:1780 - Signal is never used or assigned. WARNING:Xst:1780 - Signal is never used or assigned. WARNING:Xst:646 - Signal is assigned but never used. WARNING:Xst:653 - Signal is used but never assigned. Tied to value 0. WARNING:Xst:646 - Signal > is assigned but never used. WARNING:Xst:653 - Signal is used but never assigned. Tied to value 0. WARNING:Xst:1780 - Signal is never used or assigned. WARNING:Xst:646 - Signal is assigned but never used. WARNING:Xst:1780 - Signal is never used or assigned. WARNING:Xst:646 - Signal > is assigned but never used. WARNING:Xst:653 - Signal is used but never assigned. Tied to value 000. WARNING:Xst:653 - Signal is used but never assigned. Tied to value 0. WARNING:Xst:653 - Signal is used but never assigned. Tied to value 0. WARNING:Xst:653 - Signal is used but never assigned. Tied to value 0. INFO:Xst:1799 - State stop_acq is never reached in FSM . Found finite state machine for signal . ----------------------------------------------------------------------- | States | 4 | | Transitions | 6 | | Inputs | 1 | | Outputs | 2 | | Clock | clk (rising_edge) | | Reset | init (positive) | | Reset type | asynchronous | | Reset State | idle | | Power Up State | idle | | Encoding | automatic | | Implementation | LUT | ----------------------------------------------------------------------- Found finite state machine for signal . ----------------------------------------------------------------------- | States | 4 | | Transitions | 7 | | Inputs | 3 | | Outputs | 2 | | Clock | clk (rising_edge) | | Reset | init (positive) | | Reset type | asynchronous | | Reset State | idle_synch | | Power Up State | idle_synch | | Encoding | automatic | | Implementation | LUT | ----------------------------------------------------------------------- Found 8x2-bit ROM for signal <$n0055>. Found 26-bit register for signal . Found 13-bit register for signal . Found 26-bit register for signal . Found 5-bit register for signal . Found 3-bit register for signal . Found 3-bit register for signal . Found 9-bit adder for signal <$n0001> created at line 813. Found 24-bit subtractor for signal <$n0027> created at line 869. Found 24-bit subtractor for signal <$n0028> created at line 870. Found 24-bit subtractor for signal <$n0029> created at line 873. Found 24-bit subtractor for signal <$n0030> created at line 874. Found 24-bit subtractor for signal <$n0031> created at line 877. Found 32-bit 4-to-1 multiplexer for signal <$n0033>. Found 24-bit subtractor for signal <$n0034> created at line 871. Found 24-bit subtractor for signal <$n0035> created at line 875. Found 24-bit subtractor for signal <$n0037> created at line 1043. Found 24-bit subtractor for signal <$n0038> created at line 1044. Found 24-bit subtractor for signal <$n0039> created at line 1045. Found 24-bit adder for signal <$n0040> created at line 1049. Found 24-bit adder for signal <$n0041> created at line 1050. Found 24-bit adder for signal <$n0042> created at line 1051. Found 24-bit adder for signal <$n0046> created at line 869. Found 24-bit adder for signal <$n0047> created at line 870. Found 24-bit adder for signal <$n0048> created at line 874. Found 32-bit subtractor for signal <$n0049> created at line 802. Found 32-bit comparator greater for signal <$n0054> created at line 790. Found 32-bit comparator greatequal for signal <$n0057> created at line 792. Found 32-bit comparator lessequal for signal <$n0058> created at line 790. Found 24-bit up accumulator for signal . Found 24-bit up accumulator for signal . Found 24-bit up accumulator for signal . Found 24-bit up accumulator for signal . Found 24-bit up accumulator for signal . Found 24-bit up accumulator for signal . Found 13-bit up counter for signal . Found 17-bit down counter for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 32-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 32-bit up accumulator for signal . Found 24-bit up accumulator for signal . Found 24-bit up accumulator for signal . Found 24-bit up accumulator for signal . Found 24-bit shifter arithmetic right for signal . Found 2-bit register for signal . Found 1-bit register for signal . Found 24-bit register for signal . Found 1-bit register for signal . Found 5-bit up counter for signal . Found 1-bit register for signal . Found 2-bit register for signal . Found 1-bit register for signal . Found 3-bit up counter for signal . Found 3-bit up counter for signal . Found 2-bit register for signal . Found 1-bit register for signal . Found 8-bit down counter for signal . Found 14-bit adder for signal . Found 24-bit register for signal . Found 24-bit register for signal . Found 24-bit register for signal . Found 24-bit register for signal . Found 24-bit register for signal . Found 4-bit up counter for signal . Found 2-bit register for signal . Found 1-bit register for signal . Found 24-bit register for signal . Found 24-bit register for signal . Found 24-bit register for signal . Found 24-bit register for signal . Found 24-bit register for signal . Found 26-bit up counter for signal . Found 2-bit register for signal . Found 3-bit up counter for signal . Found 1-bit register for signal . Found 24-bit register for signal . Found 24-bit register for signal . Found 24-bit register for signal . Found 24-bit register for signal . Found 24-bit register for signal . Found 24-bit register for signal . Summary: inferred 2 Finite State Machine(s). inferred 1 ROM(s). inferred 9 Counter(s). inferred 10 Accumulator(s). inferred 506 D-type flip-flop(s). inferred 19 Adder/Subtractor(s). inferred 3 Comparator(s). inferred 32 Multiplexer(s). inferred 1 Combinational logic shifter(s). Unit synthesized. Synthesizing Unit . Related source file is "C:/DESIGNS/FPGA/Custom_Libera/Custom_libera_top.vhd". WARNING:Xst:1778 - Inout > is assigned but never used. WARNING:Xst:1779 - Inout > is used but is never assigned. WARNING:Xst:1778 - Inout > is assigned but never used. WARNING:Xst:1778 - Inout is assigned but never used. WARNING:Xst:1778 - Inout is assigned but never used. WARNING:Xst:647 - Input is never used. WARNING:Xst:1778 - Inout is assigned but never used. WARNING:Xst:647 - Input is never used. WARNING:Xst:1778 - Inout is assigned but never used. WARNING:Xst:1778 - Inout is assigned but never used. WARNING:Xst:1778 - Inout is assigned but never used. WARNING:Xst:1778 - Inout is assigned but never used. WARNING:Xst:647 - Input is never used. WARNING:Xst:1778 - Inout is assigned but never used. WARNING:Xst:647 - Input is never used. WARNING:Xst:1778 - Inout is assigned but never used. WARNING:Xst:1778 - Inout is assigned but never used. WARNING:Xst:1780 - Signal is never used or assigned. WARNING:Xst:1780 - Signal is never used or assigned. WARNING:Xst:1780 - Signal is never used or assigned. WARNING:Xst:646 - Signal is assigned but never used. WARNING:Xst:653 - Signal is used but never assigned. Tied to value 00000000000000000000000000000000. WARNING:Xst:653 - Signal is used but never assigned. Tied to value 0. WARNING:Xst:646 - Signal is assigned but never used. WARNING:Xst:653 - Signal > is used but never assigned. Tied to value 0000000000000000000000000000000. WARNING:Xst:646 - Signal is assigned but never used. WARNING:Xst:646 - Signal is assigned but never used. WARNING:Xst:1780 - Signal is never used or assigned. WARNING:Xst:1780 - Signal is never used or assigned. WARNING:Xst:646 - Signal is assigned but never used. WARNING:Xst:1780 - Signal is never used or assigned. WARNING:Xst:1780 - Signal is never used or assigned. WARNING:Xst:646 - Signal is assigned but never used. WARNING:Xst:646 - Signal is assigned but never used. WARNING:Xst:646 - Signal is assigned but never used. WARNING:Xst:1780 - Signal is never used or assigned. WARNING:Xst:1780 - Signal is never used or assigned. WARNING:Xst:1780 - Signal is never used or assigned. WARNING:Xst:1780 - Signal is never used or assigned. Found 32-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 16-bit tristate buffer for signal . Found 16-bit tristate buffer for signal . Found 4-bit tristate buffer for signal >. Found 8-bit tristate buffer for signal >. Found 14-bit register for signal . Found 14-bit register for signal . Found 14-bit register for signal . Found 32-bit 4-to-1 multiplexer for signal . Found 4-bit register for signal . Found 32-bit register for signal . Found 32-bit register for signal . Found 32-bit register for signal . Found 32-bit register for signal . Found 32-bit register for signal . Found 32-bit register for signal . Found 32-bit register for signal . Found 32-bit register for signal . Found 32-bit register for signal . Found 32-bit register for signal . Found 32-bit register for signal . Summary: inferred 398 D-type flip-flop(s). inferred 32 Multiplexer(s). inferred 84 Tristate(s). Unit synthesized. INFO:Xst:2182 - Always blocking tristate > in unit is removed. INFO:Xst:2182 - Always blocking tristate > in unit is removed. INFO:Xst:2182 - Always blocking tristate > in unit is removed. INFO:Xst:2182 - Always blocking tristate > in unit is removed. INFO:Xst:2182 - Always blocking tristate > in unit is removed. INFO:Xst:2182 - Always blocking tristate > in unit is removed. INFO:Xst:2182 - Always blocking tristate > in unit is removed. INFO:Xst:2182 - Always blocking tristate > in unit is removed. INFO:Xst:2182 - Always blocking tristate > in unit is removed. INFO:Xst:2182 - Always blocking tristate > in unit is removed. INFO:Xst:2182 - Always blocking tristate > in unit is removed. INFO:Xst:2182 - Always blocking tristate > in unit is removed. INFO:Xst:2182 - Always blocking tristate in unit is removed. INFO:Xst:2182 - Always blocking tristate in unit is removed. INFO:Xst:2182 - Always blocking tristate > in unit is removed. INFO:Xst:2182 - Always blocking tristate > in unit is removed. INFO:Xst:2182 - Always blocking tristate > in unit is removed. INFO:Xst:2182 - Always blocking tristate > in unit is removed. INFO:Xst:2182 - Always blocking tristate > in unit is removed. INFO:Xst:2182 - Always blocking tristate > in unit is removed. INFO:Xst:2182 - Always blocking tristate > in unit is removed. INFO:Xst:2182 - Always blocking tristate > in unit is removed. INFO:Xst:2182 - Always blocking tristate > in unit is removed. INFO:Xst:2182 - Always blocking tristate > in unit is removed. INFO:Xst:2182 - Always blocking tristate > in unit is removed. INFO:Xst:2182 - Always blocking tristate > in unit is removed. INFO:Xst:2182 - Always blocking tristate > in unit is removed. INFO:Xst:2182 - Always blocking tristate > in unit is removed. INFO:Xst:2182 - Always blocking tristate > in unit is removed. INFO:Xst:2182 - Always blocking tristate > in unit is removed. INFO:Xst:2182 - Always blocking tristate in unit is removed. INFO:Xst:2182 - Always blocking tristate in unit is removed. INFO:Xst:2182 - Always blocking tristate in unit is removed. INFO:Xst:2182 - Always blocking tristate in unit is removed. INFO:Xst:2182 - Always blocking tristate > in unit is removed. INFO:Xst:2182 - Always blocking tristate > in unit is removed. INFO:Xst:2182 - Always blocking tristate > in unit is removed. INFO:Xst:2182 - Always blocking tristate > in unit is removed. INFO:Xst:2182 - Always blocking tristate > in unit is removed. INFO:Xst:2182 - Always blocking tristate > in unit is removed. INFO:Xst:2182 - Always blocking tristate > in unit is removed. INFO:Xst:2182 - Always blocking tristate > in unit is removed. INFO:Xst:2182 - Always blocking tristate > in unit is removed. INFO:Xst:2182 - Always blocking tristate > in unit is removed. INFO:Xst:2182 - Always blocking tristate > in unit is removed. INFO:Xst:2182 - Always blocking tristate > in unit is removed. INFO:Xst:2182 - Always blocking tristate > in unit is removed. INFO:Xst:2182 - Always blocking tristate > in unit is removed. INFO:Xst:2182 - Always blocking tristate > in unit is removed. INFO:Xst:2182 - Always blocking tristate > in unit is removed. INFO:Xst:2182 - Always blocking tristate in unit is removed. INFO:Xst:2182 - Always blocking tristate in unit is removed. ========================================================================= HDL Synthesis Report Macro Statistics # ROMs : 1 8x2-bit ROM : 1 # Adders/Subtractors : 19 14-bit adder : 1 24-bit adder : 6 24-bit subtractor : 10 32-bit subtractor : 1 9-bit adder : 1 # Counters : 11 13-bit up counter : 1 17-bit down counter : 1 24-bit down counter : 2 26-bit up counter : 1 3-bit up counter : 3 4-bit up counter : 1 5-bit up counter : 1 8-bit down counter : 1 # Accumulators : 10 24-bit up accumulator : 9 32-bit up accumulator : 1 # Registers : 78 1-bit register : 38 13-bit register : 1 14-bit register : 3 24-bit register : 17 26-bit register : 2 3-bit register : 2 32-bit register : 12 4-bit register : 2 5-bit register : 1 # Comparators : 3 32-bit comparator greatequal : 1 32-bit comparator greater : 1 32-bit comparator lessequal : 1 # Multiplexers : 2 32-bit 4-to-1 multiplexer : 2 # Logic shifters : 1 24-bit shifter arithmetic right : 1 # Tristates : 1 32-bit tristate buffer : 1 ========================================================================= ========================================================================= * Advanced HDL Synthesis * ========================================================================= Analyzing FSM for best encoding. Optimizing FSM on signal with gray encoding. ------------------------ State | Encoding ------------------------ idle_synch | 00 wait_frev | 01 wait_beam | 11 start_acq | 10 stop_acq | unreached ------------------------ Analyzing FSM for best encoding. Optimizing FSM on signal with gray encoding. ----------------------- State | Encoding ----------------------- idle | 00 integrate | 01 ready | 11 reset_acc | 10 ----------------------- Reading module "icon.ngo" ( "icon.ngo" unchanged since last run )... Reading module "vio_control.ngo" ( "vio_control.ngo" unchanged since last run )... Reading module "vio.ngo" ( "vio.ngo" unchanged since last run )... Reading module "ila_6CH.ngo" ( "ila_6CH.ngo" unchanged since last run )... Reading module "ila_2CH.ngo" ( "ila_2CH.ngo" unchanged since last run )... Reading module "dpram8192x32.ngo" ( "dpram8192x32.ngo" unchanged since last run )... Reading module "dpram8x32.ngo" ( "dpram8x32.ngo" unchanged since last run )... Reading module "dpram32x32.ngo" ( "dpram32x32.ngo" unchanged since last run )... Reading module "phasetable.ngo" ( "phasetable.ngo" unchanged since last run )... WARNING:Xst:1474 - Core was not loaded for as one or more ports did not line up with component declaration. Declared output port > was not found in the core. Please make sure that component declaration ports are consistent with the core ports including direction and bus-naming conventions. WARNING:Xst:1474 - Core was not loaded for as one or more ports did not line up with component declaration. Declared input port > was not found in the core. Please make sure that component declaration ports are consistent with the core ports including direction and bus-naming conventions. WARNING:Xst:1474 - Core was not loaded for as one or more ports did not line up with component declaration. Declared input port > was not found in the core. Please make sure that component declaration ports are consistent with the core ports including direction and bus-naming conventions. WARNING:Xst:1474 - Core was not loaded for as one or more ports did not line up with component declaration. Declared input port > was not found in the core. Please make sure that component declaration ports are consistent with the core ports including direction and bus-naming conventions. WARNING:Xst:1474 - Core was not loaded for as one or more ports did not line up with component declaration. Declared input port > was not found in the core. Please make sure that component declaration ports are consistent with the core ports including direction and bus-naming conventions. Loading core for timing and area information for instance . Loading core for timing and area information for instance . Loading core for timing and area information for instance . Loading core for timing and area information for instance . Loading core for timing and area information for instance . Loading core for timing and area information for instance . Synthesizing (advanced) Unit . INFO:Xst:2387 - HDL ADVISOR - A 4-bit shift register was found for signal > and currently occupies 4 logic cells (2 slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally. Unit synthesized (advanced). WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block