//! **************************************************************************
// Written by: Map I.24 on Thu Nov 16 10:14:21 2006
//! **************************************************************************

SCHEMATIC START;
COMP "ddr2high_ldqs_pad_io" LOCATE = SITE "P9" LEVEL 1;
COMP "ddr2low_bank_pad_o<0>" LOCATE = SITE "G3" LEVEL 1;
COMP "ddr2low_bank_pad_o<1>" LOCATE = SITE "G1" LEVEL 1;
COMP "ddr2high_udqsn_pad_io" LOCATE = SITE "U5" LEVEL 1;
COMP "ddr2high_odt_pad_o" LOCATE = SITE "P8" LEVEL 1;
COMP "ADC_RESET_o" LOCATE = SITE "P28" LEVEL 1;
COMP "ddr2low_cke_pad_o" LOCATE = SITE "H2" LEVEL 1;
COMP "spi_cs_adc1_pad_o" LOCATE = SITE "P34" LEVEL 1;
COMP "spi_func_pad_o" LOCATE = SITE "T26" LEVEL 1;
COMP "spi_cs_adc2_pad_o" LOCATE = SITE "P33" LEVEL 1;
COMP "bp_led0_pad_o" LOCATE = SITE "K28" LEVEL 1;
COMP "spi_cs_adc3_pad_o" LOCATE = SITE "R34" LEVEL 1;
COMP "bp_led1_pad_o" LOCATE = SITE "H31" LEVEL 1;
COMP "spi_cs_adc4_pad_o" LOCATE = SITE "N31" LEVEL 1;
COMP "bp_led2_pad_o" LOCATE = SITE "H32" LEVEL 1;
COMP "ddr2low_clk_pad_o" LOCATE = SITE "H5" LEVEL 1;
COMP "ddr2low_casn_pad_o" LOCATE = SITE "M10" LEVEL 1;
COMP "ddr2low_addr_pad_o<10>" LOCATE = SITE "F4" LEVEL 1;
COMP "ddr2low_addr_pad_o<11>" LOCATE = SITE "J6" LEVEL 1;
COMP "ddr2low_addr_pad_o<12>" LOCATE = SITE "E4" LEVEL 1;
COMP "ddr2high_udm_pad_o" LOCATE = SITE "N7" LEVEL 1;
COMP "vcxo" LOCATE = SITE "M34" LEVEL 1;
COMP "ddr2high_ldqsn_pad_io" LOCATE = SITE "P10" LEVEL 1;
COMP "ddr2high_wen_pad_o" LOCATE = SITE "T6" LEVEL 1;
COMP "ddr2high_rasn_pad_o" LOCATE = SITE "N2" LEVEL 1;
COMP "ddr2high_addr_pad_o<0>" LOCATE = SITE "P7" LEVEL 1;
COMP "ddr2high_addr_pad_o<1>" LOCATE = SITE "P1" LEVEL 1;
COMP "ddr2high_addr_pad_o<2>" LOCATE = SITE "R6" LEVEL 1;
COMP "ddr2high_addr_pad_o<3>" LOCATE = SITE "P5" LEVEL 1;
COMP "ddr2high_addr_pad_o<4>" LOCATE = SITE "U11" LEVEL 1;
COMP "ddr2high_addr_pad_o<5>" LOCATE = SITE "T9" LEVEL 1;
COMP "ddr2high_addr_pad_o<6>" LOCATE = SITE "L9" LEVEL 1;
COMP "ddr2high_addr_pad_o<7>" LOCATE = SITE "U8" LEVEL 1;
COMP "ddr2high_addr_pad_o<8>" LOCATE = SITE "N9" LEVEL 1;
COMP "ddr2low_ldm_pad_o" LOCATE = SITE "N1" LEVEL 1;
COMP "ddr2high_addr_pad_o<9>" LOCATE = SITE "U9" LEVEL 1;
COMP "adc_d_dat_pad_i<0>" LOCATE = SITE "R31" LEVEL 1;
COMP "adc_d_dat_pad_i<1>" LOCATE = SITE "T32" LEVEL 1;
COMP "adc_d_dat_pad_i<2>" LOCATE = SITE "T31" LEVEL 1;
COMP "adc_d_dat_pad_i<3>" LOCATE = SITE "N25" LEVEL 1;
COMP "adc_d_dat_pad_i<4>" LOCATE = SITE "P25" LEVEL 1;
COMP "adc_d_dat_pad_i<5>" LOCATE = SITE "T28" LEVEL 1;
COMP "adc_d_dat_pad_i<6>" LOCATE = SITE "T27" LEVEL 1;
COMP "adc_d_dat_pad_i<7>" LOCATE = SITE "U32" LEVEL 1;
COMP "adc_d_dat_pad_i<8>" LOCATE = SITE "U31" LEVEL 1;
COMP "adc_d_dat_pad_i<9>" LOCATE = SITE "N34" LEVEL 1;
COMP "ddr2low_udqs_pad_io" LOCATE = SITE "H4" LEVEL 1;
COMP "adc_b_dat_pad_i<10>" LOCATE = SITE "K31" LEVEL 1;
COMP "adc_b_dat_pad_i<11>" LOCATE = SITE "N29" LEVEL 1;
COMP "adc_b_dat_pad_i<12>" LOCATE = SITE "N30" LEVEL 1;
COMP "adc_b_dat_pad_i<13>" LOCATE = SITE "M25" LEVEL 1;
COMP "ddr2low_clkn_pad_o" LOCATE = SITE "H6" LEVEL 1;
COMP "ddr2high_data_pad_io<0>" LOCATE = SITE "M4" LEVEL 1;
COMP "ddr2high_data_pad_io<1>" LOCATE = SITE "P3" LEVEL 1;
COMP "ddr2high_data_pad_io<2>" LOCATE = SITE "M6" LEVEL 1;
COMP "ddr2high_data_pad_io<3>" LOCATE = SITE "P2" LEVEL 1;
COMP "ddr2high_data_pad_io<4>" LOCATE = SITE "U6" LEVEL 1;
COMP "ddr2high_data_pad_io<5>" LOCATE = SITE "U10" LEVEL 1;
COMP "ddr2high_data_pad_io<6>" LOCATE = SITE "R1" LEVEL 1;
COMP "ddr2high_data_pad_io<7>" LOCATE = SITE "N5" LEVEL 1;
COMP "ddr2high_data_pad_io<8>" LOCATE = SITE "T4" LEVEL 1;
COMP "ddr2high_data_pad_io<9>" LOCATE = SITE "U3" LEVEL 1;
COMP "clk125_npad_i" LOCATE = SITE "AK17" LEVEL 1;
COMP "clk125_ppad_i" LOCATE = SITE "AL17" LEVEL 1;
COMP "ddr2low_ldqs_pad_io" LOCATE = SITE "N10" LEVEL 1;
COMP "ddr2low_odt_pad_o" LOCATE = SITE "J7" LEVEL 1;
COMP "DIO<1>" LOCATE = SITE "AB4" LEVEL 1;
COMP "DIO<2>" LOCATE = SITE "AJ1" LEVEL 1;
COMP "DIO<3>" LOCATE = SITE "AK1" LEVEL 1;
COMP "DIO<4>" LOCATE = SITE "W9" LEVEL 1;
COMP "DIO<5>" LOCATE = SITE "AF8" LEVEL 1;
COMP "DIO<6>" LOCATE = SITE "AG5" LEVEL 1;
COMP "DIO<7>" LOCATE = SITE "AB3" LEVEL 1;
COMP "DIO<8>" LOCATE = SITE "AG7" LEVEL 1;
COMP "DIO<9>" LOCATE = SITE "AL2" LEVEL 1;
COMP "DIR<0>" LOCATE = SITE "V6" LEVEL 1;
COMP "DIR<1>" LOCATE = SITE "Y2" LEVEL 1;
COMP "DIR<2>" LOCATE = SITE "W4" LEVEL 1;
COMP "DIR<3>" LOCATE = SITE "V10" LEVEL 1;
COMP "DIR<4>" LOCATE = SITE "V9" LEVEL 1;
COMP "DIR<5>" LOCATE = SITE "W3" LEVEL 1;
COMP "sbc_csn_pad_i" LOCATE = SITE "AL30" LEVEL 1;
COMP "adc_c_dat_pad_i<0>" LOCATE = SITE "R29" LEVEL 1;
COMP "adc_c_dat_pad_i<1>" LOCATE = SITE "N28" LEVEL 1;
COMP "adc_c_dat_pad_i<2>" LOCATE = SITE "N27" LEVEL 1;
COMP "adc_c_dat_pad_i<3>" LOCATE = SITE "R32" LEVEL 1;
COMP "adc_c_dat_pad_i<4>" LOCATE = SITE "N26" LEVEL 1;
COMP "adc_c_dat_pad_i<5>" LOCATE = SITE "U30" LEVEL 1;
COMP "adc_c_dat_pad_i<6>" LOCATE = SITE "U28" LEVEL 1;
COMP "adc_c_dat_pad_i<7>" LOCATE = SITE "U24" LEVEL 1;
COMP "adc_c_dat_pad_i<8>" LOCATE = SITE "U27" LEVEL 1;
COMP "adc_c_dat_pad_i<9>" LOCATE = SITE "P30" LEVEL 1;
COMP "ddr2high_casn_pad_o" LOCATE = SITE "T8" LEVEL 1;
COMP "ddr2low_udm_pad_o" LOCATE = SITE "L3" LEVEL 1;
COMP "sbc_dat_pad_io<10>" LOCATE = SITE "AG22" LEVEL 1;
COMP "sbc_dat_pad_io<11>" LOCATE = SITE "AH22" LEVEL 1;
COMP "sbc_dat_pad_io<20>" LOCATE = SITE "AE20" LEVEL 1;
COMP "sbc_dat_pad_io<12>" LOCATE = SITE "AJ24" LEVEL 1;
COMP "sbc_dat_pad_io<21>" LOCATE = SITE "AF20" LEVEL 1;
COMP "sbc_dat_pad_io<13>" LOCATE = SITE "AK24" LEVEL 1;
COMP "sbc_dat_pad_io<30>" LOCATE = SITE "AF19" LEVEL 1;
COMP "sbc_dat_pad_io<22>" LOCATE = SITE "AG21" LEVEL 1;
COMP "sbc_dat_pad_io<14>" LOCATE = SITE "AE21" LEVEL 1;
COMP "sbc_dat_pad_io<31>" LOCATE = SITE "AG19" LEVEL 1;
COMP "sbc_dat_pad_io<23>" LOCATE = SITE "AL23" LEVEL 1;
COMP "sbc_dat_pad_io<15>" LOCATE = SITE "AF21" LEVEL 1;
COMP "sbc_dat_pad_io<24>" LOCATE = SITE "AL22" LEVEL 1;
COMP "sbc_dat_pad_io<16>" LOCATE = SITE "AJ22" LEVEL 1;
COMP "sbc_dat_pad_io<25>" LOCATE = SITE "AE19" LEVEL 1;
COMP "sbc_dat_pad_io<17>" LOCATE = SITE "AK22" LEVEL 1;
COMP "sbc_dat_pad_io<26>" LOCATE = SITE "AD19" LEVEL 1;
COMP "sbc_dat_pad_io<18>" LOCATE = SITE "AL24" LEVEL 1;
COMP "sbc_dat_pad_io<27>" LOCATE = SITE "AM22" LEVEL 1;
COMP "sbc_dat_pad_io<19>" LOCATE = SITE "AM24" LEVEL 1;
COMP "sbc_dat_pad_io<28>" LOCATE = SITE "AM21" LEVEL 1;
COMP "sbc_dat_pad_io<29>" LOCATE = SITE "AH21" LEVEL 1;
COMP "fp_led_pad_o" LOCATE = SITE "K27" LEVEL 1;
COMP "ddr2high_addr_pad_o<10>" LOCATE = SITE "R7" LEVEL 1;
COMP "ddr2high_addr_pad_o<11>" LOCATE = SITE "N8" LEVEL 1;
COMP "ddr2high_addr_pad_o<12>" LOCATE = SITE "P6" LEVEL 1;
COMP "spi_data_pad_o" LOCATE = SITE "P32" LEVEL 1;
COMP "adc_d_dat_pad_i<10>" LOCATE = SITE "U25" LEVEL 1;
COMP "ddr2low_wen_pad_o" LOCATE = SITE "H1" LEVEL 1;
COMP "adc_d_dat_pad_i<11>" LOCATE = SITE "U26" LEVEL 1;
COMP "adc_d_dat_pad_i<12>" LOCATE = SITE "U29" LEVEL 1;
COMP "adc_d_dat_pad_i<13>" LOCATE = SITE "T29" LEVEL 1;
COMP "ddr2low_addr_pad_o<0>" LOCATE = SITE "F8" LEVEL 1;
COMP "ddr2low_addr_pad_o<1>" LOCATE = SITE "F2" LEVEL 1;
COMP "ddr2low_addr_pad_o<2>" LOCATE = SITE "F7" LEVEL 1;
COMP "ddr2low_addr_pad_o<3>" LOCATE = SITE "F1" LEVEL 1;
COMP "ddr2low_addr_pad_o<4>" LOCATE = SITE "L4" LEVEL 1;
COMP "ddr2low_addr_pad_o<5>" LOCATE = SITE "E3" LEVEL 1;
COMP "ddr2low_addr_pad_o<6>" LOCATE = SITE "G4" LEVEL 1;
COMP "ddr2low_addr_pad_o<7>" LOCATE = SITE "E1" LEVEL 1;
COMP "ddr2low_addr_pad_o<8>" LOCATE = SITE "L5" LEVEL 1;
COMP "ddr2low_addr_pad_o<9>" LOCATE = SITE "F5" LEVEL 1;
COMP "sbc_irq_pad_o" LOCATE = SITE "AL6" LEVEL 1;
COMP "adc_b_dat_pad_i<0>" LOCATE = SITE "L29" LEVEL 1;
COMP "adc_b_dat_pad_i<1>" LOCATE = SITE "L31" LEVEL 1;
COMP "adc_b_dat_pad_i<2>" LOCATE = SITE "V33" LEVEL 1;
COMP "adc_b_dat_pad_i<3>" LOCATE = SITE "M29" LEVEL 1;
COMP "adc_b_dat_pad_i<4>" LOCATE = SITE "L32" LEVEL 1;
COMP "adc_b_dat_pad_i<5>" LOCATE = SITE "J33" LEVEL 1;
COMP "adc_b_dat_pad_i<6>" LOCATE = SITE "L25" LEVEL 1;
COMP "adc_b_dat_pad_i<7>" LOCATE = SITE "K33" LEVEL 1;
COMP "adc_b_dat_pad_i<8>" LOCATE = SITE "J31" LEVEL 1;
COMP "adc_b_dat_pad_i<9>" LOCATE = SITE "G31" LEVEL 1;
COMP "ddr2high_data_pad_io<10>" LOCATE = SITE "N4" LEVEL 1;
COMP "ddr2high_data_pad_io<11>" LOCATE = SITE "T2" LEVEL 1;
COMP "ddr2high_data_pad_io<12>" LOCATE = SITE "T3" LEVEL 1;
COMP "ddr2high_data_pad_io<13>" LOCATE = SITE "R4" LEVEL 1;
COMP "ddr2high_data_pad_io<14>" LOCATE = SITE "V2" LEVEL 1;
COMP "ddr2high_data_pad_io<15>" LOCATE = SITE "T5" LEVEL 1;
COMP "ddr2high_clkn_pad_o" LOCATE = SITE "R9" LEVEL 1;
COMP "adc_a_dat_pad_i<10>" LOCATE = SITE "L30" LEVEL 1;
COMP "adc_a_dat_pad_i<11>" LOCATE = SITE "R26" LEVEL 1;
COMP "adc_a_dat_pad_i<12>" LOCATE = SITE "M28" LEVEL 1;
COMP "adc_a_dat_pad_i<13>" LOCATE = SITE "K30" LEVEL 1;
COMP "sys_clk106_en_pad_o" LOCATE = SITE "AK16" LEVEL 1;
COMP "ddr2low_udqsn_pad_io" LOCATE = SITE "N6" LEVEL 1;
COMP "ddr2high_bank_pad_o<0>" LOCATE = SITE "T7" LEVEL 1;
COMP "ddr2high_bank_pad_o<1>" LOCATE = SITE "N3" LEVEL 1;
COMP "ddr2high_cke_pad_o" LOCATE = SITE "T10" LEVEL 1;
COMP "sbc_dat_pad_io<0>" LOCATE = SITE "AG9" LEVEL 1;
COMP "sbc_dat_pad_io<1>" LOCATE = SITE "AH9" LEVEL 1;
COMP "sbc_dat_pad_io<2>" LOCATE = SITE "AK6" LEVEL 1;
COMP "sbc_dat_pad_io<3>" LOCATE = SITE "AK7" LEVEL 1;
COMP "sbc_dat_pad_io<4>" LOCATE = SITE "AK28" LEVEL 1;
COMP "sbc_dat_pad_io<5>" LOCATE = SITE "AK29" LEVEL 1;
COMP "sbc_dat_pad_io<6>" LOCATE = SITE "AH26" LEVEL 1;
COMP "sbc_dat_pad_io<7>" LOCATE = SITE "AG26" LEVEL 1;
COMP "sbc_dat_pad_io<8>" LOCATE = SITE "AE22" LEVEL 1;
COMP "sbc_dat_pad_io<9>" LOCATE = SITE "AF22" LEVEL 1;
COMP "ddr2high_clk_pad_o" LOCATE = SITE "R10" LEVEL 1;
COMP "adc_clk_npad_i" LOCATE = SITE "M31" LEVEL 1;
COMP "adc_clk_ppad_i" LOCATE = SITE "M32" LEVEL 1;
COMP "adc_a_dat_pad_i<0>" LOCATE = SITE "J28" LEVEL 1;
COMP "adc_a_dat_pad_i<1>" LOCATE = SITE "F31" LEVEL 1;
COMP "adc_a_dat_pad_i<2>" LOCATE = SITE "H34" LEVEL 1;
COMP "adc_a_dat_pad_i<3>" LOCATE = SITE "F30" LEVEL 1;
COMP "adc_a_dat_pad_i<4>" LOCATE = SITE "G32" LEVEL 1;
COMP "adc_a_dat_pad_i<5>" LOCATE = SITE "G30" LEVEL 1;
COMP "adc_a_dat_pad_i<6>" LOCATE = SITE "G29" LEVEL 1;
COMP "adc_a_dat_pad_i<7>" LOCATE = SITE "R25" LEVEL 1;
COMP "adc_a_dat_pad_i<8>" LOCATE = SITE "J32" LEVEL 1;
COMP "adc_a_dat_pad_i<9>" LOCATE = SITE "L28" LEVEL 1;
COMP "spi_clk_pad_o" LOCATE = SITE "N32" LEVEL 1;
COMP "sys_clk125_en_pad_o" LOCATE = SITE "AJ16" LEVEL 1;
COMP "ddr2low_ldqsn_pad_io" LOCATE = SITE "L10" LEVEL 1;
COMP "DIO<10>" LOCATE = SITE "AH5" LEVEL 1;
COMP "DIO<11>" LOCATE = SITE "W10" LEVEL 1;
COMP "sbc_rst_pad_o" LOCATE = SITE "AC4" LEVEL 1;
COMP "DIO<12>" LOCATE = SITE "AK3" LEVEL 1;
COMP "DIO<20>" LOCATE = SITE "V7" LEVEL 1;
COMP "DIO<21>" LOCATE = SITE "AJ7" LEVEL 1;
COMP "DIO<13>" LOCATE = SITE "AA6" LEVEL 1;
COMP "DIO<22>" LOCATE = SITE "V3" LEVEL 1;
COMP "DIO<14>" LOCATE = SITE "AA3" LEVEL 1;
COMP "DIO<23>" LOCATE = SITE "Y9" LEVEL 1;
COMP "DIO<15>" LOCATE = SITE "AA5" LEVEL 1;
COMP "DIO<16>" LOCATE = SITE "Y10" LEVEL 1;
COMP "DIO<24>" LOCATE = SITE "W2" LEVEL 1;
COMP "DIO<17>" LOCATE = SITE "AA4" LEVEL 1;
COMP "DIO<18>" LOCATE = SITE "AB1" LEVEL 1;
COMP "DIO<19>" LOCATE = SITE "AJ5" LEVEL 1;
COMP "sbc_adr_pad_i<10>" LOCATE = SITE "AL12" LEVEL 1;
COMP "sbc_adr_pad_i<11>" LOCATE = SITE "AD16" LEVEL 1;
COMP "sbc_adr_pad_i<12>" LOCATE = SITE "AE16" LEVEL 1;
COMP "sbc_adr_pad_i<13>" LOCATE = SITE "AG18" LEVEL 1;
COMP "sbc_adr_pad_i<14>" LOCATE = SITE "AF18" LEVEL 1;
COMP "sbc_adr_pad_i<15>" LOCATE = SITE "AK19" LEVEL 1;
COMP "sbc_adr_pad_i<16>" LOCATE = SITE "AJ19" LEVEL 1;
COMP "sbc_adr_pad_i<17>" LOCATE = SITE "AH19" LEVEL 1;
COMP "ddr2high_csn_pad_o" LOCATE = SITE "M7" LEVEL 1;
COMP "spi_cs_ckm_pad_o" LOCATE = SITE "N33" LEVEL 1;
COMP "ddr2low_rasn_pad_o" LOCATE = SITE "K8" LEVEL 1;
COMP "ddr2low_data_pad_io<10>" LOCATE = SITE "K7" LEVEL 1;
COMP "ddr2low_data_pad_io<11>" LOCATE = SITE "M3" LEVEL 1;
COMP "ddr2low_data_pad_io<12>" LOCATE = SITE "K2" LEVEL 1;
COMP "ddr2low_data_pad_io<13>" LOCATE = SITE "M9" LEVEL 1;
COMP "ddr2low_data_pad_io<14>" LOCATE = SITE "L1" LEVEL 1;
COMP "ddr2low_data_pad_io<15>" LOCATE = SITE "M2" LEVEL 1;
COMP "adc_c_dat_pad_i<10>" LOCATE = SITE "P29" LEVEL 1;
COMP "adc_c_dat_pad_i<11>" LOCATE = SITE "P27" LEVEL 1;
COMP "adc_c_dat_pad_i<12>" LOCATE = SITE "T24" LEVEL 1;
COMP "adc_c_dat_pad_i<13>" LOCATE = SITE "R28" LEVEL 1;
COMP "ddr2high_ldm_pad_o" LOCATE = SITE "R3" LEVEL 1;
COMP "sbc_adr_pad_i<2>" LOCATE = SITE "AJ13" LEVEL 1;
COMP "sbc_adr_pad_i<3>" LOCATE = SITE "AK13" LEVEL 1;
COMP "sbc_adr_pad_i<4>" LOCATE = SITE "AL11" LEVEL 1;
COMP "sbc_adr_pad_i<5>" LOCATE = SITE "AE15" LEVEL 1;
COMP "sbc_adr_pad_i<6>" LOCATE = SITE "AF15" LEVEL 1;
COMP "sbc_adr_pad_i<7>" LOCATE = SITE "AG14" LEVEL 1;
COMP "sbc_adr_pad_i<8>" LOCATE = SITE "AH14" LEVEL 1;
COMP "sbc_adr_pad_i<9>" LOCATE = SITE "AL13" LEVEL 1;
COMP "ddr2low_data_pad_io<0>" LOCATE = SITE "J8" LEVEL 1;
COMP "ddr2low_data_pad_io<1>" LOCATE = SITE "H3" LEVEL 1;
COMP "ddr2low_data_pad_io<2>" LOCATE = SITE "L6" LEVEL 1;
COMP "ddr2low_data_pad_io<3>" LOCATE = SITE "J5" LEVEL 1;
COMP "ddr2low_data_pad_io<4>" LOCATE = SITE "J3" LEVEL 1;
COMP "ddr2low_data_pad_io<5>" LOCATE = SITE "G5" LEVEL 1;
COMP "ddr2low_data_pad_io<6>" LOCATE = SITE "K1" LEVEL 1;
COMP "ddr2low_data_pad_io<7>" LOCATE = SITE "L7" LEVEL 1;
COMP "sbc_wrn_pad_i" LOCATE = SITE "AL29" LEVEL 1;
COMP "ddr2low_data_pad_io<8>" LOCATE = SITE "L8" LEVEL 1;
COMP "ddr2low_data_pad_io<9>" LOCATE = SITE "K4" LEVEL 1;
COMP "ddr2high_udqs_pad_io" LOCATE = SITE "U4" LEVEL 1;
COMP "ADC_CLK_A_i" LOCATE = SITE "J27" LEVEL 1;
COMP "ADC_CLK_B_i" LOCATE = SITE "L27" LEVEL 1;
COMP "ADC_CLK_C_i" LOCATE = SITE "R33" LEVEL 1;
COMP "ADC_CLK_D_i" LOCATE = SITE "T33" LEVEL 1;
NET "DIO_2_OBUF1" BEL "DIO_2_OBUF_BUFG.GCLKMUX" USELOCALCONNECT;
NET "sbc_csn_pad_i_BUFGP/IBUFG" BEL "sbc_csn_pad_i_BUFGP/BUFG.GCLKMUX"
        USELOCALCONNECT;
PIN PLL/C_TABLE/B6.A_pins<53> = BEL "PLL/C_TABLE/B6.A" PINNAME CLKA;
PIN PLL/C_TABLE/B6.B_pins<53> = BEL "PLL/C_TABLE/B6.B" PINNAME CLKB;
PIN PLL/C_TABLE/B9.A_pins<53> = BEL "PLL/C_TABLE/B9.A" PINNAME CLKA;
PIN PLL/C_TABLE/B9.B_pins<53> = BEL "PLL/C_TABLE/B9.B" PINNAME CLKB;
PIN PLL/C_TABLE/B12.A_pins<53> = BEL "PLL/C_TABLE/B12.A" PINNAME CLKA;
PIN PLL/C_TABLE/B12.B_pins<53> = BEL "PLL/C_TABLE/B12.B" PINNAME CLKB;
PIN PLL/C_TABLE/B15.A_pins<53> = BEL "PLL/C_TABLE/B15.A" PINNAME CLKA;
PIN PLL/C_TABLE/B15.B_pins<53> = BEL "PLL/C_TABLE/B15.B" PINNAME CLKB;
PIN PLL/C_TABLE/B181.A_pins<53> = BEL "PLL/C_TABLE/B181.A" PINNAME CLKA;
PIN PLL/C_TABLE/B181.B_pins<53> = BEL "PLL/C_TABLE/B181.B" PINNAME CLKB;
PIN PLL/C_TABLE/B184.A_pins<53> = BEL "PLL/C_TABLE/B184.A" PINNAME CLKA;
PIN PLL/C_TABLE/B184.B_pins<53> = BEL "PLL/C_TABLE/B184.B" PINNAME CLKB;
PIN PLL/C_TABLE/B187.A_pins<53> = BEL "PLL/C_TABLE/B187.A" PINNAME CLKA;
PIN PLL/C_TABLE/B187.B_pins<53> = BEL "PLL/C_TABLE/B187.B" PINNAME CLKB;
PIN PLL/C_TABLE/B190.A_pins<53> = BEL "PLL/C_TABLE/B190.A" PINNAME CLKA;
PIN PLL/C_TABLE/B190.B_pins<53> = BEL "PLL/C_TABLE/B190.B" PINNAME CLKB;
PIN PLL/C_TABLE/B356.A_pins<53> = BEL "PLL/C_TABLE/B356.A" PINNAME CLKA;
PIN PLL/C_TABLE/B356.B_pins<53> = BEL "PLL/C_TABLE/B356.B" PINNAME CLKB;
PIN PLL/C_TABLE/B359.A_pins<53> = BEL "PLL/C_TABLE/B359.A" PINNAME CLKA;
PIN PLL/C_TABLE/B359.B_pins<53> = BEL "PLL/C_TABLE/B359.B" PINNAME CLKB;
PIN PLL/C_TABLE/B362.A_pins<53> = BEL "PLL/C_TABLE/B362.A" PINNAME CLKA;
PIN PLL/C_TABLE/B362.B_pins<53> = BEL "PLL/C_TABLE/B362.B" PINNAME CLKB;
PIN PLL/C_TABLE/B365.A_pins<53> = BEL "PLL/C_TABLE/B365.A" PINNAME CLKA;
PIN PLL/C_TABLE/B365.B_pins<53> = BEL "PLL/C_TABLE/B365.B" PINNAME CLKB;
PIN PLL/C_TABLE/B531.A_pins<53> = BEL "PLL/C_TABLE/B531.A" PINNAME CLKA;
PIN PLL/C_TABLE/B531.B_pins<53> = BEL "PLL/C_TABLE/B531.B" PINNAME CLKB;
PIN PLL/C_TABLE/B535.A_pins<53> = BEL "PLL/C_TABLE/B535.A" PINNAME CLKA;
PIN PLL/C_TABLE/B535.B_pins<53> = BEL "PLL/C_TABLE/B535.B" PINNAME CLKB;
PIN PLL/C_TABLE/B539.A_pins<53> = BEL "PLL/C_TABLE/B539.A" PINNAME CLKA;
PIN PLL/C_TABLE/B539.B_pins<53> = BEL "PLL/C_TABLE/B539.B" PINNAME CLKB;
PIN PLL/ST_TABLE/B6.A_pins<53> = BEL "PLL/ST_TABLE/B6.A" PINNAME CLKA;
PIN PLL/ST_TABLE/B6.B_pins<53> = BEL "PLL/ST_TABLE/B6.B" PINNAME CLKB;
PIN PLL/HC_TABLE/B6.A_pins<53> = BEL "PLL/HC_TABLE/B6.A" PINNAME CLKA;
PIN PLL/HC_TABLE/B6.B_pins<53> = BEL "PLL/HC_TABLE/B6.B" PINNAME CLKB;
PIN PLL/INJ_TABLE/B6.A_pins<53> = BEL "PLL/INJ_TABLE/B6.A" PINNAME CLKA;
PIN PLL/INJ_TABLE/B6.B_pins<53> = BEL "PLL/INJ_TABLE/B6.B" PINNAME CLKB;
PIN PLL/ph_table_0/B6.A_pins<53> = BEL "PLL/ph_table_0/B6.A" PINNAME CLKA;
PIN PLL/ph_table_0/B6.B_pins<53> = BEL "PLL/ph_table_0/B6.B" PINNAME CLKB;
PIN PLL/ph_table_0/B10.A_pins<53> = BEL "PLL/ph_table_0/B10.A" PINNAME CLKA;
PIN PLL/ph_table_0/B10.B_pins<53> = BEL "PLL/ph_table_0/B10.B" PINNAME CLKB;
PIN
        PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/48/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1025.B_pins<53>
        = BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/48/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1025.B"
        PINNAME CLKB;
PIN
        PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/47/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1029.B_pins<53>
        = BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/47/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1029.B"
        PINNAME CLKB;
PIN
        PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/46/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1033.B_pins<53>
        = BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/46/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1033.B"
        PINNAME CLKB;
PIN
        PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/45/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1037.B_pins<53>
        = BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/45/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1037.B"
        PINNAME CLKB;
PIN
        PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/44/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1041.B_pins<53>
        = BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/44/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1041.B"
        PINNAME CLKB;
PIN
        PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/43/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1045.B_pins<53>
        = BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/43/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1045.B"
        PINNAME CLKB;
PIN
        PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/42/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1049.B_pins<53>
        = BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/42/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1049.B"
        PINNAME CLKB;
PIN
        PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/41/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1053.B_pins<53>
        = BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/41/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1053.B"
        PINNAME CLKB;
PIN
        PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/40/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1057.B_pins<53>
        = BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/40/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1057.B"
        PINNAME CLKB;
PIN
        PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/39/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1061.B_pins<53>
        = BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/39/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1061.B"
        PINNAME CLKB;
PIN
        PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/38/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1065.B_pins<53>
        = BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/38/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1065.B"
        PINNAME CLKB;
PIN
        PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/37/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1069.B_pins<53>
        = BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/37/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1069.B"
        PINNAME CLKB;
PIN
        PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/36/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1073.B_pins<53>
        = BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/36/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1073.B"
        PINNAME CLKB;
PIN
        PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/35/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1077.B_pins<53>
        = BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/35/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1077.B"
        PINNAME CLKB;
PIN
        PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/34/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1081.B_pins<53>
        = BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/34/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1081.B"
        PINNAME CLKB;
PIN
        PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/33/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1085.B_pins<53>
        = BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/33/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1085.B"
        PINNAME CLKB;
PIN
        PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/32/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1089.B_pins<53>
        = BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/32/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1089.B"
        PINNAME CLKB;
PIN
        PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/31/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1093.B_pins<53>
        = BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/31/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1093.B"
        PINNAME CLKB;
PIN
        PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/30/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1097.B_pins<53>
        = BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/30/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1097.B"
        PINNAME CLKB;
PIN
        PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/29/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1101.B_pins<53>
        = BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/29/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1101.B"
        PINNAME CLKB;
PIN
        PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/28/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1105.B_pins<53>
        = BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/28/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1105.B"
        PINNAME CLKB;
PIN
        PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/27/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1109.B_pins<53>
        = BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/27/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1109.B"
        PINNAME CLKB;
PIN
        PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/26/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1113.B_pins<53>
        = BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/26/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1113.B"
        PINNAME CLKB;
PIN
        PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/25/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1117.B_pins<53>
        = BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/25/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1117.B"
        PINNAME CLKB;
PIN
        PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/24/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1121.B_pins<53>
        = BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/24/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1121.B"
        PINNAME CLKB;
PIN
        PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/23/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1125.B_pins<53>
        = BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/23/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1125.B"
        PINNAME CLKB;
PIN
        PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/22/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1129.B_pins<53>
        = BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/22/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1129.B"
        PINNAME CLKB;
PIN
        PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/21/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1133.B_pins<53>
        = BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/21/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1133.B"
        PINNAME CLKB;
PIN
        PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/20/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1137.B_pins<53>
        = BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/20/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1137.B"
        PINNAME CLKB;
PIN
        PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/19/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1141.B_pins<53>
        = BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/19/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1141.B"
        PINNAME CLKB;
PIN
        PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/18/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1145.B_pins<53>
        = BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/18/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1145.B"
        PINNAME CLKB;
PIN
        PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/17/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1149.B_pins<53>
        = BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/17/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1149.B"
        PINNAME CLKB;
PIN
        PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/16/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1153.B_pins<53>
        = BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/16/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1153.B"
        PINNAME CLKB;
PIN
        PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/15/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1157.B_pins<53>
        = BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/15/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1157.B"
        PINNAME CLKB;
PIN
        PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/14/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1161.B_pins<53>
        = BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/14/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1161.B"
        PINNAME CLKB;
PIN
        PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/13/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1165.B_pins<53>
        = BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/13/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1165.B"
        PINNAME CLKB;
PIN
        PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/12/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1169.B_pins<53>
        = BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/12/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1169.B"
        PINNAME CLKB;
PIN
        PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/11/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1173.B_pins<53>
        = BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/11/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1173.B"
        PINNAME CLKB;
PIN
        PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/10/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1177.B_pins<53>
        = BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/10/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1177.B"
        PINNAME CLKB;
PIN
        PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/9/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1181.B_pins<53>
        = BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/9/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1181.B"
        PINNAME CLKB;
PIN
        PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/8/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1185.B_pins<53>
        = BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/8/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1185.B"
        PINNAME CLKB;
PIN
        PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/7/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1189.B_pins<53>
        = BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/7/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1189.B"
        PINNAME CLKB;
PIN
        PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/6/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1193.B_pins<53>
        = BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/6/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1193.B"
        PINNAME CLKB;
PIN
        PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/5/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1197.B_pins<53>
        = BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/5/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1197.B"
        PINNAME CLKB;
PIN
        PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/4/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1201.B_pins<53>
        = BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/4/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1201.B"
        PINNAME CLKB;
PIN
        PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/3/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1205.B_pins<53>
        = BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/3/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1205.B"
        PINNAME CLKB;
PIN
        PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/2/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1209.B_pins<53>
        = BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/2/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1209.B"
        PINNAME CLKB;
PIN
        PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/1/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1213.B_pins<53>
        = BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/1/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1213.B"
        PINNAME CLKB;
PIN
        PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/0/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1217.B_pins<53>
        = BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/0/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1217.B"
        PINNAME CLKB;
PIN
        PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/24/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim844.B_pins<53>
        = BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/24/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim844.B"
        PINNAME CLKB;
PIN
        PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/23/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim848.B_pins<53>
        = BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/23/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim848.B"
        PINNAME CLKB;
PIN
        PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/22/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim852.B_pins<53>
        = BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/22/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim852.B"
        PINNAME CLKB;
PIN
        PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/21/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim856.B_pins<53>
        = BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/21/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim856.B"
        PINNAME CLKB;
PIN
        PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/20/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim860.B_pins<53>
        = BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/20/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim860.B"
        PINNAME CLKB;
PIN
        PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/19/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim864.B_pins<53>
        = BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/19/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim864.B"
        PINNAME CLKB;
PIN
        PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/18/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim868.B_pins<53>
        = BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/18/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim868.B"
        PINNAME CLKB;
PIN
        PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/17/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim872.B_pins<53>
        = BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/17/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim872.B"
        PINNAME CLKB;
PIN
        PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/16/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim876.B_pins<53>
        = BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/16/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim876.B"
        PINNAME CLKB;
PIN
        PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/15/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim880.B_pins<53>
        = BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/15/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim880.B"
        PINNAME CLKB;
PIN
        PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/14/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim884.B_pins<53>
        = BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/14/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim884.B"
        PINNAME CLKB;
PIN
        PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/13/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim888.B_pins<53>
        = BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/13/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim888.B"
        PINNAME CLKB;
PIN
        PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/12/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim892.B_pins<53>
        = BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/12/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim892.B"
        PINNAME CLKB;
PIN
        PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/11/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim896.B_pins<53>
        = BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/11/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim896.B"
        PINNAME CLKB;
PIN
        PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/10/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim900.B_pins<53>
        = BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/10/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim900.B"
        PINNAME CLKB;
PIN
        PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/9/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim904.B_pins<53>
        = BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/9/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim904.B"
        PINNAME CLKB;
PIN
        PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/8/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim908.B_pins<53>
        = BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/8/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim908.B"
        PINNAME CLKB;
PIN
        PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/7/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim912.B_pins<53>
        = BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/7/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim912.B"
        PINNAME CLKB;
PIN
        PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/6/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim916.B_pins<53>
        = BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/6/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim916.B"
        PINNAME CLKB;
PIN
        PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/5/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim920.B_pins<53>
        = BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/5/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim920.B"
        PINNAME CLKB;
PIN
        PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/4/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim924.B_pins<53>
        = BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/4/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim924.B"
        PINNAME CLKB;
PIN
        PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/3/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim928.B_pins<53>
        = BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/3/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim928.B"
        PINNAME CLKB;
PIN
        PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/2/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim932.B_pins<53>
        = BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/2/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim932.B"
        PINNAME CLKB;
PIN
        PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/1/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim936.B_pins<53>
        = BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/1/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim936.B"
        PINNAME CLKB;
PIN
        PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/0/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim940.B_pins<53>
        = BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/0/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim940.B"
        PINNAME CLKB;
TIMEGRP D_CLK = BEL "ADC_A_buf_0" BEL "ADC_A_buf_1" BEL "ADC_A_buf_2" BEL
        "ADC_A_buf_3" BEL "ADC_A_buf_4" BEL "ADC_A_buf_5" BEL "ADC_A_buf_6"
        BEL "ADC_A_buf_7" BEL "ADC_A_buf_8" BEL "ADC_A_buf_9" BEL
        "ADC_A_buf_10" BEL "ADC_A_buf_11" BEL "ADC_A_buf_12" BEL "ADC_B_buf_0"
        BEL "ADC_B_buf_1" BEL "ADC_B_buf_2" BEL "ADC_B_buf_3" BEL
        "ADC_B_buf_4" BEL "ADC_B_buf_5" BEL "ADC_B_buf_6" BEL "ADC_B_buf_7"
        BEL "ADC_B_buf_8" BEL "ADC_B_buf_9" BEL "ADC_B_buf_10" BEL
        "ADC_B_buf_11" BEL "ADC_B_buf_12" BEL "ADC_C_buf_0" BEL "ADC_C_buf_1"
        BEL "ADC_C_buf_2" BEL "ADC_C_buf_3" BEL "ADC_C_buf_4" BEL
        "ADC_C_buf_5" BEL "ADC_C_buf_6" BEL "ADC_C_buf_7" BEL "ADC_C_buf_8"
        BEL "ADC_C_buf_9" BEL "ADC_C_buf_10" BEL "ADC_C_buf_11" BEL
        "ADC_C_buf_12" BEL "edge_reg_0" BEL "edge_reg_1" BEL "edge_reg_2" BEL
        "edge_reg_3" PIN "PLL/C_TABLE/B6.A_pins<53>" PIN
        "PLL/C_TABLE/B6.B_pins<53>" PIN "PLL/C_TABLE/B9.A_pins<53>" PIN
        "PLL/C_TABLE/B9.B_pins<53>" PIN "PLL/C_TABLE/B12.A_pins<53>" PIN
        "PLL/C_TABLE/B12.B_pins<53>" PIN "PLL/C_TABLE/B15.A_pins<53>" PIN
        "PLL/C_TABLE/B15.B_pins<53>" BEL "PLL/C_TABLE/BU21" BEL
        "PLL/C_TABLE/BU24" PIN "PLL/C_TABLE/B181.A_pins<53>" PIN
        "PLL/C_TABLE/B181.B_pins<53>" PIN "PLL/C_TABLE/B184.A_pins<53>" PIN
        "PLL/C_TABLE/B184.B_pins<53>" PIN "PLL/C_TABLE/B187.A_pins<53>" PIN
        "PLL/C_TABLE/B187.B_pins<53>" PIN "PLL/C_TABLE/B190.A_pins<53>" PIN
        "PLL/C_TABLE/B190.B_pins<53>" BEL "PLL/C_TABLE/BU196" BEL
        "PLL/C_TABLE/BU199" PIN "PLL/C_TABLE/B356.A_pins<53>" PIN
        "PLL/C_TABLE/B356.B_pins<53>" PIN "PLL/C_TABLE/B359.A_pins<53>" PIN
        "PLL/C_TABLE/B359.B_pins<53>" PIN "PLL/C_TABLE/B362.A_pins<53>" PIN
        "PLL/C_TABLE/B362.B_pins<53>" PIN "PLL/C_TABLE/B365.A_pins<53>" PIN
        "PLL/C_TABLE/B365.B_pins<53>" BEL "PLL/C_TABLE/BU371" BEL
        "PLL/C_TABLE/BU374" PIN "PLL/C_TABLE/B531.A_pins<53>" PIN
        "PLL/C_TABLE/B531.B_pins<53>" PIN "PLL/C_TABLE/B535.A_pins<53>" PIN
        "PLL/C_TABLE/B535.B_pins<53>" PIN "PLL/C_TABLE/B539.A_pins<53>" PIN
        "PLL/C_TABLE/B539.B_pins<53>" PIN "PLL/ST_TABLE/B6.A_pins<53>" PIN
        "PLL/ST_TABLE/B6.B_pins<53>" PIN "PLL/HC_TABLE/B6.A_pins<53>" PIN
        "PLL/HC_TABLE/B6.B_pins<53>" PIN "PLL/INJ_TABLE/B6.A_pins<53>" PIN
        "PLL/INJ_TABLE/B6.B_pins<53>" PIN "PLL/ph_table_0/B6.A_pins<53>" PIN
        "PLL/ph_table_0/B6.B_pins<53>" PIN "PLL/ph_table_0/B10.A_pins<53>" PIN
        "PLL/ph_table_0/B10.B_pins<53>" BEL "PLL/C_timer_stop" BEL
        "PLL/HC_timing_rising" BEL "PLL/ST_edg_det_0" BEL
        "PLL/inj_trig_rising" BEL "PLL/ST_timing_rising" BEL
        "PLL/HC_tim_edg_det_0" BEL "PLL/filter1_in_0" BEL "PLL/filter1_in_1"
        BEL "PLL/filter1_in_2" BEL "PLL/filter1_in_3" BEL "PLL/filter1_in_4"
        BEL "PLL/filter1_in_5" BEL "PLL/filter1_in_6" BEL "PLL/filter1_in_7"
        BEL "PLL/filter1_in_8" BEL "PLL/filter1_in_9" BEL "PLL/filter1_in_10"
        BEL "PLL/filter1_in_11" BEL "PLL/filter1_in_12" BEL
        "PLL/filter1_in_13" BEL "PLL/PT_MSB_rising" BEL
        "PLL/inj_trig_edg_det_0" BEL "PLL/change_PT" BEL "PLL/clk62" BEL
        "PLL/ST_edg_det_1" BEL "PLL/HC_tim_edg_det_1" BEL "PLL/HC_temp" BEL
        "PLL/HC_synch" BEL "PLL/inj_trig_edg_det_1" BEL "PLL/ST_tab_ST_addr_0"
        BEL "PLL/ST_tab_ST_addr_1" BEL "PLL/ST_tab_ST_addr_2" BEL
        "PLL/SDRAM_ST_addr_0" BEL "PLL/SDRAM_ST_addr_1" BEL
        "PLL/SDRAM_ST_addr_2" BEL "PLL/SDRAM_ST_addr_3" BEL
        "PLL/SDRAM_ST_addr_4" BEL "PLL/SDRAM_ST_addr_5" BEL
        "PLL/SDRAM_ST_addr_6" BEL "PLL/SDRAM_ST_addr_7" BEL
        "PLL/SDRAM_ST_addr_8" BEL "PLL/SDRAM_ST_addr_9" BEL
        "PLL/SDRAM_ST_addr_10" BEL "PLL/SDRAM_ST_addr_11" BEL
        "PLL/SDRAM_ST_addr_12" BEL "PLL/SDRAM_ST_addr_13" BEL
        "PLL/SDRAM_ST_addr_14" BEL "PLL/SDRAM_ST_addr_15" BEL
        "PLL/SDRAM_ST_addr_16" BEL "PLL/SDRAM_ST_addr_17" BEL
        "PLL/SDRAM_ST_addr_18" BEL "PLL/SDRAM_ST_addr_19" BEL
        "PLL/SDRAM_ST_addr_20" BEL "PLL/SDRAM_ST_addr_21" BEL
        "PLL/SDRAM_ST_addr_22" BEL "PLL/SDRAM_ST_addr_23" BEL
        "PLL/SDRAM_ST_addr_24" BEL "PLL/SDRAM_ST_addr_25" BEL
        "PLL/HC_tab_ST_addr_0" BEL "PLL/HC_tab_ST_addr_1" BEL
        "PLL/HC_tab_ST_addr_2" BEL "PLL/HC_tab_ST_addr_3" BEL
        "PLL/HC_tab_ST_addr_4" BEL "PLL/C_tab_ST_addr_0" BEL
        "PLL/C_tab_ST_addr_1" BEL "PLL/C_tab_ST_addr_2" BEL
        "PLL/C_tab_ST_addr_3" BEL "PLL/C_tab_ST_addr_4" BEL
        "PLL/C_tab_ST_addr_5" BEL "PLL/C_tab_ST_addr_6" BEL
        "PLL/C_tab_ST_addr_7" BEL "PLL/C_tab_ST_addr_8" BEL
        "PLL/C_tab_ST_addr_9" BEL "PLL/C_tab_ST_addr_10" BEL
        "PLL/C_tab_ST_addr_11" BEL "PLL/C_tab_ST_addr_12" BEL
        "PLL/INJ_tab_ST_addr_0" BEL "PLL/INJ_tab_ST_addr_1" BEL
        "PLL/INJ_tab_ST_addr_2" BEL "PLL/x0_0" BEL "PLL/x0_1" BEL "PLL/x0_2"
        BEL "PLL/x0_3" BEL "PLL/x0_4" BEL "PLL/x0_5" BEL "PLL/x0_6" BEL
        "PLL/x0_7" BEL "PLL/x0_8" BEL "PLL/x0_9" BEL "PLL/x0_10" BEL
        "PLL/x0_11" BEL "PLL/x0_12" BEL "PLL/x0_13" BEL "PLL/x0_14" BEL
        "PLL/x0_15" BEL "PLL/x0_16" BEL "PLL/x0_17" BEL "PLL/x0_18" BEL
        "PLL/x0_19" BEL "PLL/x0_20" BEL "PLL/x0_21" BEL "PLL/x0_22" BEL
        "PLL/x0_23" BEL "PLL/x1_0" BEL "PLL/x1_1" BEL "PLL/x1_2" BEL
        "PLL/x1_3" BEL "PLL/x1_4" BEL "PLL/x1_5" BEL "PLL/x1_6" BEL "PLL/x1_7"
        BEL "PLL/x1_8" BEL "PLL/x1_9" BEL "PLL/x1_10" BEL "PLL/x1_11" BEL
        "PLL/x1_12" BEL "PLL/x1_13" BEL "PLL/x1_14" BEL "PLL/x1_15" BEL
        "PLL/x1_16" BEL "PLL/x1_17" BEL "PLL/x1_18" BEL "PLL/x1_19" BEL
        "PLL/x1_20" BEL "PLL/x1_21" BEL "PLL/x1_22" BEL "PLL/x1_23" BEL
        "PLL/x2_0" BEL "PLL/x2_1" BEL "PLL/x2_2" BEL "PLL/x2_3" BEL "PLL/x2_4"
        BEL "PLL/x2_5" BEL "PLL/x2_6" BEL "PLL/x2_7" BEL "PLL/x2_8" BEL
        "PLL/x2_9" BEL "PLL/x2_10" BEL "PLL/x2_11" BEL "PLL/x2_12" BEL
        "PLL/x2_13" BEL "PLL/x2_14" BEL "PLL/x2_15" BEL "PLL/x2_16" BEL
        "PLL/x2_17" BEL "PLL/x2_18" BEL "PLL/x2_19" BEL "PLL/x2_20" BEL
        "PLL/x2_21" BEL "PLL/x2_22" BEL "PLL/x2_23" BEL "PLL/n2_0" BEL
        "PLL/n2_1" BEL "PLL/n2_2" BEL "PLL/n2_3" BEL "PLL/n2_4" BEL "PLL/n2_5"
        BEL "PLL/n2_6" BEL "PLL/n2_7" BEL "PLL/n2_8" BEL "PLL/n2_9" BEL
        "PLL/n2_10" BEL "PLL/n2_11" BEL "PLL/n2_12" BEL "PLL/n2_13" BEL
        "PLL/n2_14" BEL "PLL/n2_15" BEL "PLL/n2_16" BEL "PLL/n2_17" BEL
        "PLL/n2_18" BEL "PLL/n2_19" BEL "PLL/n2_20" BEL "PLL/n2_21" BEL
        "PLL/n2_22" BEL "PLL/n2_23" BEL "PLL/y1_0" BEL "PLL/y1_1" BEL
        "PLL/y1_2" BEL "PLL/y1_3" BEL "PLL/y1_4" BEL "PLL/y1_5" BEL "PLL/y1_6"
        BEL "PLL/y1_7" BEL "PLL/y1_8" BEL "PLL/y1_9" BEL "PLL/y1_10" BEL
        "PLL/y1_11" BEL "PLL/y1_12" BEL "PLL/y1_13" BEL "PLL/y1_14" BEL
        "PLL/y1_15" BEL "PLL/y1_16" BEL "PLL/y1_17" BEL "PLL/y1_18" BEL
        "PLL/y1_19" BEL "PLL/y1_20" BEL "PLL/y1_21" BEL "PLL/y1_22" BEL
        "PLL/y1_23" BEL "PLL/y0_0" BEL "PLL/y0_1" BEL "PLL/y0_2" BEL
        "PLL/y0_3" BEL "PLL/y0_4" BEL "PLL/y0_5" BEL "PLL/y0_6" BEL "PLL/y0_7"
        BEL "PLL/y0_8" BEL "PLL/y0_9" BEL "PLL/y0_10" BEL "PLL/y0_11" BEL
        "PLL/y0_12" BEL "PLL/y0_13" BEL "PLL/y0_14" BEL "PLL/y0_15" BEL
        "PLL/y0_16" BEL "PLL/y0_17" BEL "PLL/y0_18" BEL "PLL/y0_19" BEL
        "PLL/y0_20" BEL "PLL/y0_21" BEL "PLL/y0_22" BEL "PLL/y0_23" BEL
        "PLL/y2_0" BEL "PLL/y2_1" BEL "PLL/y2_2" BEL "PLL/y2_3" BEL "PLL/y2_4"
        BEL "PLL/y2_5" BEL "PLL/y2_6" BEL "PLL/y2_7" BEL "PLL/y2_8" BEL
        "PLL/y2_9" BEL "PLL/y2_10" BEL "PLL/y2_11" BEL "PLL/y2_12" BEL
        "PLL/y2_13" BEL "PLL/y2_14" BEL "PLL/y2_15" BEL "PLL/y2_16" BEL
        "PLL/y2_17" BEL "PLL/y2_18" BEL "PLL/y2_19" BEL "PLL/y2_20" BEL
        "PLL/y2_21" BEL "PLL/y2_22" BEL "PLL/y2_23" BEL "PLL/n3_0" BEL
        "PLL/n3_1" BEL "PLL/n3_2" BEL "PLL/n3_3" BEL "PLL/n3_4" BEL "PLL/n3_5"
        BEL "PLL/n3_6" BEL "PLL/n3_7" BEL "PLL/n3_8" BEL "PLL/n3_9" BEL
        "PLL/n3_10" BEL "PLL/n3_11" BEL "PLL/n3_12" BEL "PLL/n3_13" BEL
        "PLL/n3_14" BEL "PLL/n3_15" BEL "PLL/n3_16" BEL "PLL/n3_17" BEL
        "PLL/n3_18" BEL "PLL/n3_19" BEL "PLL/n3_20" BEL "PLL/n3_21" BEL
        "PLL/n3_22" BEL "PLL/n3_23" BEL "PLL/result2_tmp_0" BEL
        "PLL/result2_tmp_1" BEL "PLL/result2_tmp_2" BEL "PLL/result2_tmp_3"
        BEL "PLL/result2_tmp_4" BEL "PLL/result2_tmp_5" BEL
        "PLL/result2_tmp_6" BEL "PLL/result2_tmp_7" BEL "PLL/result2_tmp_8"
        BEL "PLL/result2_tmp_9" BEL "PLL/result2_tmp_10" BEL
        "PLL/result2_tmp_11" BEL "PLL/result2_tmp_12" BEL "PLL/result2_tmp_13"
        BEL "PLL/result2_tmp_14" BEL "PLL/result2_tmp_15" BEL
        "PLL/result1_tmp_0" BEL "PLL/result1_tmp_1" BEL "PLL/result1_tmp_2"
        BEL "PLL/result1_tmp_3" BEL "PLL/result1_tmp_4" BEL
        "PLL/result1_tmp_5" BEL "PLL/result1_tmp_6" BEL "PLL/result1_tmp_7"
        BEL "PLL/result1_tmp_8" BEL "PLL/result1_tmp_9" BEL
        "PLL/result1_tmp_10" BEL "PLL/result1_tmp_11" BEL "PLL/result1_tmp_12"
        BEL "PLL/result1_tmp_13" BEL "PLL/result1_tmp_14" BEL
        "PLL/result1_tmp_15" BEL "PLL/result0_tmp_0" BEL "PLL/result0_tmp_1"
        BEL "PLL/result0_tmp_2" BEL "PLL/result0_tmp_3" BEL
        "PLL/result0_tmp_4" BEL "PLL/result0_tmp_5" BEL "PLL/result0_tmp_6"
        BEL "PLL/result0_tmp_7" BEL "PLL/result0_tmp_8" BEL
        "PLL/result0_tmp_9" BEL "PLL/result0_tmp_10" BEL "PLL/result0_tmp_11"
        BEL "PLL/result0_tmp_12" BEL "PLL/result0_tmp_13" BEL
        "PLL/result0_tmp_14" BEL "PLL/result0_tmp_15" BEL "PLL/s4_0" BEL
        "PLL/s4_1" BEL "PLL/s4_2" BEL "PLL/s4_3" BEL "PLL/s4_4" BEL "PLL/s4_5"
        BEL "PLL/s4_6" BEL "PLL/s4_7" BEL "PLL/s4_8" BEL "PLL/s4_9" BEL
        "PLL/s4_10" BEL "PLL/s4_11" BEL "PLL/s4_12" BEL "PLL/s4_13" BEL
        "PLL/s4_14" BEL "PLL/s4_15" BEL "PLL/s4_16" BEL "PLL/s4_17" BEL
        "PLL/s4_18" BEL "PLL/s4_19" BEL "PLL/s4_20" BEL "PLL/s4_21" BEL
        "PLL/s4_22" BEL "PLL/s4_23" BEL "PLL/n4_0" BEL "PLL/n4_1" BEL
        "PLL/n4_2" BEL "PLL/n4_3" BEL "PLL/n4_4" BEL "PLL/n4_5" BEL "PLL/n4_6"
        BEL "PLL/n4_7" BEL "PLL/n4_8" BEL "PLL/n4_9" BEL "PLL/n4_10" BEL
        "PLL/n4_11" BEL "PLL/n4_12" BEL "PLL/n4_13" BEL "PLL/n4_14" BEL
        "PLL/n4_15" BEL "PLL/n4_16" BEL "PLL/n4_17" BEL "PLL/n4_18" BEL
        "PLL/n4_19" BEL "PLL/n4_20" BEL "PLL/n4_21" BEL "PLL/n4_22" BEL
        "PLL/n4_23" BEL "PLL/n5_0" BEL "PLL/n5_1" BEL "PLL/n5_2" BEL
        "PLL/n5_3" BEL "PLL/n5_4" BEL "PLL/n5_5" BEL "PLL/n5_6" BEL "PLL/n5_7"
        BEL "PLL/n5_8" BEL "PLL/n5_9" BEL "PLL/n5_10" BEL "PLL/n5_11" BEL
        "PLL/n5_12" BEL "PLL/n5_13" BEL "PLL/n5_14" BEL "PLL/n5_15" BEL
        "PLL/n5_16" BEL "PLL/n5_17" BEL "PLL/n5_18" BEL "PLL/n5_19" BEL
        "PLL/n5_20" BEL "PLL/n5_21" BEL "PLL/n5_22" BEL "PLL/n5_23" BEL
        "PLL/s6_0" BEL "PLL/s6_1" BEL "PLL/s6_2" BEL "PLL/s6_3" BEL "PLL/s6_4"
        BEL "PLL/s6_5" BEL "PLL/s6_6" BEL "PLL/s6_7" BEL "PLL/s6_8" BEL
        "PLL/s6_9" BEL "PLL/s6_10" BEL "PLL/s6_11" BEL "PLL/s6_12" BEL
        "PLL/s6_13" BEL "PLL/s6_14" BEL "PLL/s6_15" BEL "PLL/s6_16" BEL
        "PLL/s6_17" BEL "PLL/s6_18" BEL "PLL/s6_19" BEL "PLL/s6_20" BEL
        "PLL/s6_21" BEL "PLL/s6_22" BEL "PLL/s6_23" BEL "PLL/n6_0" BEL
        "PLL/n6_1" BEL "PLL/n6_2" BEL "PLL/n6_3" BEL "PLL/n6_4" BEL "PLL/n6_5"
        BEL "PLL/n6_6" BEL "PLL/n6_7" BEL "PLL/n6_8" BEL "PLL/n6_9" BEL
        "PLL/n6_10" BEL "PLL/n6_11" BEL "PLL/n6_12" BEL "PLL/n6_13" BEL
        "PLL/n6_14" BEL "PLL/n6_15" BEL "PLL/n6_16" BEL "PLL/n6_17" BEL
        "PLL/n6_18" BEL "PLL/n6_19" BEL "PLL/n6_20" BEL "PLL/n6_21" BEL
        "PLL/n6_22" BEL "PLL/n6_23" BEL "PLL/dds_freq_OVR" BEL
        "PLL/PT_MSB_edg_det_0" BEL "PLL/dds_freq_UR" BEL
        "PLL/PT_MSB_edg_det_1" BEL "PLL/HC_tab_addr_cnt_0" BEL
        "PLL/HC_tab_addr_cnt_1" BEL "PLL/HC_tab_addr_cnt_2" BEL
        "PLL/HC_tab_addr_cnt_3" BEL "PLL/HC_tab_addr_cnt_4" BEL
        "PLL/ST_tab_addr_cnt_0" BEL "PLL/ST_tab_addr_cnt_1" BEL
        "PLL/ST_tab_addr_cnt_2" BEL "PLL/INJ_tab_addr_cnt_0" BEL
        "PLL/INJ_tab_addr_cnt_1" BEL "PLL/INJ_tab_addr_cnt_2" BEL
        "PLL/state_FFd1" BEL "PLL/state_FFd2" BEL "PLL/accumulate_0_0" BEL
        "PLL/accumulate_0_1" BEL "PLL/accumulate_0_2" BEL "PLL/accumulate_0_3"
        BEL "PLL/accumulate_0_4" BEL "PLL/accumulate_0_5" BEL
        "PLL/accumulate_0_6" BEL "PLL/accumulate_0_7" BEL "PLL/accumulate_0_8"
        BEL "PLL/accumulate_0_9" BEL "PLL/accumulate_0_10" BEL
        "PLL/accumulate_0_11" BEL "PLL/accumulate_0_12" BEL
        "PLL/accumulate_0_13" BEL "PLL/accumulate_0_14" BEL
        "PLL/accumulate_0_15" BEL "PLL/C_tab_addr_cnt_0" BEL
        "PLL/C_tab_addr_cnt_1" BEL "PLL/C_tab_addr_cnt_2" BEL
        "PLL/C_tab_addr_cnt_3" BEL "PLL/C_tab_addr_cnt_4" BEL
        "PLL/C_tab_addr_cnt_5" BEL "PLL/C_tab_addr_cnt_6" BEL
        "PLL/C_tab_addr_cnt_7" BEL "PLL/C_tab_addr_cnt_8" BEL
        "PLL/C_tab_addr_cnt_9" BEL "PLL/C_tab_addr_cnt_10" BEL
        "PLL/C_tab_addr_cnt_11" BEL "PLL/C_tab_addr_cnt_12" BEL
        "PLL/accumulate_1_0" BEL "PLL/accumulate_1_1" BEL "PLL/accumulate_1_2"
        BEL "PLL/accumulate_1_3" BEL "PLL/accumulate_1_4" BEL
        "PLL/accumulate_1_5" BEL "PLL/accumulate_1_6" BEL "PLL/accumulate_1_7"
        BEL "PLL/accumulate_1_8" BEL "PLL/accumulate_1_9" BEL
        "PLL/accumulate_1_10" BEL "PLL/accumulate_1_11" BEL
        "PLL/accumulate_1_12" BEL "PLL/accumulate_1_13" BEL
        "PLL/accumulate_1_14" BEL "PLL/accumulate_1_15" BEL
        "PLL/accumulate_2_0" BEL "PLL/accumulate_2_1" BEL "PLL/accumulate_2_2"
        BEL "PLL/accumulate_2_3" BEL "PLL/accumulate_2_4" BEL
        "PLL/accumulate_2_5" BEL "PLL/accumulate_2_6" BEL "PLL/accumulate_2_7"
        BEL "PLL/accumulate_2_8" BEL "PLL/accumulate_2_9" BEL
        "PLL/accumulate_2_10" BEL "PLL/accumulate_2_11" BEL
        "PLL/accumulate_2_12" BEL "PLL/accumulate_2_13" BEL
        "PLL/accumulate_2_14" BEL "PLL/accumulate_2_15" BEL
        "PLL/SDRAM_Addr_cnt_0" BEL "PLL/SDRAM_Addr_cnt_1" BEL
        "PLL/SDRAM_Addr_cnt_2" BEL "PLL/SDRAM_Addr_cnt_3" BEL
        "PLL/SDRAM_Addr_cnt_4" BEL "PLL/SDRAM_Addr_cnt_5" BEL
        "PLL/SDRAM_Addr_cnt_6" BEL "PLL/SDRAM_Addr_cnt_7" BEL
        "PLL/SDRAM_Addr_cnt_8" BEL "PLL/SDRAM_Addr_cnt_9" BEL
        "PLL/SDRAM_Addr_cnt_10" BEL "PLL/SDRAM_Addr_cnt_11" BEL
        "PLL/SDRAM_Addr_cnt_12" BEL "PLL/SDRAM_Addr_cnt_13" BEL
        "PLL/SDRAM_Addr_cnt_14" BEL "PLL/SDRAM_Addr_cnt_15" BEL
        "PLL/SDRAM_Addr_cnt_16" BEL "PLL/SDRAM_Addr_cnt_17" BEL
        "PLL/SDRAM_Addr_cnt_18" BEL "PLL/SDRAM_Addr_cnt_19" BEL
        "PLL/SDRAM_Addr_cnt_20" BEL "PLL/SDRAM_Addr_cnt_21" BEL
        "PLL/SDRAM_Addr_cnt_22" BEL "PLL/SDRAM_Addr_cnt_23" BEL
        "PLL/SDRAM_Addr_cnt_24" BEL "PLL/SDRAM_Addr_cnt_25" BEL
        "PLL/C_timer_count_0" BEL "PLL/C_timer_count_1" BEL
        "PLL/C_timer_count_2" BEL "PLL/C_timer_count_3" BEL
        "PLL/C_timer_count_4" BEL "PLL/C_timer_count_5" BEL
        "PLL/C_timer_count_6" BEL "PLL/C_timer_count_7" BEL
        "PLL/C_timer_count_8" BEL "PLL/C_timer_count_9" BEL
        "PLL/C_timer_count_10" BEL "PLL/C_timer_count_11" BEL
        "PLL/C_timer_count_12" BEL "PLL/C_timer_count_13" BEL
        "PLL/C_timer_count_14" BEL "PLL/C_timer_count_15" BEL
        "PLL/C_timer_count_16" BEL "PLL/b0_0" BEL "PLL/b0_1" BEL "PLL/b0_2"
        BEL "PLL/b0_3" BEL "PLL/b0_4" BEL "PLL/b0_5" BEL "PLL/b0_6" BEL
        "PLL/b0_7" BEL "PLL/b0_8" BEL "PLL/b0_9" BEL "PLL/b0_10" BEL
        "PLL/b0_11" BEL "PLL/b0_12" BEL "PLL/b0_13" BEL "PLL/b0_14" BEL
        "PLL/b0_15" BEL "PLL/b0_16" BEL "PLL/b0_17" BEL "PLL/b0_18" BEL
        "PLL/b0_19" BEL "PLL/b0_20" BEL "PLL/b0_21" BEL "PLL/b0_22" BEL
        "PLL/b0_23" BEL "PLL/b1_0" BEL "PLL/b1_1" BEL "PLL/b1_2" BEL
        "PLL/b1_3" BEL "PLL/b1_4" BEL "PLL/b1_5" BEL "PLL/b1_6" BEL "PLL/b1_7"
        BEL "PLL/b1_8" BEL "PLL/b1_9" BEL "PLL/b1_10" BEL "PLL/b1_11" BEL
        "PLL/b1_12" BEL "PLL/b1_13" BEL "PLL/b1_14" BEL "PLL/b1_15" BEL
        "PLL/b1_16" BEL "PLL/b1_17" BEL "PLL/b1_18" BEL "PLL/b1_19" BEL
        "PLL/b1_20" BEL "PLL/b1_21" BEL "PLL/b1_22" BEL "PLL/b1_23" BEL
        "PLL/e1_0" BEL "PLL/e1_1" BEL "PLL/e1_2" BEL "PLL/e1_3" BEL "PLL/e1_4"
        BEL "PLL/e1_5" BEL "PLL/e1_6" BEL "PLL/e1_7" BEL "PLL/e1_8" BEL
        "PLL/e1_9" BEL "PLL/e1_10" BEL "PLL/e1_11" BEL "PLL/e1_12" BEL
        "PLL/e1_13" BEL "PLL/e1_14" BEL "PLL/e1_15" BEL "PLL/e1_16" BEL
        "PLL/e1_17" BEL "PLL/e1_18" BEL "PLL/e1_19" BEL "PLL/e1_20" BEL
        "PLL/e1_21" BEL "PLL/e1_22" BEL "PLL/e1_23" BEL "PLL/b2_0" BEL
        "PLL/b2_1" BEL "PLL/b2_2" BEL "PLL/b2_3" BEL "PLL/b2_4" BEL "PLL/b2_5"
        BEL "PLL/b2_6" BEL "PLL/b2_7" BEL "PLL/b2_8" BEL "PLL/b2_9" BEL
        "PLL/b2_10" BEL "PLL/b2_11" BEL "PLL/b2_12" BEL "PLL/b2_13" BEL
        "PLL/b2_14" BEL "PLL/b2_15" BEL "PLL/b2_16" BEL "PLL/b2_17" BEL
        "PLL/b2_18" BEL "PLL/b2_19" BEL "PLL/b2_20" BEL "PLL/b2_21" BEL
        "PLL/b2_22" BEL "PLL/b2_23" BEL "PLL/e0_0" BEL "PLL/e0_1" BEL
        "PLL/e0_2" BEL "PLL/e0_3" BEL "PLL/e0_4" BEL "PLL/e0_5" BEL "PLL/e0_6"
        BEL "PLL/e0_7" BEL "PLL/e0_8" BEL "PLL/e0_9" BEL "PLL/e0_10" BEL
        "PLL/e0_11" BEL "PLL/e0_12" BEL "PLL/e0_13" BEL "PLL/e0_14" BEL
        "PLL/e0_15" BEL "PLL/e0_16" BEL "PLL/e0_17" BEL "PLL/e0_18" BEL
        "PLL/e0_19" BEL "PLL/e0_20" BEL "PLL/e0_21" BEL "PLL/e0_22" BEL
        "PLL/e0_23" BEL "PLL/e2_0" BEL "PLL/e2_1" BEL "PLL/e2_2" BEL
        "PLL/e2_3" BEL "PLL/e2_4" BEL "PLL/e2_5" BEL "PLL/e2_6" BEL "PLL/e2_7"
        BEL "PLL/e2_8" BEL "PLL/e2_9" BEL "PLL/e2_10" BEL "PLL/e2_11" BEL
        "PLL/e2_12" BEL "PLL/e2_13" BEL "PLL/e2_14" BEL "PLL/e2_15" BEL
        "PLL/e2_16" BEL "PLL/e2_17" BEL "PLL/e2_18" BEL "PLL/e2_19" BEL
        "PLL/e2_20" BEL "PLL/e2_21" BEL "PLL/e2_22" BEL "PLL/e2_23" BEL
        "PLL/dds_ph_0" BEL "PLL/dds_ph_1" BEL "PLL/dds_ph_2" BEL
        "PLL/dds_ph_3" BEL "PLL/dds_ph_4" BEL "PLL/dds_ph_5" BEL
        "PLL/dds_ph_6" BEL "PLL/dds_ph_7" BEL "PLL/dds_ph_8" BEL
        "PLL/dds_ph_9" BEL "PLL/dds_ph_10" BEL "PLL/dds_ph_11" BEL
        "PLL/dds_ph_12" BEL "PLL/dds_ph_13" BEL "PLL/dds_ph_14" BEL
        "PLL/dds_ph_15" BEL "PLL/dds_ph_16" BEL "PLL/dds_ph_17" BEL
        "PLL/dds_ph_18" BEL "PLL/dds_ph_19" BEL "PLL/dds_ph_20" BEL
        "PLL/dds_ph_21" BEL "PLL/dds_ph_22" BEL "PLL/dds_ph_23" BEL
        "PLL/dds_ph_24" BEL "PLL/dds_ph_25" BEL "PLL/dds_ph_26" BEL
        "PLL/dds_ph_27" BEL "PLL/dds_ph_28" BEL "PLL/dds_ph_29" BEL
        "PLL/dds_ph_30" BEL "PLL/dds_ph_31" BEL "PLL/dds_freq_31" BEL
        "PLL/dds_freq_30" BEL "PLL/dds_freq_29" BEL "PLL/dds_freq_28" BEL
        "PLL/dds_freq_27" BEL "PLL/dds_freq_26" BEL "PLL/dds_freq_25" BEL
        "PLL/dds_freq_24" BEL "PLL/dds_freq_23" BEL "PLL/dds_freq_22" BEL
        "PLL/dds_freq_21" BEL "PLL/dds_freq_20" BEL "PLL/dds_freq_19" BEL
        "PLL/dds_freq_18" BEL "PLL/dds_freq_17" BEL "PLL/dds_freq_16" BEL
        "PLL/dds_freq_15" BEL "PLL/dds_freq_14" BEL "PLL/dds_freq_13" BEL
        "PLL/dds_freq_12" BEL "PLL/dds_freq_11" BEL "PLL/dds_freq_10" BEL
        "PLL/dds_freq_9" BEL "PLL/dds_freq_8" BEL "PLL/dds_freq_7" BEL
        "PLL/dds_freq_6" BEL "PLL/dds_freq_5" BEL "PLL/dds_freq_4" BEL
        "PLL/dds_freq_3" BEL "PLL/dds_freq_2" BEL "PLL/dds_freq_1" BEL
        "PLL/dds_freq_0" BEL "PLL/chipscope/trig_del1_0" BEL
        "PLL/chipscope/trig_del1_1" BEL "PLL/chipscope/trig_del1_2" BEL
        "PLL/chipscope/stop_trig_0" BEL "PLL/chipscope/clk2" BEL
        "PLL/chipscope/trig_ch0_delayed" BEL "PLL/chipscope/trig_del2_0" BEL
        "PLL/chipscope/trig_del2_1" BEL "PLL/chipscope/trig_del2_2" BEL
        "PLL/chipscope/stop_trig_1" BEL "PLL/chipscope/trig_timer_en" BEL
        "PLL/chipscope/stop_trig_2" BEL "PLL/chipscope/stop_trig_3" BEL
        "PLL/chipscope/stop_trig_4" BEL "PLL/chipscope/trig_del3_0" BEL
        "PLL/chipscope/trig_del3_3" BEL "PLL/chipscope/trig_del3_2" BEL
        "PLL/chipscope/timer_0" BEL "PLL/chipscope/timer_1" BEL
        "PLL/chipscope/timer_2" BEL "PLL/chipscope/timer_3" BEL
        "PLL/chipscope/timer_4" BEL "PLL/chipscope/timer_5" BEL
        "PLL/chipscope/timer_6" BEL "PLL/chipscope/timer_7" BEL
        "PLL/chipscope/timer_8" BEL "PLL/chipscope/timer_9" BEL
        "PLL/chipscope/timer_10" BEL "PLL/chipscope/timer_11" BEL
        "PLL/chipscope/timer_12" BEL "PLL/chipscope/timer_13" BEL
        "PLL/chipscope/timer_14" BEL "PLL/chipscope/timer_15" BEL
        "PLL/chipscope/timer_16" BEL "PLL/chipscope/timer_17" BEL
        "PLL/chipscope/timer_18" BEL "PLL/chipscope/timer_19" BEL
        "PLL/chipscope/timer_20" BEL "PLL/chipscope/timer_23" BEL
        "PLL/chipscope/timer_21" BEL "PLL/chipscope/timer_22" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_tq0/g_tw/0/u_tq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_tq0/g_tw/1/u_tq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_tq0/g_tw/2/u_tq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_tq0/g_tw/3/u_tq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/0/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/1/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/2/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/3/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/4/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/5/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/6/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/7/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/8/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/9/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/10/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/11/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/12/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/13/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/14/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/15/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/16/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/17/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/18/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/19/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/20/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/21/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/22/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/23/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/24/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/25/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/26/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/27/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/28/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/29/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/30/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/31/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/32/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/33/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/34/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/35/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/36/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/37/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/38/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/39/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/40/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/41/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/42/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/43/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/44/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/45/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/46/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/47/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/48/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/49/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/50/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/51/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/52/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/53/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/54/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/55/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/56/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/57/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/58/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/59/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/60/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/61/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/62/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/63/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/64/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/65/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/66/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/67/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/68/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/69/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/70/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/71/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/72/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/73/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/74/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/75/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/76/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/77/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/78/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/79/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/80/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/81/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/82/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/83/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/84/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/85/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/86/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/87/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/88/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/89/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/90/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/91/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/92/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/93/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/94/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/95/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/0/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/0/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/1/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/1/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/2/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/2/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/3/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/3/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/4/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/4/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/5/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/5/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/6/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/6/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/7/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/7/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/8/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/8/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/9/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/9/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/10/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/10/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/11/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/11/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/12/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/12/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/13/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/13/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/14/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/14/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/15/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/15/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/16/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/16/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/17/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/17/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/18/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/18/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/19/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/19/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/20/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/20/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/21/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/21/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/22/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/22/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/23/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/23/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/24/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/24/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/25/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/25/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/26/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/26/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/27/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/27/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/28/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/28/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/29/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/29/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/30/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/30/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/31/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/31/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/32/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/32/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/33/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/33/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/34/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/34/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/35/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/35/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/36/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/36/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/37/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/37/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/38/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/38/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/39/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/39/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/40/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/40/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/41/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/41/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/42/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/42/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/43/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/43/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/44/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/44/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/45/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/45/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/46/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/46/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/47/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/47/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/48/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/48/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/49/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/49/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/50/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/50/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/51/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/51/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/52/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/52/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/53/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/53/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/54/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/54/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/55/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/55/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/56/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/56/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/57/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/57/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/58/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/58/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/59/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/59/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/60/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/60/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/61/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/61/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/62/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/62/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/63/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/63/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/64/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/64/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/65/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/65/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/66/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/66/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/67/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/67/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/68/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/68/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/69/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/69/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/70/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/70/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/71/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/71/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/72/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/72/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/73/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/73/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/74/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/74/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/75/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/75/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/76/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/76/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/77/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/77/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/78/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/78/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/79/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/79/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/80/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/80/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/81/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/81/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/82/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/82/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/83/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/83/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/84/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/84/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/85/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/85/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/86/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/86/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/87/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/87/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/88/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/88/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/89/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/89/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/90/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/90/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/91/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/91/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/92/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/92/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/93/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/93/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/94/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/94/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/95/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/95/i_srlt_ne_0/ff"
        BEL "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_rst/u_por" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_rst/u_halt_xfer/u_dout0"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_rst/u_halt_xfer/u_dout1"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_rst/u_halt_xfer/u_dout"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_rst/u_halt_xfer/u_rfdre"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_rst/u_halt_xfer/u_gen_delay/1/u_fd"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_rst/u_halt_xfer/u_gen_delay/2/u_fd"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_rst/u_arm_xfer/u_dout0"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_rst/u_arm_xfer/u_dout1"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_rst/u_arm_xfer/u_dout"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_rst/u_arm_xfer/u_rfdre"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_rst/u_arm_xfer/u_gen_delay/1/u_fd"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_rst/u_arm_xfer/u_gen_delay/2/u_fd"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_rst/u_arm_xfer/u_gen_delay/3/u_fd"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_rst/u_arm_xfer/u_gen_delay/4/u_fd"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_rst/g_rst/0/u_rst"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_rst/g_rst/1/u_rst"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_rst/g_rst/2/u_rst"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_rst/g_rst/3/u_rst"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_rst/g_rst/4/u_rst"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_rst/g_rst/5/u_rst"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_rst/g_rst/6/u_rst"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_rst/g_rst/7/u_rst"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_trig/u_tm/g_nmu/0/u_m/u_mu/i_mut_gand/u_match/pd_rpm/i_twmod8_ne0/i_yes_rpm/i_oreg/u_oreg"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_trig/u_tm/g_nmu/0/u_m/u_mu/i_mut_gand/u_match/i_yes_ireg/f_tw/0/u_ireg"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_trig/u_tm/g_nmu/0/u_m/u_mu/i_mut_gand/u_match/i_yes_ireg/f_tw/1/u_ireg"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_trig/u_tm/g_nmu/0/u_m/u_mu/i_mut_gand/u_match/i_yes_ireg/f_tw/2/u_ireg"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_trig/u_tm/g_nmu/0/u_m/u_mu/i_mut_gand/u_match/i_yes_ireg/f_tw/3/u_ireg"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_trig/u_tm/g_nmu/0/u_m/u_mu/i_oreg/i_yes_oreg/u_oreg"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_trig/u_tm/g_nmu/0/u_m/i_mc_no/u_no_mc_reg"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_trig/u_tc/i_tseq_neq2/u_tc_equation/i_srlt_ne_1/i_nmu_1_to_4/u_tcl/i_outreg/u_dout"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_trig/u_tc/i_tseq_neq2/u_tc_equation/i_srlt_ne_1/i_nmu_1_to_4/u_trigq"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_trig/u_tc/i_storage_qual/u_storage_qual/i_srlt_ne_1/i_nmu_1_to_4/u_tcl/i_outreg/u_dout"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_trig/u_tc/i_storage_qual/u_storage_qual/i_srlt_ne_1/i_nmu_1_to_4/u_trigq"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_trig/u_tc/i_storage_qual/u_cap_dly"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_trig/f_no_tcmc/u_fdr"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_stat/u_dsl1/u_dout0"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_stat/u_dsl1/u_dout1"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_stat/u_dsl1/u_dout"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_stat/u_dsl1/u_rfdre"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_stat/u_dsl1/u_gen_delay/1/u_fd"
        BEL "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_stat/u_dsl2" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_stat/u_dsl3" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_stat/u_cr" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_stat/g_ns/12/u_nsq"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_stat/g_ns/11/u_nsq"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_stat/g_ns/10/u_nsq"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_stat/g_ns/9/u_nsq"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_stat/g_ns/8/u_nsq"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_stat/g_ns/7/u_nsq"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_stat/g_ns/6/u_nsq"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_stat/g_ns/5/u_nsq"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_stat/g_ns/4/u_nsq"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_stat/g_ns/3/u_nsq"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_stat/g_ns/2/u_nsq"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_stat/g_ns/1/u_nsq"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_stat/g_ns/0/u_nsq"
        BEL "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_stat/u_state1"
        BEL "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_stat/u_state0"
        BEL "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_stat/u_arm" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_stat/u_trigger" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_stat/u_full" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_stat/u_tsof" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_stat/u_ecr" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_stat/u_ece" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_stat/u_rising" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_intcap/f_cap_addr/0/u_icap_addr"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_intcap/f_cap_addr/0/u_cap_addr"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_intcap/f_cap_addr/1/u_icap_addr"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_intcap/f_cap_addr/1/u_cap_addr"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_intcap/f_cap_addr/2/u_icap_addr"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_intcap/f_cap_addr/2/u_cap_addr"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_intcap/f_cap_addr/3/u_icap_addr"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_intcap/f_cap_addr/3/u_cap_addr"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_intcap/f_cap_addr/4/u_icap_addr"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_intcap/f_cap_addr/4/u_cap_addr"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_intcap/f_cap_addr/5/u_icap_addr"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_intcap/f_cap_addr/5/u_cap_addr"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_intcap/f_cap_addr/6/u_icap_addr"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_intcap/f_cap_addr/6/u_cap_addr"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_intcap/f_cap_addr/7/u_icap_addr"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_intcap/f_cap_addr/7/u_cap_addr"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_intcap/f_cap_addr/8/u_icap_addr"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_intcap/f_cap_addr/8/u_cap_addr"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_intcap/f_cap_addr/9/u_icap_addr"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_intcap/f_cap_addr/9/u_cap_addr"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_intcap/f_cap_addr/10/u_icap_addr"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_intcap/f_cap_addr/10/u_cap_addr"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_intcap/f_cap_addr/11/u_icap_addr"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_intcap/f_cap_addr/11/u_cap_addr"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_intcap/f_cap_addr/12/u_icap_addr"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_intcap/f_cap_addr/12/u_cap_addr"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_no_tseq/i_srlt_ne_1/u_scnt/g/12/u_fdre"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_no_tseq/i_srlt_ne_1/u_scnt/g/11/u_fdre"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_no_tseq/i_srlt_ne_1/u_scnt/g/10/u_fdre"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_no_tseq/i_srlt_ne_1/u_scnt/g/9/u_fdre"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_no_tseq/i_srlt_ne_1/u_scnt/g/8/u_fdre"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_no_tseq/i_srlt_ne_1/u_scnt/g/7/u_fdre"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_no_tseq/i_srlt_ne_1/u_scnt/g/6/u_fdre"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_no_tseq/i_srlt_ne_1/u_scnt/g/5/u_fdre"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_no_tseq/i_srlt_ne_1/u_scnt/g/4/u_fdre"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_no_tseq/i_srlt_ne_1/u_scnt/g/3/u_fdre"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_no_tseq/i_srlt_ne_1/u_scnt/g/2/u_fdre"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_no_tseq/i_srlt_ne_1/u_scnt/g/1/u_fdre"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_no_tseq/i_srlt_ne_1/u_scnt/g/0/u_fdre"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_srlt_ne_1/u_wcnt/g/12/u_fdre"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_srlt_ne_1/u_wcnt/g/11/u_fdre"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_srlt_ne_1/u_wcnt/g/10/u_fdre"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_srlt_ne_1/u_wcnt/g/9/u_fdre"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_srlt_ne_1/u_wcnt/g/8/u_fdre"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_srlt_ne_1/u_wcnt/g/7/u_fdre"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_srlt_ne_1/u_wcnt/g/6/u_fdre"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_srlt_ne_1/u_wcnt/g/5/u_fdre"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_srlt_ne_1/u_wcnt/g/4/u_fdre"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_srlt_ne_1/u_wcnt/g/3/u_fdre"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_srlt_ne_1/u_wcnt/g/2/u_fdre"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_srlt_ne_1/u_wcnt/g/1/u_fdre"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_srlt_ne_1/u_wcnt/g/0/u_fdre"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_wcnt_hcmp_q"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_wcnt_lcmp_q"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_scnt_cmp_q"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_ns1/pd_rpm/i_srl_t2/i_yes_rpm/i_yes_oreg/out_reg"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_ns0/pd_rpm/i_srl_t2/i_yes_rpm/i_yes_oreg/out_reg"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_cdone/pd_rpm/i_srl_t2/i_yes_rpm/i_yes_oreg/out_reg"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_intcap_f/u_capwe0"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_intcap_f/u_capwe1"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_trig0"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_trig1"
        PIN
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/48/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1025.B_pins<53>"
        PIN
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/47/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1029.B_pins<53>"
        PIN
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/46/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1033.B_pins<53>"
        PIN
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/45/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1037.B_pins<53>"
        PIN
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/44/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1041.B_pins<53>"
        PIN
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/43/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1045.B_pins<53>"
        PIN
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/42/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1049.B_pins<53>"
        PIN
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/41/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1053.B_pins<53>"
        PIN
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/40/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1057.B_pins<53>"
        PIN
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/39/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1061.B_pins<53>"
        PIN
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/38/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1065.B_pins<53>"
        PIN
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/37/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1069.B_pins<53>"
        PIN
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/36/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1073.B_pins<53>"
        PIN
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/35/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1077.B_pins<53>"
        PIN
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/34/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1081.B_pins<53>"
        PIN
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/33/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1085.B_pins<53>"
        PIN
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/32/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1089.B_pins<53>"
        PIN
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/31/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1093.B_pins<53>"
        PIN
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/30/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1097.B_pins<53>"
        PIN
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/29/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1101.B_pins<53>"
        PIN
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/28/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1105.B_pins<53>"
        PIN
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/27/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1109.B_pins<53>"
        PIN
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/26/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1113.B_pins<53>"
        PIN
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/25/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1117.B_pins<53>"
        PIN
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/24/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1121.B_pins<53>"
        PIN
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/23/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1125.B_pins<53>"
        PIN
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/22/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1129.B_pins<53>"
        PIN
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/21/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1133.B_pins<53>"
        PIN
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/20/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1137.B_pins<53>"
        PIN
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/19/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1141.B_pins<53>"
        PIN
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/18/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1145.B_pins<53>"
        PIN
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/17/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1149.B_pins<53>"
        PIN
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/16/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1153.B_pins<53>"
        PIN
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/15/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1157.B_pins<53>"
        PIN
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/14/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1161.B_pins<53>"
        PIN
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/13/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1165.B_pins<53>"
        PIN
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/12/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1169.B_pins<53>"
        PIN
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/11/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1173.B_pins<53>"
        PIN
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/10/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1177.B_pins<53>"
        PIN
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/9/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1181.B_pins<53>"
        PIN
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/8/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1185.B_pins<53>"
        PIN
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/7/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1189.B_pins<53>"
        PIN
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/6/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1193.B_pins<53>"
        PIN
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/5/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1197.B_pins<53>"
        PIN
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/4/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1201.B_pins<53>"
        PIN
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/3/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1205.B_pins<53>"
        PIN
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/2/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1209.B_pins<53>"
        PIN
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/1/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1213.B_pins<53>"
        PIN
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/0/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1217.B_pins<53>"
        BEL "PLL/chipscope/i_ila_2CH/ila_2CH/i_tq0/g_tw/0/u_tq" BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_tq0/g_tw/1/u_tq" BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_tq0/g_tw/2/u_tq" BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_tq0/g_tw/3/u_tq" BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_dq/g_dw/0/u_dq" BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_dq/g_dw/1/u_dq" BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_dq/g_dw/2/u_dq" BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_dq/g_dw/3/u_dq" BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_dq/g_dw/4/u_dq" BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_dq/g_dw/5/u_dq" BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_dq/g_dw/6/u_dq" BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_dq/g_dw/7/u_dq" BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_dq/g_dw/8/u_dq" BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_dq/g_dw/9/u_dq" BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_dq/g_dw/10/u_dq" BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_dq/g_dw/11/u_dq" BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_dq/g_dw/12/u_dq" BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_dq/g_dw/13/u_dq" BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_dq/g_dw/14/u_dq" BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_dq/g_dw/15/u_dq" BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_dq/g_dw/16/u_dq" BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_dq/g_dw/17/u_dq" BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_dq/g_dw/18/u_dq" BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_dq/g_dw/19/u_dq" BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_dq/g_dw/20/u_dq" BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_dq/g_dw/21/u_dq" BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_dq/g_dw/22/u_dq" BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_dq/g_dw/23/u_dq" BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_dq/g_dw/24/u_dq" BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_dq/g_dw/25/u_dq" BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_dq/g_dw/26/u_dq" BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_dq/g_dw/27/u_dq" BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_dq/g_dw/28/u_dq" BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_dq/g_dw/29/u_dq" BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_dq/g_dw/30/u_dq" BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_dq/g_dw/31/u_dq" BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_dq/g_dw/32/u_dq" BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_dq/g_dw/33/u_dq" BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_dq/g_dw/34/u_dq" BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_dq/g_dw/35/u_dq" BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_dq/g_dw/36/u_dq" BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_dq/g_dw/37/u_dq" BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_dq/g_dw/38/u_dq" BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_dq/g_dw/39/u_dq" BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_dq/g_dw/40/u_dq" BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_dq/g_dw/41/u_dq" BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_dq/g_dw/42/u_dq" BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_dq/g_dw/43/u_dq" BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_dq/g_dw/44/u_dq" BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_dq/g_dw/45/u_dq" BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_dq/g_dw/46/u_dq" BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_dq/g_dw/47/u_dq" BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/0/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/0/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/1/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/1/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/2/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/2/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/3/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/3/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/4/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/4/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/5/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/5/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/6/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/6/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/7/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/7/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/8/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/8/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/9/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/9/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/10/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/10/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/11/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/11/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/12/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/12/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/13/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/13/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/14/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/14/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/15/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/15/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/16/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/16/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/17/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/17/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/18/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/18/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/19/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/19/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/20/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/20/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/21/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/21/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/22/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/22/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/23/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/23/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/24/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/24/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/25/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/25/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/26/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/26/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/27/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/27/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/28/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/28/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/29/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/29/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/30/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/30/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/31/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/31/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/32/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/32/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/33/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/33/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/34/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/34/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/35/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/35/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/36/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/36/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/37/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/37/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/38/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/38/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/39/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/39/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/40/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/40/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/41/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/41/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/42/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/42/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/43/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/43/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/44/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/44/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/45/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/45/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/46/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/46/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/47/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/47/i_srlt_ne_0/ff"
        BEL "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_rst/u_por" BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_rst/u_halt_xfer/u_dout0"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_rst/u_halt_xfer/u_dout1"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_rst/u_halt_xfer/u_dout"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_rst/u_halt_xfer/u_rfdre"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_rst/u_halt_xfer/u_gen_delay/1/u_fd"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_rst/u_halt_xfer/u_gen_delay/2/u_fd"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_rst/u_arm_xfer/u_dout0"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_rst/u_arm_xfer/u_dout1"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_rst/u_arm_xfer/u_dout"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_rst/u_arm_xfer/u_rfdre"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_rst/u_arm_xfer/u_gen_delay/1/u_fd"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_rst/u_arm_xfer/u_gen_delay/2/u_fd"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_rst/u_arm_xfer/u_gen_delay/3/u_fd"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_rst/u_arm_xfer/u_gen_delay/4/u_fd"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_rst/g_rst/0/u_rst"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_rst/g_rst/1/u_rst"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_rst/g_rst/2/u_rst"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_rst/g_rst/3/u_rst"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_rst/g_rst/4/u_rst"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_rst/g_rst/5/u_rst"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_rst/g_rst/6/u_rst"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_rst/g_rst/7/u_rst"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_trig/u_tm/g_nmu/0/u_m/u_mu/i_mut_gand/u_match/pd_rpm/i_twmod8_ne0/i_yes_rpm/i_oreg/u_oreg"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_trig/u_tm/g_nmu/0/u_m/u_mu/i_mut_gand/u_match/i_yes_ireg/f_tw/0/u_ireg"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_trig/u_tm/g_nmu/0/u_m/u_mu/i_mut_gand/u_match/i_yes_ireg/f_tw/1/u_ireg"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_trig/u_tm/g_nmu/0/u_m/u_mu/i_mut_gand/u_match/i_yes_ireg/f_tw/2/u_ireg"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_trig/u_tm/g_nmu/0/u_m/u_mu/i_mut_gand/u_match/i_yes_ireg/f_tw/3/u_ireg"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_trig/u_tm/g_nmu/0/u_m/u_mu/i_oreg/i_yes_oreg/u_oreg"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_trig/u_tm/g_nmu/0/u_m/i_mc_no/u_no_mc_reg"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_trig/u_tc/i_tseq_neq2/u_tc_equation/i_srlt_ne_1/i_nmu_1_to_4/u_tcl/i_outreg/u_dout"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_trig/u_tc/i_tseq_neq2/u_tc_equation/i_srlt_ne_1/i_nmu_1_to_4/u_trigq"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_trig/u_tc/i_storage_qual/u_storage_qual/i_srlt_ne_1/i_nmu_1_to_4/u_tcl/i_outreg/u_dout"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_trig/u_tc/i_storage_qual/u_storage_qual/i_srlt_ne_1/i_nmu_1_to_4/u_trigq"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_trig/u_tc/i_storage_qual/u_cap_dly"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_trig/f_no_tcmc/u_fdr"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_stat/u_dsl1/u_dout0"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_stat/u_dsl1/u_dout1"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_stat/u_dsl1/u_dout"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_stat/u_dsl1/u_rfdre"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_stat/u_dsl1/u_gen_delay/1/u_fd"
        BEL "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_stat/u_dsl2" BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_stat/u_dsl3" BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_stat/u_cr" BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_stat/g_ns/12/u_nsq"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_stat/g_ns/11/u_nsq"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_stat/g_ns/10/u_nsq"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_stat/g_ns/9/u_nsq"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_stat/g_ns/8/u_nsq"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_stat/g_ns/7/u_nsq"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_stat/g_ns/6/u_nsq"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_stat/g_ns/5/u_nsq"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_stat/g_ns/4/u_nsq"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_stat/g_ns/3/u_nsq"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_stat/g_ns/2/u_nsq"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_stat/g_ns/1/u_nsq"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_stat/g_ns/0/u_nsq"
        BEL "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_stat/u_state1"
        BEL "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_stat/u_state0"
        BEL "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_stat/u_arm" BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_stat/u_trigger" BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_stat/u_full" BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_stat/u_tsof" BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_stat/u_ecr" BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_stat/u_ece" BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_stat/u_rising" BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_intcap/f_cap_addr/0/u_icap_addr"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_intcap/f_cap_addr/0/u_cap_addr"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_intcap/f_cap_addr/1/u_icap_addr"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_intcap/f_cap_addr/1/u_cap_addr"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_intcap/f_cap_addr/2/u_icap_addr"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_intcap/f_cap_addr/2/u_cap_addr"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_intcap/f_cap_addr/3/u_icap_addr"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_intcap/f_cap_addr/3/u_cap_addr"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_intcap/f_cap_addr/4/u_icap_addr"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_intcap/f_cap_addr/4/u_cap_addr"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_intcap/f_cap_addr/5/u_icap_addr"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_intcap/f_cap_addr/5/u_cap_addr"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_intcap/f_cap_addr/6/u_icap_addr"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_intcap/f_cap_addr/6/u_cap_addr"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_intcap/f_cap_addr/7/u_icap_addr"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_intcap/f_cap_addr/7/u_cap_addr"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_intcap/f_cap_addr/8/u_icap_addr"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_intcap/f_cap_addr/8/u_cap_addr"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_intcap/f_cap_addr/9/u_icap_addr"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_intcap/f_cap_addr/9/u_cap_addr"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_intcap/f_cap_addr/10/u_icap_addr"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_intcap/f_cap_addr/10/u_cap_addr"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_intcap/f_cap_addr/11/u_icap_addr"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_intcap/f_cap_addr/11/u_cap_addr"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_intcap/f_cap_addr/12/u_icap_addr"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_intcap/f_cap_addr/12/u_cap_addr"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_no_tseq/i_srlt_ne_1/u_scnt/g/12/u_fdre"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_no_tseq/i_srlt_ne_1/u_scnt/g/11/u_fdre"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_no_tseq/i_srlt_ne_1/u_scnt/g/10/u_fdre"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_no_tseq/i_srlt_ne_1/u_scnt/g/9/u_fdre"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_no_tseq/i_srlt_ne_1/u_scnt/g/8/u_fdre"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_no_tseq/i_srlt_ne_1/u_scnt/g/7/u_fdre"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_no_tseq/i_srlt_ne_1/u_scnt/g/6/u_fdre"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_no_tseq/i_srlt_ne_1/u_scnt/g/5/u_fdre"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_no_tseq/i_srlt_ne_1/u_scnt/g/4/u_fdre"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_no_tseq/i_srlt_ne_1/u_scnt/g/3/u_fdre"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_no_tseq/i_srlt_ne_1/u_scnt/g/2/u_fdre"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_no_tseq/i_srlt_ne_1/u_scnt/g/1/u_fdre"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_no_tseq/i_srlt_ne_1/u_scnt/g/0/u_fdre"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_srlt_ne_1/u_wcnt/g/12/u_fdre"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_srlt_ne_1/u_wcnt/g/11/u_fdre"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_srlt_ne_1/u_wcnt/g/10/u_fdre"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_srlt_ne_1/u_wcnt/g/9/u_fdre"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_srlt_ne_1/u_wcnt/g/8/u_fdre"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_srlt_ne_1/u_wcnt/g/7/u_fdre"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_srlt_ne_1/u_wcnt/g/6/u_fdre"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_srlt_ne_1/u_wcnt/g/5/u_fdre"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_srlt_ne_1/u_wcnt/g/4/u_fdre"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_srlt_ne_1/u_wcnt/g/3/u_fdre"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_srlt_ne_1/u_wcnt/g/2/u_fdre"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_srlt_ne_1/u_wcnt/g/1/u_fdre"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_srlt_ne_1/u_wcnt/g/0/u_fdre"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_wcnt_hcmp_q"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_wcnt_lcmp_q"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_scnt_cmp_q"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_ns1/pd_rpm/i_srl_t2/i_yes_rpm/i_yes_oreg/out_reg"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_ns0/pd_rpm/i_srl_t2/i_yes_rpm/i_yes_oreg/out_reg"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_cdone/pd_rpm/i_srl_t2/i_yes_rpm/i_yes_oreg/out_reg"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_intcap_f/u_capwe0"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_intcap_f/u_capwe1"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_trig0"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_trig1"
        PIN
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/24/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim844.B_pins<53>"
        PIN
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/23/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim848.B_pins<53>"
        PIN
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/22/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim852.B_pins<53>"
        PIN
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/21/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim856.B_pins<53>"
        PIN
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/20/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim860.B_pins<53>"
        PIN
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/19/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim864.B_pins<53>"
        PIN
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/18/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim868.B_pins<53>"
        PIN
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/17/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim872.B_pins<53>"
        PIN
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/16/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim876.B_pins<53>"
        PIN
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/15/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim880.B_pins<53>"
        PIN
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/14/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim884.B_pins<53>"
        PIN
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/13/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim888.B_pins<53>"
        PIN
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/12/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim892.B_pins<53>"
        PIN
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/11/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim896.B_pins<53>"
        PIN
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/10/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim900.B_pins<53>"
        PIN
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/9/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim904.B_pins<53>"
        PIN
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/8/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim908.B_pins<53>"
        PIN
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/7/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim912.B_pins<53>"
        PIN
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/6/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim916.B_pins<53>"
        PIN
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/5/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim920.B_pins<53>"
        PIN
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/4/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim924.B_pins<53>"
        PIN
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/3/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim928.B_pins<53>"
        PIN
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/2/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim932.B_pins<53>"
        PIN
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/1/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim936.B_pins<53>"
        PIN
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/0/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim940.B_pins<53>"
        BEL "PLL/chipscope/trig_timer_2" BEL "PLL/chipscope/trig_timer_0" BEL
        "PLL/chipscope/trig_timer_1" BEL "PLL/chipscope/trig_timer_5" BEL
        "PLL/chipscope/trig_timer_3" BEL "PLL/chipscope/trig_timer_4" BEL
        "PLL/chipscope/trig_timer_8" BEL "PLL/chipscope/trig_timer_6" BEL
        "PLL/chipscope/trig_timer_7" BEL "PLL/chipscope/trig_timer_11" BEL
        "PLL/chipscope/trig_timer_9" BEL "PLL/chipscope/trig_timer_10" BEL
        "PLL/chipscope/trig_timer_14" BEL "PLL/chipscope/trig_timer_12" BEL
        "PLL/chipscope/trig_timer_13" BEL "PLL/chipscope/trig_timer_17" BEL
        "PLL/chipscope/trig_timer_15" BEL "PLL/chipscope/trig_timer_16" BEL
        "PLL/chipscope/trig_timer_20" BEL "PLL/chipscope/trig_timer_18" BEL
        "PLL/chipscope/trig_timer_19" BEL "PLL/chipscope/trig_timer_23" BEL
        "PLL/chipscope/trig_timer_21" BEL "PLL/chipscope/trig_timer_22" BEL
        "ADC_A_buf_13" BEL "ADC_B_buf_13" BEL "ADC_C_buf_13" BEL "PLL/n6_23_1"
        BEL "PLL/n6_23_2" BEL "DIO<8>" BEL "ddr2high_ldm_pad_o" BEL
        "ddr2low_ldm_pad_o" BEL "ddr2high_csn_pad_o" BEL "ddr2high_cke_pad_o"
        BEL "ddr2low_cke_pad_o" BEL "ddr2high_casn_pad_o" BEL
        "ddr2high_wen_pad_o" BEL "ddr2low_casn_pad_o" BEL "ddr2low_wen_pad_o"
        BEL "sbc_irq_pad_o" BEL "ddr2high_clkn_pad_o" BEL "ddr2high_odt_pad_o"
        BEL "ddr2high_rasn_pad_o" BEL "lemo_il_pad_o" BEL "ddr2high_udm_pad_o"
        BEL "ddr2low_clkn_pad_o" BEL "ddr2low_odt_pad_o" BEL
        "ddr2low_rasn_pad_o" BEL "ddr2high_clk_pad_o" BEL "ddr2low_udm_pad_o"
        BEL "sbc_rst_pad_o" BEL "ddr2low_clk_pad_o" BEL "DIR<5>" BEL "DIR<4>"
        BEL "DIR<3>" BEL "DIR<2>" BEL "ddr2high_addr_pad_o<12>" BEL
        "ddr2high_addr_pad_o<11>" BEL "ddr2high_addr_pad_o<10>" BEL
        "ddr2high_addr_pad_o<9>" BEL "ddr2high_addr_pad_o<8>" BEL
        "ddr2high_addr_pad_o<7>" BEL "ddr2high_addr_pad_o<6>" BEL
        "ddr2high_addr_pad_o<5>" BEL "ddr2high_addr_pad_o<4>" BEL
        "ddr2high_addr_pad_o<3>" BEL "ddr2high_addr_pad_o<2>" BEL
        "ddr2high_addr_pad_o<1>" BEL "ddr2high_addr_pad_o<0>" BEL
        "ddr2low_addr_pad_o<12>" BEL "ddr2low_addr_pad_o<11>" BEL
        "ddr2low_addr_pad_o<10>" BEL "ddr2low_addr_pad_o<9>" BEL
        "ddr2low_addr_pad_o<8>" BEL "ddr2low_addr_pad_o<7>" BEL
        "ddr2low_addr_pad_o<6>" BEL "ddr2low_addr_pad_o<5>" BEL
        "ddr2low_addr_pad_o<4>" BEL "ddr2low_addr_pad_o<3>" BEL
        "ddr2low_addr_pad_o<2>" BEL "ddr2low_addr_pad_o<1>" BEL
        "ddr2low_addr_pad_o<0>" BEL "ddr2high_bank_pad_o<1>" BEL
        "ddr2high_bank_pad_o<0>" BEL "ddr2low_bank_pad_o<1>" BEL
        "ddr2low_bank_pad_o<0>";
TIMEGRP adc_clk_ppad_i = BEL "ADC_A_buf_0" BEL "ADC_A_buf_1" BEL "ADC_A_buf_2"
        BEL "ADC_A_buf_3" BEL "ADC_A_buf_4" BEL "ADC_A_buf_5" BEL
        "ADC_A_buf_6" BEL "ADC_A_buf_7" BEL "ADC_A_buf_8" BEL "ADC_A_buf_9"
        BEL "ADC_A_buf_10" BEL "ADC_A_buf_11" BEL "ADC_A_buf_12" BEL
        "ADC_B_buf_0" BEL "ADC_B_buf_1" BEL "ADC_B_buf_2" BEL "ADC_B_buf_3"
        BEL "ADC_B_buf_4" BEL "ADC_B_buf_5" BEL "ADC_B_buf_6" BEL
        "ADC_B_buf_7" BEL "ADC_B_buf_8" BEL "ADC_B_buf_9" BEL "ADC_B_buf_10"
        BEL "ADC_B_buf_11" BEL "ADC_B_buf_12" BEL "ADC_C_buf_0" BEL
        "ADC_C_buf_1" BEL "ADC_C_buf_2" BEL "ADC_C_buf_3" BEL "ADC_C_buf_4"
        BEL "ADC_C_buf_5" BEL "ADC_C_buf_6" BEL "ADC_C_buf_7" BEL
        "ADC_C_buf_8" BEL "ADC_C_buf_9" BEL "ADC_C_buf_10" BEL "ADC_C_buf_11"
        BEL "ADC_C_buf_12" BEL "edge_reg_0" BEL "edge_reg_1" BEL "edge_reg_2"
        BEL "edge_reg_3" PIN "PLL/C_TABLE/B6.A_pins<53>" PIN
        "PLL/C_TABLE/B6.B_pins<53>" PIN "PLL/C_TABLE/B9.A_pins<53>" PIN
        "PLL/C_TABLE/B9.B_pins<53>" PIN "PLL/C_TABLE/B12.A_pins<53>" PIN
        "PLL/C_TABLE/B12.B_pins<53>" PIN "PLL/C_TABLE/B15.A_pins<53>" PIN
        "PLL/C_TABLE/B15.B_pins<53>" BEL "PLL/C_TABLE/BU21" BEL
        "PLL/C_TABLE/BU24" PIN "PLL/C_TABLE/B181.A_pins<53>" PIN
        "PLL/C_TABLE/B181.B_pins<53>" PIN "PLL/C_TABLE/B184.A_pins<53>" PIN
        "PLL/C_TABLE/B184.B_pins<53>" PIN "PLL/C_TABLE/B187.A_pins<53>" PIN
        "PLL/C_TABLE/B187.B_pins<53>" PIN "PLL/C_TABLE/B190.A_pins<53>" PIN
        "PLL/C_TABLE/B190.B_pins<53>" BEL "PLL/C_TABLE/BU196" BEL
        "PLL/C_TABLE/BU199" PIN "PLL/C_TABLE/B356.A_pins<53>" PIN
        "PLL/C_TABLE/B356.B_pins<53>" PIN "PLL/C_TABLE/B359.A_pins<53>" PIN
        "PLL/C_TABLE/B359.B_pins<53>" PIN "PLL/C_TABLE/B362.A_pins<53>" PIN
        "PLL/C_TABLE/B362.B_pins<53>" PIN "PLL/C_TABLE/B365.A_pins<53>" PIN
        "PLL/C_TABLE/B365.B_pins<53>" BEL "PLL/C_TABLE/BU371" BEL
        "PLL/C_TABLE/BU374" PIN "PLL/C_TABLE/B531.A_pins<53>" PIN
        "PLL/C_TABLE/B531.B_pins<53>" PIN "PLL/C_TABLE/B535.A_pins<53>" PIN
        "PLL/C_TABLE/B535.B_pins<53>" PIN "PLL/C_TABLE/B539.A_pins<53>" PIN
        "PLL/C_TABLE/B539.B_pins<53>" PIN "PLL/ST_TABLE/B6.A_pins<53>" PIN
        "PLL/ST_TABLE/B6.B_pins<53>" PIN "PLL/HC_TABLE/B6.A_pins<53>" PIN
        "PLL/HC_TABLE/B6.B_pins<53>" PIN "PLL/INJ_TABLE/B6.A_pins<53>" PIN
        "PLL/INJ_TABLE/B6.B_pins<53>" PIN "PLL/ph_table_0/B6.A_pins<53>" PIN
        "PLL/ph_table_0/B6.B_pins<53>" PIN "PLL/ph_table_0/B10.A_pins<53>" PIN
        "PLL/ph_table_0/B10.B_pins<53>" BEL "PLL/C_timer_stop" BEL
        "PLL/HC_timing_rising" BEL "PLL/ST_edg_det_0" BEL
        "PLL/inj_trig_rising" BEL "PLL/ST_timing_rising" BEL
        "PLL/HC_tim_edg_det_0" BEL "PLL/filter1_in_0" BEL "PLL/filter1_in_1"
        BEL "PLL/filter1_in_2" BEL "PLL/filter1_in_3" BEL "PLL/filter1_in_4"
        BEL "PLL/filter1_in_5" BEL "PLL/filter1_in_6" BEL "PLL/filter1_in_7"
        BEL "PLL/filter1_in_8" BEL "PLL/filter1_in_9" BEL "PLL/filter1_in_10"
        BEL "PLL/filter1_in_11" BEL "PLL/filter1_in_12" BEL
        "PLL/filter1_in_13" BEL "PLL/PT_MSB_rising" BEL
        "PLL/inj_trig_edg_det_0" BEL "PLL/change_PT" BEL "PLL/clk62" BEL
        "PLL/ST_edg_det_1" BEL "PLL/HC_tim_edg_det_1" BEL "PLL/HC_temp" BEL
        "PLL/HC_synch" BEL "PLL/inj_trig_edg_det_1" BEL "PLL/ST_tab_ST_addr_0"
        BEL "PLL/ST_tab_ST_addr_1" BEL "PLL/ST_tab_ST_addr_2" BEL
        "PLL/SDRAM_ST_addr_0" BEL "PLL/SDRAM_ST_addr_1" BEL
        "PLL/SDRAM_ST_addr_2" BEL "PLL/SDRAM_ST_addr_3" BEL
        "PLL/SDRAM_ST_addr_4" BEL "PLL/SDRAM_ST_addr_5" BEL
        "PLL/SDRAM_ST_addr_6" BEL "PLL/SDRAM_ST_addr_7" BEL
        "PLL/SDRAM_ST_addr_8" BEL "PLL/SDRAM_ST_addr_9" BEL
        "PLL/SDRAM_ST_addr_10" BEL "PLL/SDRAM_ST_addr_11" BEL
        "PLL/SDRAM_ST_addr_12" BEL "PLL/SDRAM_ST_addr_13" BEL
        "PLL/SDRAM_ST_addr_14" BEL "PLL/SDRAM_ST_addr_15" BEL
        "PLL/SDRAM_ST_addr_16" BEL "PLL/SDRAM_ST_addr_17" BEL
        "PLL/SDRAM_ST_addr_18" BEL "PLL/SDRAM_ST_addr_19" BEL
        "PLL/SDRAM_ST_addr_20" BEL "PLL/SDRAM_ST_addr_21" BEL
        "PLL/SDRAM_ST_addr_22" BEL "PLL/SDRAM_ST_addr_23" BEL
        "PLL/SDRAM_ST_addr_24" BEL "PLL/SDRAM_ST_addr_25" BEL
        "PLL/HC_tab_ST_addr_0" BEL "PLL/HC_tab_ST_addr_1" BEL
        "PLL/HC_tab_ST_addr_2" BEL "PLL/HC_tab_ST_addr_3" BEL
        "PLL/HC_tab_ST_addr_4" BEL "PLL/C_tab_ST_addr_0" BEL
        "PLL/C_tab_ST_addr_1" BEL "PLL/C_tab_ST_addr_2" BEL
        "PLL/C_tab_ST_addr_3" BEL "PLL/C_tab_ST_addr_4" BEL
        "PLL/C_tab_ST_addr_5" BEL "PLL/C_tab_ST_addr_6" BEL
        "PLL/C_tab_ST_addr_7" BEL "PLL/C_tab_ST_addr_8" BEL
        "PLL/C_tab_ST_addr_9" BEL "PLL/C_tab_ST_addr_10" BEL
        "PLL/C_tab_ST_addr_11" BEL "PLL/C_tab_ST_addr_12" BEL
        "PLL/INJ_tab_ST_addr_0" BEL "PLL/INJ_tab_ST_addr_1" BEL
        "PLL/INJ_tab_ST_addr_2" BEL "PLL/x0_0" BEL "PLL/x0_1" BEL "PLL/x0_2"
        BEL "PLL/x0_3" BEL "PLL/x0_4" BEL "PLL/x0_5" BEL "PLL/x0_6" BEL
        "PLL/x0_7" BEL "PLL/x0_8" BEL "PLL/x0_9" BEL "PLL/x0_10" BEL
        "PLL/x0_11" BEL "PLL/x0_12" BEL "PLL/x0_13" BEL "PLL/x0_14" BEL
        "PLL/x0_15" BEL "PLL/x0_16" BEL "PLL/x0_17" BEL "PLL/x0_18" BEL
        "PLL/x0_19" BEL "PLL/x0_20" BEL "PLL/x0_21" BEL "PLL/x0_22" BEL
        "PLL/x0_23" BEL "PLL/x1_0" BEL "PLL/x1_1" BEL "PLL/x1_2" BEL
        "PLL/x1_3" BEL "PLL/x1_4" BEL "PLL/x1_5" BEL "PLL/x1_6" BEL "PLL/x1_7"
        BEL "PLL/x1_8" BEL "PLL/x1_9" BEL "PLL/x1_10" BEL "PLL/x1_11" BEL
        "PLL/x1_12" BEL "PLL/x1_13" BEL "PLL/x1_14" BEL "PLL/x1_15" BEL
        "PLL/x1_16" BEL "PLL/x1_17" BEL "PLL/x1_18" BEL "PLL/x1_19" BEL
        "PLL/x1_20" BEL "PLL/x1_21" BEL "PLL/x1_22" BEL "PLL/x1_23" BEL
        "PLL/x2_0" BEL "PLL/x2_1" BEL "PLL/x2_2" BEL "PLL/x2_3" BEL "PLL/x2_4"
        BEL "PLL/x2_5" BEL "PLL/x2_6" BEL "PLL/x2_7" BEL "PLL/x2_8" BEL
        "PLL/x2_9" BEL "PLL/x2_10" BEL "PLL/x2_11" BEL "PLL/x2_12" BEL
        "PLL/x2_13" BEL "PLL/x2_14" BEL "PLL/x2_15" BEL "PLL/x2_16" BEL
        "PLL/x2_17" BEL "PLL/x2_18" BEL "PLL/x2_19" BEL "PLL/x2_20" BEL
        "PLL/x2_21" BEL "PLL/x2_22" BEL "PLL/x2_23" BEL "PLL/n2_0" BEL
        "PLL/n2_1" BEL "PLL/n2_2" BEL "PLL/n2_3" BEL "PLL/n2_4" BEL "PLL/n2_5"
        BEL "PLL/n2_6" BEL "PLL/n2_7" BEL "PLL/n2_8" BEL "PLL/n2_9" BEL
        "PLL/n2_10" BEL "PLL/n2_11" BEL "PLL/n2_12" BEL "PLL/n2_13" BEL
        "PLL/n2_14" BEL "PLL/n2_15" BEL "PLL/n2_16" BEL "PLL/n2_17" BEL
        "PLL/n2_18" BEL "PLL/n2_19" BEL "PLL/n2_20" BEL "PLL/n2_21" BEL
        "PLL/n2_22" BEL "PLL/n2_23" BEL "PLL/y1_0" BEL "PLL/y1_1" BEL
        "PLL/y1_2" BEL "PLL/y1_3" BEL "PLL/y1_4" BEL "PLL/y1_5" BEL "PLL/y1_6"
        BEL "PLL/y1_7" BEL "PLL/y1_8" BEL "PLL/y1_9" BEL "PLL/y1_10" BEL
        "PLL/y1_11" BEL "PLL/y1_12" BEL "PLL/y1_13" BEL "PLL/y1_14" BEL
        "PLL/y1_15" BEL "PLL/y1_16" BEL "PLL/y1_17" BEL "PLL/y1_18" BEL
        "PLL/y1_19" BEL "PLL/y1_20" BEL "PLL/y1_21" BEL "PLL/y1_22" BEL
        "PLL/y1_23" BEL "PLL/y0_0" BEL "PLL/y0_1" BEL "PLL/y0_2" BEL
        "PLL/y0_3" BEL "PLL/y0_4" BEL "PLL/y0_5" BEL "PLL/y0_6" BEL "PLL/y0_7"
        BEL "PLL/y0_8" BEL "PLL/y0_9" BEL "PLL/y0_10" BEL "PLL/y0_11" BEL
        "PLL/y0_12" BEL "PLL/y0_13" BEL "PLL/y0_14" BEL "PLL/y0_15" BEL
        "PLL/y0_16" BEL "PLL/y0_17" BEL "PLL/y0_18" BEL "PLL/y0_19" BEL
        "PLL/y0_20" BEL "PLL/y0_21" BEL "PLL/y0_22" BEL "PLL/y0_23" BEL
        "PLL/y2_0" BEL "PLL/y2_1" BEL "PLL/y2_2" BEL "PLL/y2_3" BEL "PLL/y2_4"
        BEL "PLL/y2_5" BEL "PLL/y2_6" BEL "PLL/y2_7" BEL "PLL/y2_8" BEL
        "PLL/y2_9" BEL "PLL/y2_10" BEL "PLL/y2_11" BEL "PLL/y2_12" BEL
        "PLL/y2_13" BEL "PLL/y2_14" BEL "PLL/y2_15" BEL "PLL/y2_16" BEL
        "PLL/y2_17" BEL "PLL/y2_18" BEL "PLL/y2_19" BEL "PLL/y2_20" BEL
        "PLL/y2_21" BEL "PLL/y2_22" BEL "PLL/y2_23" BEL "PLL/n3_0" BEL
        "PLL/n3_1" BEL "PLL/n3_2" BEL "PLL/n3_3" BEL "PLL/n3_4" BEL "PLL/n3_5"
        BEL "PLL/n3_6" BEL "PLL/n3_7" BEL "PLL/n3_8" BEL "PLL/n3_9" BEL
        "PLL/n3_10" BEL "PLL/n3_11" BEL "PLL/n3_12" BEL "PLL/n3_13" BEL
        "PLL/n3_14" BEL "PLL/n3_15" BEL "PLL/n3_16" BEL "PLL/n3_17" BEL
        "PLL/n3_18" BEL "PLL/n3_19" BEL "PLL/n3_20" BEL "PLL/n3_21" BEL
        "PLL/n3_22" BEL "PLL/n3_23" BEL "PLL/result2_tmp_0" BEL
        "PLL/result2_tmp_1" BEL "PLL/result2_tmp_2" BEL "PLL/result2_tmp_3"
        BEL "PLL/result2_tmp_4" BEL "PLL/result2_tmp_5" BEL
        "PLL/result2_tmp_6" BEL "PLL/result2_tmp_7" BEL "PLL/result2_tmp_8"
        BEL "PLL/result2_tmp_9" BEL "PLL/result2_tmp_10" BEL
        "PLL/result2_tmp_11" BEL "PLL/result2_tmp_12" BEL "PLL/result2_tmp_13"
        BEL "PLL/result2_tmp_14" BEL "PLL/result2_tmp_15" BEL
        "PLL/result1_tmp_0" BEL "PLL/result1_tmp_1" BEL "PLL/result1_tmp_2"
        BEL "PLL/result1_tmp_3" BEL "PLL/result1_tmp_4" BEL
        "PLL/result1_tmp_5" BEL "PLL/result1_tmp_6" BEL "PLL/result1_tmp_7"
        BEL "PLL/result1_tmp_8" BEL "PLL/result1_tmp_9" BEL
        "PLL/result1_tmp_10" BEL "PLL/result1_tmp_11" BEL "PLL/result1_tmp_12"
        BEL "PLL/result1_tmp_13" BEL "PLL/result1_tmp_14" BEL
        "PLL/result1_tmp_15" BEL "PLL/result0_tmp_0" BEL "PLL/result0_tmp_1"
        BEL "PLL/result0_tmp_2" BEL "PLL/result0_tmp_3" BEL
        "PLL/result0_tmp_4" BEL "PLL/result0_tmp_5" BEL "PLL/result0_tmp_6"
        BEL "PLL/result0_tmp_7" BEL "PLL/result0_tmp_8" BEL
        "PLL/result0_tmp_9" BEL "PLL/result0_tmp_10" BEL "PLL/result0_tmp_11"
        BEL "PLL/result0_tmp_12" BEL "PLL/result0_tmp_13" BEL
        "PLL/result0_tmp_14" BEL "PLL/result0_tmp_15" BEL "PLL/s4_0" BEL
        "PLL/s4_1" BEL "PLL/s4_2" BEL "PLL/s4_3" BEL "PLL/s4_4" BEL "PLL/s4_5"
        BEL "PLL/s4_6" BEL "PLL/s4_7" BEL "PLL/s4_8" BEL "PLL/s4_9" BEL
        "PLL/s4_10" BEL "PLL/s4_11" BEL "PLL/s4_12" BEL "PLL/s4_13" BEL
        "PLL/s4_14" BEL "PLL/s4_15" BEL "PLL/s4_16" BEL "PLL/s4_17" BEL
        "PLL/s4_18" BEL "PLL/s4_19" BEL "PLL/s4_20" BEL "PLL/s4_21" BEL
        "PLL/s4_22" BEL "PLL/s4_23" BEL "PLL/n4_0" BEL "PLL/n4_1" BEL
        "PLL/n4_2" BEL "PLL/n4_3" BEL "PLL/n4_4" BEL "PLL/n4_5" BEL "PLL/n4_6"
        BEL "PLL/n4_7" BEL "PLL/n4_8" BEL "PLL/n4_9" BEL "PLL/n4_10" BEL
        "PLL/n4_11" BEL "PLL/n4_12" BEL "PLL/n4_13" BEL "PLL/n4_14" BEL
        "PLL/n4_15" BEL "PLL/n4_16" BEL "PLL/n4_17" BEL "PLL/n4_18" BEL
        "PLL/n4_19" BEL "PLL/n4_20" BEL "PLL/n4_21" BEL "PLL/n4_22" BEL
        "PLL/n4_23" BEL "PLL/n5_0" BEL "PLL/n5_1" BEL "PLL/n5_2" BEL
        "PLL/n5_3" BEL "PLL/n5_4" BEL "PLL/n5_5" BEL "PLL/n5_6" BEL "PLL/n5_7"
        BEL "PLL/n5_8" BEL "PLL/n5_9" BEL "PLL/n5_10" BEL "PLL/n5_11" BEL
        "PLL/n5_12" BEL "PLL/n5_13" BEL "PLL/n5_14" BEL "PLL/n5_15" BEL
        "PLL/n5_16" BEL "PLL/n5_17" BEL "PLL/n5_18" BEL "PLL/n5_19" BEL
        "PLL/n5_20" BEL "PLL/n5_21" BEL "PLL/n5_22" BEL "PLL/n5_23" BEL
        "PLL/s6_0" BEL "PLL/s6_1" BEL "PLL/s6_2" BEL "PLL/s6_3" BEL "PLL/s6_4"
        BEL "PLL/s6_5" BEL "PLL/s6_6" BEL "PLL/s6_7" BEL "PLL/s6_8" BEL
        "PLL/s6_9" BEL "PLL/s6_10" BEL "PLL/s6_11" BEL "PLL/s6_12" BEL
        "PLL/s6_13" BEL "PLL/s6_14" BEL "PLL/s6_15" BEL "PLL/s6_16" BEL
        "PLL/s6_17" BEL "PLL/s6_18" BEL "PLL/s6_19" BEL "PLL/s6_20" BEL
        "PLL/s6_21" BEL "PLL/s6_22" BEL "PLL/s6_23" BEL "PLL/n6_0" BEL
        "PLL/n6_1" BEL "PLL/n6_2" BEL "PLL/n6_3" BEL "PLL/n6_4" BEL "PLL/n6_5"
        BEL "PLL/n6_6" BEL "PLL/n6_7" BEL "PLL/n6_8" BEL "PLL/n6_9" BEL
        "PLL/n6_10" BEL "PLL/n6_11" BEL "PLL/n6_12" BEL "PLL/n6_13" BEL
        "PLL/n6_14" BEL "PLL/n6_15" BEL "PLL/n6_16" BEL "PLL/n6_17" BEL
        "PLL/n6_18" BEL "PLL/n6_19" BEL "PLL/n6_20" BEL "PLL/n6_21" BEL
        "PLL/n6_22" BEL "PLL/n6_23" BEL "PLL/dds_freq_OVR" BEL
        "PLL/PT_MSB_edg_det_0" BEL "PLL/dds_freq_UR" BEL
        "PLL/PT_MSB_edg_det_1" BEL "PLL/HC_tab_addr_cnt_0" BEL
        "PLL/HC_tab_addr_cnt_1" BEL "PLL/HC_tab_addr_cnt_2" BEL
        "PLL/HC_tab_addr_cnt_3" BEL "PLL/HC_tab_addr_cnt_4" BEL
        "PLL/ST_tab_addr_cnt_0" BEL "PLL/ST_tab_addr_cnt_1" BEL
        "PLL/ST_tab_addr_cnt_2" BEL "PLL/INJ_tab_addr_cnt_0" BEL
        "PLL/INJ_tab_addr_cnt_1" BEL "PLL/INJ_tab_addr_cnt_2" BEL
        "PLL/state_FFd1" BEL "PLL/state_FFd2" BEL "PLL/accumulate_0_0" BEL
        "PLL/accumulate_0_1" BEL "PLL/accumulate_0_2" BEL "PLL/accumulate_0_3"
        BEL "PLL/accumulate_0_4" BEL "PLL/accumulate_0_5" BEL
        "PLL/accumulate_0_6" BEL "PLL/accumulate_0_7" BEL "PLL/accumulate_0_8"
        BEL "PLL/accumulate_0_9" BEL "PLL/accumulate_0_10" BEL
        "PLL/accumulate_0_11" BEL "PLL/accumulate_0_12" BEL
        "PLL/accumulate_0_13" BEL "PLL/accumulate_0_14" BEL
        "PLL/accumulate_0_15" BEL "PLL/C_tab_addr_cnt_0" BEL
        "PLL/C_tab_addr_cnt_1" BEL "PLL/C_tab_addr_cnt_2" BEL
        "PLL/C_tab_addr_cnt_3" BEL "PLL/C_tab_addr_cnt_4" BEL
        "PLL/C_tab_addr_cnt_5" BEL "PLL/C_tab_addr_cnt_6" BEL
        "PLL/C_tab_addr_cnt_7" BEL "PLL/C_tab_addr_cnt_8" BEL
        "PLL/C_tab_addr_cnt_9" BEL "PLL/C_tab_addr_cnt_10" BEL
        "PLL/C_tab_addr_cnt_11" BEL "PLL/C_tab_addr_cnt_12" BEL
        "PLL/accumulate_1_0" BEL "PLL/accumulate_1_1" BEL "PLL/accumulate_1_2"
        BEL "PLL/accumulate_1_3" BEL "PLL/accumulate_1_4" BEL
        "PLL/accumulate_1_5" BEL "PLL/accumulate_1_6" BEL "PLL/accumulate_1_7"
        BEL "PLL/accumulate_1_8" BEL "PLL/accumulate_1_9" BEL
        "PLL/accumulate_1_10" BEL "PLL/accumulate_1_11" BEL
        "PLL/accumulate_1_12" BEL "PLL/accumulate_1_13" BEL
        "PLL/accumulate_1_14" BEL "PLL/accumulate_1_15" BEL
        "PLL/accumulate_2_0" BEL "PLL/accumulate_2_1" BEL "PLL/accumulate_2_2"
        BEL "PLL/accumulate_2_3" BEL "PLL/accumulate_2_4" BEL
        "PLL/accumulate_2_5" BEL "PLL/accumulate_2_6" BEL "PLL/accumulate_2_7"
        BEL "PLL/accumulate_2_8" BEL "PLL/accumulate_2_9" BEL
        "PLL/accumulate_2_10" BEL "PLL/accumulate_2_11" BEL
        "PLL/accumulate_2_12" BEL "PLL/accumulate_2_13" BEL
        "PLL/accumulate_2_14" BEL "PLL/accumulate_2_15" BEL
        "PLL/SDRAM_Addr_cnt_0" BEL "PLL/SDRAM_Addr_cnt_1" BEL
        "PLL/SDRAM_Addr_cnt_2" BEL "PLL/SDRAM_Addr_cnt_3" BEL
        "PLL/SDRAM_Addr_cnt_4" BEL "PLL/SDRAM_Addr_cnt_5" BEL
        "PLL/SDRAM_Addr_cnt_6" BEL "PLL/SDRAM_Addr_cnt_7" BEL
        "PLL/SDRAM_Addr_cnt_8" BEL "PLL/SDRAM_Addr_cnt_9" BEL
        "PLL/SDRAM_Addr_cnt_10" BEL "PLL/SDRAM_Addr_cnt_11" BEL
        "PLL/SDRAM_Addr_cnt_12" BEL "PLL/SDRAM_Addr_cnt_13" BEL
        "PLL/SDRAM_Addr_cnt_14" BEL "PLL/SDRAM_Addr_cnt_15" BEL
        "PLL/SDRAM_Addr_cnt_16" BEL "PLL/SDRAM_Addr_cnt_17" BEL
        "PLL/SDRAM_Addr_cnt_18" BEL "PLL/SDRAM_Addr_cnt_19" BEL
        "PLL/SDRAM_Addr_cnt_20" BEL "PLL/SDRAM_Addr_cnt_21" BEL
        "PLL/SDRAM_Addr_cnt_22" BEL "PLL/SDRAM_Addr_cnt_23" BEL
        "PLL/SDRAM_Addr_cnt_24" BEL "PLL/SDRAM_Addr_cnt_25" BEL
        "PLL/C_timer_count_0" BEL "PLL/C_timer_count_1" BEL
        "PLL/C_timer_count_2" BEL "PLL/C_timer_count_3" BEL
        "PLL/C_timer_count_4" BEL "PLL/C_timer_count_5" BEL
        "PLL/C_timer_count_6" BEL "PLL/C_timer_count_7" BEL
        "PLL/C_timer_count_8" BEL "PLL/C_timer_count_9" BEL
        "PLL/C_timer_count_10" BEL "PLL/C_timer_count_11" BEL
        "PLL/C_timer_count_12" BEL "PLL/C_timer_count_13" BEL
        "PLL/C_timer_count_14" BEL "PLL/C_timer_count_15" BEL
        "PLL/C_timer_count_16" BEL "PLL/b0_0" BEL "PLL/b0_1" BEL "PLL/b0_2"
        BEL "PLL/b0_3" BEL "PLL/b0_4" BEL "PLL/b0_5" BEL "PLL/b0_6" BEL
        "PLL/b0_7" BEL "PLL/b0_8" BEL "PLL/b0_9" BEL "PLL/b0_10" BEL
        "PLL/b0_11" BEL "PLL/b0_12" BEL "PLL/b0_13" BEL "PLL/b0_14" BEL
        "PLL/b0_15" BEL "PLL/b0_16" BEL "PLL/b0_17" BEL "PLL/b0_18" BEL
        "PLL/b0_19" BEL "PLL/b0_20" BEL "PLL/b0_21" BEL "PLL/b0_22" BEL
        "PLL/b0_23" BEL "PLL/b1_0" BEL "PLL/b1_1" BEL "PLL/b1_2" BEL
        "PLL/b1_3" BEL "PLL/b1_4" BEL "PLL/b1_5" BEL "PLL/b1_6" BEL "PLL/b1_7"
        BEL "PLL/b1_8" BEL "PLL/b1_9" BEL "PLL/b1_10" BEL "PLL/b1_11" BEL
        "PLL/b1_12" BEL "PLL/b1_13" BEL "PLL/b1_14" BEL "PLL/b1_15" BEL
        "PLL/b1_16" BEL "PLL/b1_17" BEL "PLL/b1_18" BEL "PLL/b1_19" BEL
        "PLL/b1_20" BEL "PLL/b1_21" BEL "PLL/b1_22" BEL "PLL/b1_23" BEL
        "PLL/e1_0" BEL "PLL/e1_1" BEL "PLL/e1_2" BEL "PLL/e1_3" BEL "PLL/e1_4"
        BEL "PLL/e1_5" BEL "PLL/e1_6" BEL "PLL/e1_7" BEL "PLL/e1_8" BEL
        "PLL/e1_9" BEL "PLL/e1_10" BEL "PLL/e1_11" BEL "PLL/e1_12" BEL
        "PLL/e1_13" BEL "PLL/e1_14" BEL "PLL/e1_15" BEL "PLL/e1_16" BEL
        "PLL/e1_17" BEL "PLL/e1_18" BEL "PLL/e1_19" BEL "PLL/e1_20" BEL
        "PLL/e1_21" BEL "PLL/e1_22" BEL "PLL/e1_23" BEL "PLL/b2_0" BEL
        "PLL/b2_1" BEL "PLL/b2_2" BEL "PLL/b2_3" BEL "PLL/b2_4" BEL "PLL/b2_5"
        BEL "PLL/b2_6" BEL "PLL/b2_7" BEL "PLL/b2_8" BEL "PLL/b2_9" BEL
        "PLL/b2_10" BEL "PLL/b2_11" BEL "PLL/b2_12" BEL "PLL/b2_13" BEL
        "PLL/b2_14" BEL "PLL/b2_15" BEL "PLL/b2_16" BEL "PLL/b2_17" BEL
        "PLL/b2_18" BEL "PLL/b2_19" BEL "PLL/b2_20" BEL "PLL/b2_21" BEL
        "PLL/b2_22" BEL "PLL/b2_23" BEL "PLL/e0_0" BEL "PLL/e0_1" BEL
        "PLL/e0_2" BEL "PLL/e0_3" BEL "PLL/e0_4" BEL "PLL/e0_5" BEL "PLL/e0_6"
        BEL "PLL/e0_7" BEL "PLL/e0_8" BEL "PLL/e0_9" BEL "PLL/e0_10" BEL
        "PLL/e0_11" BEL "PLL/e0_12" BEL "PLL/e0_13" BEL "PLL/e0_14" BEL
        "PLL/e0_15" BEL "PLL/e0_16" BEL "PLL/e0_17" BEL "PLL/e0_18" BEL
        "PLL/e0_19" BEL "PLL/e0_20" BEL "PLL/e0_21" BEL "PLL/e0_22" BEL
        "PLL/e0_23" BEL "PLL/e2_0" BEL "PLL/e2_1" BEL "PLL/e2_2" BEL
        "PLL/e2_3" BEL "PLL/e2_4" BEL "PLL/e2_5" BEL "PLL/e2_6" BEL "PLL/e2_7"
        BEL "PLL/e2_8" BEL "PLL/e2_9" BEL "PLL/e2_10" BEL "PLL/e2_11" BEL
        "PLL/e2_12" BEL "PLL/e2_13" BEL "PLL/e2_14" BEL "PLL/e2_15" BEL
        "PLL/e2_16" BEL "PLL/e2_17" BEL "PLL/e2_18" BEL "PLL/e2_19" BEL
        "PLL/e2_20" BEL "PLL/e2_21" BEL "PLL/e2_22" BEL "PLL/e2_23" BEL
        "PLL/dds_ph_0" BEL "PLL/dds_ph_1" BEL "PLL/dds_ph_2" BEL
        "PLL/dds_ph_3" BEL "PLL/dds_ph_4" BEL "PLL/dds_ph_5" BEL
        "PLL/dds_ph_6" BEL "PLL/dds_ph_7" BEL "PLL/dds_ph_8" BEL
        "PLL/dds_ph_9" BEL "PLL/dds_ph_10" BEL "PLL/dds_ph_11" BEL
        "PLL/dds_ph_12" BEL "PLL/dds_ph_13" BEL "PLL/dds_ph_14" BEL
        "PLL/dds_ph_15" BEL "PLL/dds_ph_16" BEL "PLL/dds_ph_17" BEL
        "PLL/dds_ph_18" BEL "PLL/dds_ph_19" BEL "PLL/dds_ph_20" BEL
        "PLL/dds_ph_21" BEL "PLL/dds_ph_22" BEL "PLL/dds_ph_23" BEL
        "PLL/dds_ph_24" BEL "PLL/dds_ph_25" BEL "PLL/dds_ph_26" BEL
        "PLL/dds_ph_27" BEL "PLL/dds_ph_28" BEL "PLL/dds_ph_29" BEL
        "PLL/dds_ph_30" BEL "PLL/dds_ph_31" BEL "PLL/dds_freq_31" BEL
        "PLL/dds_freq_30" BEL "PLL/dds_freq_29" BEL "PLL/dds_freq_28" BEL
        "PLL/dds_freq_27" BEL "PLL/dds_freq_26" BEL "PLL/dds_freq_25" BEL
        "PLL/dds_freq_24" BEL "PLL/dds_freq_23" BEL "PLL/dds_freq_22" BEL
        "PLL/dds_freq_21" BEL "PLL/dds_freq_20" BEL "PLL/dds_freq_19" BEL
        "PLL/dds_freq_18" BEL "PLL/dds_freq_17" BEL "PLL/dds_freq_16" BEL
        "PLL/dds_freq_15" BEL "PLL/dds_freq_14" BEL "PLL/dds_freq_13" BEL
        "PLL/dds_freq_12" BEL "PLL/dds_freq_11" BEL "PLL/dds_freq_10" BEL
        "PLL/dds_freq_9" BEL "PLL/dds_freq_8" BEL "PLL/dds_freq_7" BEL
        "PLL/dds_freq_6" BEL "PLL/dds_freq_5" BEL "PLL/dds_freq_4" BEL
        "PLL/dds_freq_3" BEL "PLL/dds_freq_2" BEL "PLL/dds_freq_1" BEL
        "PLL/dds_freq_0" BEL "PLL/chipscope/trig_del1_0" BEL
        "PLL/chipscope/trig_del1_1" BEL "PLL/chipscope/trig_del1_2" BEL
        "PLL/chipscope/stop_trig_0" BEL "PLL/chipscope/clk2" BEL
        "PLL/chipscope/trig_ch0_delayed" BEL "PLL/chipscope/trig_del2_0" BEL
        "PLL/chipscope/trig_del2_1" BEL "PLL/chipscope/trig_del2_2" BEL
        "PLL/chipscope/stop_trig_1" BEL "PLL/chipscope/trig_timer_en" BEL
        "PLL/chipscope/stop_trig_2" BEL "PLL/chipscope/stop_trig_3" BEL
        "PLL/chipscope/stop_trig_4" BEL "PLL/chipscope/trig_del3_0" BEL
        "PLL/chipscope/trig_del3_3" BEL "PLL/chipscope/trig_del3_2" BEL
        "PLL/chipscope/timer_0" BEL "PLL/chipscope/timer_1" BEL
        "PLL/chipscope/timer_2" BEL "PLL/chipscope/timer_3" BEL
        "PLL/chipscope/timer_4" BEL "PLL/chipscope/timer_5" BEL
        "PLL/chipscope/timer_6" BEL "PLL/chipscope/timer_7" BEL
        "PLL/chipscope/timer_8" BEL "PLL/chipscope/timer_9" BEL
        "PLL/chipscope/timer_10" BEL "PLL/chipscope/timer_11" BEL
        "PLL/chipscope/timer_12" BEL "PLL/chipscope/timer_13" BEL
        "PLL/chipscope/timer_14" BEL "PLL/chipscope/timer_15" BEL
        "PLL/chipscope/timer_16" BEL "PLL/chipscope/timer_17" BEL
        "PLL/chipscope/timer_18" BEL "PLL/chipscope/timer_19" BEL
        "PLL/chipscope/timer_20" BEL "PLL/chipscope/timer_23" BEL
        "PLL/chipscope/timer_21" BEL "PLL/chipscope/timer_22" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_tq0/g_tw/0/u_tq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_tq0/g_tw/1/u_tq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_tq0/g_tw/2/u_tq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_tq0/g_tw/3/u_tq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/0/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/1/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/2/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/3/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/4/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/5/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/6/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/7/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/8/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/9/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/10/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/11/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/12/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/13/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/14/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/15/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/16/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/17/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/18/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/19/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/20/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/21/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/22/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/23/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/24/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/25/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/26/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/27/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/28/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/29/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/30/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/31/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/32/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/33/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/34/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/35/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/36/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/37/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/38/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/39/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/40/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/41/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/42/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/43/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/44/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/45/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/46/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/47/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/48/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/49/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/50/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/51/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/52/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/53/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/54/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/55/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/56/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/57/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/58/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/59/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/60/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/61/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/62/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/63/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/64/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/65/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/66/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/67/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/68/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/69/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/70/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/71/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/72/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/73/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/74/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/75/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/76/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/77/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/78/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/79/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/80/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/81/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/82/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/83/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/84/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/85/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/86/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/87/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/88/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/89/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/90/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/91/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/92/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/93/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/94/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_dq/g_dw/95/u_dq" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/0/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/0/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/1/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/1/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/2/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/2/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/3/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/3/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/4/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/4/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/5/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/5/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/6/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/6/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/7/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/7/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/8/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/8/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/9/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/9/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/10/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/10/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/11/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/11/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/12/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/12/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/13/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/13/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/14/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/14/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/15/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/15/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/16/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/16/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/17/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/17/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/18/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/18/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/19/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/19/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/20/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/20/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/21/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/21/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/22/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/22/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/23/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/23/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/24/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/24/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/25/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/25/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/26/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/26/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/27/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/27/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/28/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/28/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/29/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/29/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/30/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/30/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/31/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/31/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/32/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/32/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/33/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/33/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/34/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/34/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/35/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/35/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/36/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/36/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/37/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/37/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/38/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/38/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/39/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/39/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/40/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/40/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/41/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/41/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/42/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/42/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/43/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/43/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/44/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/44/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/45/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/45/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/46/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/46/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/47/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/47/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/48/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/48/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/49/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/49/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/50/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/50/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/51/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/51/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/52/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/52/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/53/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/53/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/54/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/54/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/55/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/55/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/56/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/56/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/57/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/57/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/58/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/58/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/59/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/59/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/60/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/60/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/61/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/61/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/62/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/62/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/63/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/63/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/64/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/64/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/65/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/65/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/66/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/66/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/67/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/67/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/68/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/68/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/69/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/69/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/70/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/70/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/71/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/71/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/72/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/72/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/73/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/73/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/74/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/74/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/75/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/75/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/76/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/76/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/77/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/77/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/78/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/78/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/79/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/79/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/80/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/80/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/81/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/81/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/82/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/82/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/83/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/83/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/84/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/84/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/85/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/85/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/86/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/86/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/87/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/87/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/88/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/88/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/89/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/89/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/90/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/90/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/91/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/91/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/92/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/92/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/93/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/93/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/94/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/94/i_srlt_ne_0/ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/95/i_srlt_ne_0/dly9/SRL16E"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/95/i_srlt_ne_0/ff"
        BEL "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_rst/u_por" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_rst/u_halt_xfer/u_dout0"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_rst/u_halt_xfer/u_dout1"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_rst/u_halt_xfer/u_dout"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_rst/u_halt_xfer/u_rfdre"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_rst/u_halt_xfer/u_gen_delay/1/u_fd"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_rst/u_halt_xfer/u_gen_delay/2/u_fd"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_rst/u_arm_xfer/u_dout0"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_rst/u_arm_xfer/u_dout1"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_rst/u_arm_xfer/u_dout"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_rst/u_arm_xfer/u_rfdre"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_rst/u_arm_xfer/u_gen_delay/1/u_fd"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_rst/u_arm_xfer/u_gen_delay/2/u_fd"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_rst/u_arm_xfer/u_gen_delay/3/u_fd"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_rst/u_arm_xfer/u_gen_delay/4/u_fd"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_rst/g_rst/0/u_rst"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_rst/g_rst/1/u_rst"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_rst/g_rst/2/u_rst"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_rst/g_rst/3/u_rst"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_rst/g_rst/4/u_rst"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_rst/g_rst/5/u_rst"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_rst/g_rst/6/u_rst"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_rst/g_rst/7/u_rst"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_trig/u_tm/g_nmu/0/u_m/u_mu/i_mut_gand/u_match/pd_rpm/i_twmod8_ne0/i_yes_rpm/i_oreg/u_oreg"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_trig/u_tm/g_nmu/0/u_m/u_mu/i_mut_gand/u_match/i_yes_ireg/f_tw/0/u_ireg"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_trig/u_tm/g_nmu/0/u_m/u_mu/i_mut_gand/u_match/i_yes_ireg/f_tw/1/u_ireg"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_trig/u_tm/g_nmu/0/u_m/u_mu/i_mut_gand/u_match/i_yes_ireg/f_tw/2/u_ireg"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_trig/u_tm/g_nmu/0/u_m/u_mu/i_mut_gand/u_match/i_yes_ireg/f_tw/3/u_ireg"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_trig/u_tm/g_nmu/0/u_m/u_mu/i_oreg/i_yes_oreg/u_oreg"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_trig/u_tm/g_nmu/0/u_m/i_mc_no/u_no_mc_reg"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_trig/u_tc/i_tseq_neq2/u_tc_equation/i_srlt_ne_1/i_nmu_1_to_4/u_tcl/i_outreg/u_dout"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_trig/u_tc/i_tseq_neq2/u_tc_equation/i_srlt_ne_1/i_nmu_1_to_4/u_trigq"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_trig/u_tc/i_storage_qual/u_storage_qual/i_srlt_ne_1/i_nmu_1_to_4/u_tcl/i_outreg/u_dout"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_trig/u_tc/i_storage_qual/u_storage_qual/i_srlt_ne_1/i_nmu_1_to_4/u_trigq"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_trig/u_tc/i_storage_qual/u_cap_dly"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_trig/f_no_tcmc/u_fdr"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_stat/u_dsl1/u_dout0"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_stat/u_dsl1/u_dout1"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_stat/u_dsl1/u_dout"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_stat/u_dsl1/u_rfdre"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_stat/u_dsl1/u_gen_delay/1/u_fd"
        BEL "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_stat/u_dsl2" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_stat/u_dsl3" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_stat/u_cr" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_stat/g_ns/12/u_nsq"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_stat/g_ns/11/u_nsq"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_stat/g_ns/10/u_nsq"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_stat/g_ns/9/u_nsq"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_stat/g_ns/8/u_nsq"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_stat/g_ns/7/u_nsq"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_stat/g_ns/6/u_nsq"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_stat/g_ns/5/u_nsq"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_stat/g_ns/4/u_nsq"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_stat/g_ns/3/u_nsq"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_stat/g_ns/2/u_nsq"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_stat/g_ns/1/u_nsq"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_stat/g_ns/0/u_nsq"
        BEL "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_stat/u_state1"
        BEL "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_stat/u_state0"
        BEL "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_stat/u_arm" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_stat/u_trigger" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_stat/u_full" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_stat/u_tsof" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_stat/u_ecr" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_stat/u_ece" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_stat/u_rising" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_intcap/f_cap_addr/0/u_icap_addr"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_intcap/f_cap_addr/0/u_cap_addr"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_intcap/f_cap_addr/1/u_icap_addr"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_intcap/f_cap_addr/1/u_cap_addr"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_intcap/f_cap_addr/2/u_icap_addr"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_intcap/f_cap_addr/2/u_cap_addr"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_intcap/f_cap_addr/3/u_icap_addr"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_intcap/f_cap_addr/3/u_cap_addr"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_intcap/f_cap_addr/4/u_icap_addr"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_intcap/f_cap_addr/4/u_cap_addr"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_intcap/f_cap_addr/5/u_icap_addr"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_intcap/f_cap_addr/5/u_cap_addr"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_intcap/f_cap_addr/6/u_icap_addr"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_intcap/f_cap_addr/6/u_cap_addr"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_intcap/f_cap_addr/7/u_icap_addr"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_intcap/f_cap_addr/7/u_cap_addr"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_intcap/f_cap_addr/8/u_icap_addr"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_intcap/f_cap_addr/8/u_cap_addr"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_intcap/f_cap_addr/9/u_icap_addr"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_intcap/f_cap_addr/9/u_cap_addr"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_intcap/f_cap_addr/10/u_icap_addr"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_intcap/f_cap_addr/10/u_cap_addr"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_intcap/f_cap_addr/11/u_icap_addr"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_intcap/f_cap_addr/11/u_cap_addr"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_intcap/f_cap_addr/12/u_icap_addr"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_intcap/f_cap_addr/12/u_cap_addr"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_no_tseq/i_srlt_ne_1/u_scnt/g/12/u_fdre"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_no_tseq/i_srlt_ne_1/u_scnt/g/11/u_fdre"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_no_tseq/i_srlt_ne_1/u_scnt/g/10/u_fdre"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_no_tseq/i_srlt_ne_1/u_scnt/g/9/u_fdre"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_no_tseq/i_srlt_ne_1/u_scnt/g/8/u_fdre"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_no_tseq/i_srlt_ne_1/u_scnt/g/7/u_fdre"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_no_tseq/i_srlt_ne_1/u_scnt/g/6/u_fdre"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_no_tseq/i_srlt_ne_1/u_scnt/g/5/u_fdre"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_no_tseq/i_srlt_ne_1/u_scnt/g/4/u_fdre"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_no_tseq/i_srlt_ne_1/u_scnt/g/3/u_fdre"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_no_tseq/i_srlt_ne_1/u_scnt/g/2/u_fdre"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_no_tseq/i_srlt_ne_1/u_scnt/g/1/u_fdre"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_no_tseq/i_srlt_ne_1/u_scnt/g/0/u_fdre"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_srlt_ne_1/u_wcnt/g/12/u_fdre"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_srlt_ne_1/u_wcnt/g/11/u_fdre"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_srlt_ne_1/u_wcnt/g/10/u_fdre"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_srlt_ne_1/u_wcnt/g/9/u_fdre"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_srlt_ne_1/u_wcnt/g/8/u_fdre"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_srlt_ne_1/u_wcnt/g/7/u_fdre"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_srlt_ne_1/u_wcnt/g/6/u_fdre"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_srlt_ne_1/u_wcnt/g/5/u_fdre"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_srlt_ne_1/u_wcnt/g/4/u_fdre"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_srlt_ne_1/u_wcnt/g/3/u_fdre"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_srlt_ne_1/u_wcnt/g/2/u_fdre"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_srlt_ne_1/u_wcnt/g/1/u_fdre"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_srlt_ne_1/u_wcnt/g/0/u_fdre"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_wcnt_hcmp_q"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_wcnt_lcmp_q"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_scnt_cmp_q"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_ns1/pd_rpm/i_srl_t2/i_yes_rpm/i_yes_oreg/out_reg"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_ns0/pd_rpm/i_srl_t2/i_yes_rpm/i_yes_oreg/out_reg"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_cdone/pd_rpm/i_srl_t2/i_yes_rpm/i_yes_oreg/out_reg"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_intcap_f/u_capwe0"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_intcap_f/u_capwe1"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_trig0"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_trig1"
        PIN
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/48/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1025.B_pins<53>"
        PIN
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/47/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1029.B_pins<53>"
        PIN
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/46/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1033.B_pins<53>"
        PIN
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/45/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1037.B_pins<53>"
        PIN
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/44/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1041.B_pins<53>"
        PIN
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/43/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1045.B_pins<53>"
        PIN
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/42/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1049.B_pins<53>"
        PIN
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/41/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1053.B_pins<53>"
        PIN
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/40/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1057.B_pins<53>"
        PIN
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/39/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1061.B_pins<53>"
        PIN
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/38/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1065.B_pins<53>"
        PIN
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/37/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1069.B_pins<53>"
        PIN
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/36/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1073.B_pins<53>"
        PIN
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/35/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1077.B_pins<53>"
        PIN
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/34/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1081.B_pins<53>"
        PIN
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/33/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1085.B_pins<53>"
        PIN
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/32/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1089.B_pins<53>"
        PIN
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/31/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1093.B_pins<53>"
        PIN
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/30/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1097.B_pins<53>"
        PIN
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/29/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1101.B_pins<53>"
        PIN
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/28/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1105.B_pins<53>"
        PIN
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/27/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1109.B_pins<53>"
        PIN
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/26/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1113.B_pins<53>"
        PIN
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/25/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1117.B_pins<53>"
        PIN
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/24/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1121.B_pins<53>"
        PIN
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/23/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1125.B_pins<53>"
        PIN
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/22/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1129.B_pins<53>"
        PIN
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/21/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1133.B_pins<53>"
        PIN
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/20/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1137.B_pins<53>"
        PIN
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/19/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1141.B_pins<53>"
        PIN
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/18/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1145.B_pins<53>"
        PIN
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/17/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1149.B_pins<53>"
        PIN
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/16/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1153.B_pins<53>"
        PIN
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/15/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1157.B_pins<53>"
        PIN
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/14/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1161.B_pins<53>"
        PIN
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/13/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1165.B_pins<53>"
        PIN
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/12/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1169.B_pins<53>"
        PIN
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/11/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1173.B_pins<53>"
        PIN
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/10/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1177.B_pins<53>"
        PIN
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/9/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1181.B_pins<53>"
        PIN
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/8/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1185.B_pins<53>"
        PIN
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/7/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1189.B_pins<53>"
        PIN
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/6/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1193.B_pins<53>"
        PIN
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/5/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1197.B_pins<53>"
        PIN
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/4/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1201.B_pins<53>"
        PIN
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/3/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1205.B_pins<53>"
        PIN
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/2/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1209.B_pins<53>"
        PIN
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/1/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1213.B_pins<53>"
        PIN
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/0/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1217.B_pins<53>"
        BEL "PLL/chipscope/trig_timer_2" BEL "PLL/chipscope/trig_timer_0" BEL
        "PLL/chipscope/trig_timer_1" BEL "PLL/chipscope/trig_timer_5" BEL
        "PLL/chipscope/trig_timer_3" BEL "PLL/chipscope/trig_timer_4" BEL
        "PLL/chipscope/trig_timer_8" BEL "PLL/chipscope/trig_timer_6" BEL
        "PLL/chipscope/trig_timer_7" BEL "PLL/chipscope/trig_timer_11" BEL
        "PLL/chipscope/trig_timer_9" BEL "PLL/chipscope/trig_timer_10" BEL
        "PLL/chipscope/trig_timer_14" BEL "PLL/chipscope/trig_timer_12" BEL
        "PLL/chipscope/trig_timer_13" BEL "PLL/chipscope/trig_timer_17" BEL
        "PLL/chipscope/trig_timer_15" BEL "PLL/chipscope/trig_timer_16" BEL
        "PLL/chipscope/trig_timer_20" BEL "PLL/chipscope/trig_timer_18" BEL
        "PLL/chipscope/trig_timer_19" BEL "PLL/chipscope/trig_timer_23" BEL
        "PLL/chipscope/trig_timer_21" BEL "PLL/chipscope/trig_timer_22" BEL
        "ADC_A_buf_13" BEL "ADC_B_buf_13" BEL "ADC_C_buf_13" BEL "PLL/n6_23_1"
        BEL "PLL/n6_23_2" BEL "DIO<2>";
PIN
        PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/48/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1025.A_pins<53>
        = BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/48/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1025.A"
        PINNAME CLKA;
PIN
        PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/47/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1029.A_pins<53>
        = BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/47/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1029.A"
        PINNAME CLKA;
PIN
        PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/46/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1033.A_pins<53>
        = BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/46/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1033.A"
        PINNAME CLKA;
PIN
        PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/45/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1037.A_pins<53>
        = BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/45/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1037.A"
        PINNAME CLKA;
PIN
        PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/44/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1041.A_pins<53>
        = BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/44/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1041.A"
        PINNAME CLKA;
PIN
        PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/43/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1045.A_pins<53>
        = BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/43/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1045.A"
        PINNAME CLKA;
PIN
        PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/42/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1049.A_pins<53>
        = BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/42/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1049.A"
        PINNAME CLKA;
PIN
        PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/41/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1053.A_pins<53>
        = BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/41/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1053.A"
        PINNAME CLKA;
PIN
        PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/40/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1057.A_pins<53>
        = BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/40/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1057.A"
        PINNAME CLKA;
PIN
        PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/39/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1061.A_pins<53>
        = BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/39/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1061.A"
        PINNAME CLKA;
PIN
        PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/38/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1065.A_pins<53>
        = BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/38/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1065.A"
        PINNAME CLKA;
PIN
        PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/37/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1069.A_pins<53>
        = BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/37/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1069.A"
        PINNAME CLKA;
PIN
        PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/36/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1073.A_pins<53>
        = BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/36/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1073.A"
        PINNAME CLKA;
PIN
        PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/35/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1077.A_pins<53>
        = BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/35/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1077.A"
        PINNAME CLKA;
PIN
        PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/34/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1081.A_pins<53>
        = BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/34/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1081.A"
        PINNAME CLKA;
PIN
        PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/33/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1085.A_pins<53>
        = BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/33/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1085.A"
        PINNAME CLKA;
PIN
        PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/32/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1089.A_pins<53>
        = BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/32/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1089.A"
        PINNAME CLKA;
PIN
        PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/31/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1093.A_pins<53>
        = BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/31/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1093.A"
        PINNAME CLKA;
PIN
        PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/30/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1097.A_pins<53>
        = BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/30/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1097.A"
        PINNAME CLKA;
PIN
        PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/29/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1101.A_pins<53>
        = BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/29/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1101.A"
        PINNAME CLKA;
PIN
        PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/28/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1105.A_pins<53>
        = BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/28/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1105.A"
        PINNAME CLKA;
PIN
        PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/27/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1109.A_pins<53>
        = BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/27/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1109.A"
        PINNAME CLKA;
PIN
        PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/26/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1113.A_pins<53>
        = BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/26/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1113.A"
        PINNAME CLKA;
PIN
        PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/25/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1117.A_pins<53>
        = BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/25/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1117.A"
        PINNAME CLKA;
PIN
        PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/24/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1121.A_pins<53>
        = BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/24/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1121.A"
        PINNAME CLKA;
PIN
        PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/23/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1125.A_pins<53>
        = BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/23/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1125.A"
        PINNAME CLKA;
PIN
        PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/22/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1129.A_pins<53>
        = BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/22/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1129.A"
        PINNAME CLKA;
PIN
        PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/21/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1133.A_pins<53>
        = BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/21/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1133.A"
        PINNAME CLKA;
PIN
        PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/20/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1137.A_pins<53>
        = BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/20/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1137.A"
        PINNAME CLKA;
PIN
        PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/19/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1141.A_pins<53>
        = BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/19/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1141.A"
        PINNAME CLKA;
PIN
        PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/18/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1145.A_pins<53>
        = BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/18/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1145.A"
        PINNAME CLKA;
PIN
        PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/17/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1149.A_pins<53>
        = BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/17/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1149.A"
        PINNAME CLKA;
PIN
        PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/16/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1153.A_pins<53>
        = BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/16/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1153.A"
        PINNAME CLKA;
PIN
        PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/15/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1157.A_pins<53>
        = BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/15/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1157.A"
        PINNAME CLKA;
PIN
        PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/14/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1161.A_pins<53>
        = BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/14/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1161.A"
        PINNAME CLKA;
PIN
        PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/13/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1165.A_pins<53>
        = BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/13/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1165.A"
        PINNAME CLKA;
PIN
        PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/12/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1169.A_pins<53>
        = BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/12/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1169.A"
        PINNAME CLKA;
PIN
        PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/11/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1173.A_pins<53>
        = BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/11/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1173.A"
        PINNAME CLKA;
PIN
        PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/10/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1177.A_pins<53>
        = BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/10/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1177.A"
        PINNAME CLKA;
PIN
        PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/9/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1181.A_pins<53>
        = BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/9/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1181.A"
        PINNAME CLKA;
PIN
        PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/8/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1185.A_pins<53>
        = BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/8/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1185.A"
        PINNAME CLKA;
PIN
        PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/7/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1189.A_pins<53>
        = BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/7/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1189.A"
        PINNAME CLKA;
PIN
        PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/6/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1193.A_pins<53>
        = BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/6/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1193.A"
        PINNAME CLKA;
PIN
        PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/5/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1197.A_pins<53>
        = BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/5/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1197.A"
        PINNAME CLKA;
PIN
        PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/4/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1201.A_pins<53>
        = BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/4/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1201.A"
        PINNAME CLKA;
PIN
        PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/3/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1205.A_pins<53>
        = BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/3/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1205.A"
        PINNAME CLKA;
PIN
        PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/2/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1209.A_pins<53>
        = BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/2/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1209.A"
        PINNAME CLKA;
PIN
        PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/1/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1213.A_pins<53>
        = BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/1/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1213.A"
        PINNAME CLKA;
PIN
        PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/0/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1217.A_pins<53>
        = BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/0/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1217.A"
        PINNAME CLKA;
PIN
        PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/24/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim844.A_pins<53>
        = BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/24/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim844.A"
        PINNAME CLKA;
PIN
        PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/23/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim848.A_pins<53>
        = BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/23/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim848.A"
        PINNAME CLKA;
PIN
        PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/22/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim852.A_pins<53>
        = BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/22/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim852.A"
        PINNAME CLKA;
PIN
        PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/21/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim856.A_pins<53>
        = BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/21/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim856.A"
        PINNAME CLKA;
PIN
        PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/20/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim860.A_pins<53>
        = BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/20/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim860.A"
        PINNAME CLKA;
PIN
        PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/19/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim864.A_pins<53>
        = BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/19/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim864.A"
        PINNAME CLKA;
PIN
        PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/18/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim868.A_pins<53>
        = BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/18/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim868.A"
        PINNAME CLKA;
PIN
        PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/17/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim872.A_pins<53>
        = BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/17/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim872.A"
        PINNAME CLKA;
PIN
        PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/16/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim876.A_pins<53>
        = BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/16/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim876.A"
        PINNAME CLKA;
PIN
        PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/15/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim880.A_pins<53>
        = BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/15/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim880.A"
        PINNAME CLKA;
PIN
        PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/14/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim884.A_pins<53>
        = BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/14/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim884.A"
        PINNAME CLKA;
PIN
        PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/13/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim888.A_pins<53>
        = BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/13/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim888.A"
        PINNAME CLKA;
PIN
        PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/12/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim892.A_pins<53>
        = BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/12/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim892.A"
        PINNAME CLKA;
PIN
        PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/11/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim896.A_pins<53>
        = BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/11/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim896.A"
        PINNAME CLKA;
PIN
        PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/10/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim900.A_pins<53>
        = BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/10/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim900.A"
        PINNAME CLKA;
PIN
        PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/9/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim904.A_pins<53>
        = BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/9/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim904.A"
        PINNAME CLKA;
PIN
        PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/8/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim908.A_pins<53>
        = BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/8/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim908.A"
        PINNAME CLKA;
PIN
        PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/7/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim912.A_pins<53>
        = BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/7/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim912.A"
        PINNAME CLKA;
PIN
        PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/6/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim916.A_pins<53>
        = BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/6/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim916.A"
        PINNAME CLKA;
PIN
        PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/5/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim920.A_pins<53>
        = BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/5/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim920.A"
        PINNAME CLKA;
PIN
        PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/4/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim924.A_pins<53>
        = BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/4/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim924.A"
        PINNAME CLKA;
PIN
        PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/3/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim928.A_pins<53>
        = BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/3/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim928.A"
        PINNAME CLKA;
PIN
        PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/2/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim932.A_pins<53>
        = BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/2/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim932.A"
        PINNAME CLKA;
PIN
        PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/1/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim936.A_pins<53>
        = BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/1/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim936.A"
        PINNAME CLKA;
PIN
        PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/0/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim940.A_pins<53>
        = BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/0/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim940.A"
        PINNAME CLKA;
TIMEGRP J_CLK = BEL "PLL/chipscope/i_icon/icon/u_icon/u_tdi_reg" BEL
        "PLL/chipscope/i_icon/icon/u_icon/u_tdo_reg" BEL
        "PLL/chipscope/i_icon/icon/u_icon/u_cmd/g_target/15/i_eq0/u_target"
        BEL
        "PLL/chipscope/i_icon/icon/u_icon/u_cmd/g_target/14/i_ne0/u_target"
        BEL
        "PLL/chipscope/i_icon/icon/u_icon/u_cmd/g_target/13/i_ne0/u_target"
        BEL
        "PLL/chipscope/i_icon/icon/u_icon/u_cmd/g_target/12/i_ne0/u_target"
        BEL
        "PLL/chipscope/i_icon/icon/u_icon/u_cmd/g_target/11/i_ne0/u_target"
        BEL
        "PLL/chipscope/i_icon/icon/u_icon/u_cmd/g_target/10/i_ne0/u_target"
        BEL "PLL/chipscope/i_icon/icon/u_icon/u_cmd/g_target/9/i_ne0/u_target"
        BEL "PLL/chipscope/i_icon/icon/u_icon/u_cmd/g_target/8/i_ne0/u_target"
        BEL "PLL/chipscope/i_icon/icon/u_icon/u_cmd/g_target/7/i_ne0/u_target"
        BEL "PLL/chipscope/i_icon/icon/u_icon/u_cmd/g_target/6/i_ne0/u_target"
        BEL
        "PLL/chipscope/i_icon/icon/u_icon/u_sync/g_sync_word/6/i_eq0/u_fdr"
        BEL
        "PLL/chipscope/i_icon/icon/u_icon/u_sync/g_sync_word/5/i_ne0/u_fdr"
        BEL
        "PLL/chipscope/i_icon/icon/u_icon/u_sync/g_sync_word/4/i_ne0/u_fdr"
        BEL
        "PLL/chipscope/i_icon/icon/u_icon/u_sync/g_sync_word/3/i_ne0/u_fdr"
        BEL
        "PLL/chipscope/i_icon/icon/u_icon/u_sync/g_sync_word/2/i_ne0/u_fdr"
        BEL
        "PLL/chipscope/i_icon/icon/u_icon/u_sync/g_sync_word/1/i_ne0/u_fdr"
        BEL
        "PLL/chipscope/i_icon/icon/u_icon/u_sync/g_sync_word/0/i_ne0/u_fdr"
        BEL "PLL/chipscope/i_icon/icon/u_icon/u_sync/u_sync" BEL
        "PLL/chipscope/i_icon/icon/u_icon/u_stat/u_stat_cnt/g/5/u_fdre" BEL
        "PLL/chipscope/i_icon/icon/u_icon/u_stat/u_stat_cnt/g/4/u_fdre" BEL
        "PLL/chipscope/i_icon/icon/u_icon/u_stat/u_stat_cnt/g/3/u_fdre" BEL
        "PLL/chipscope/i_icon/icon/u_icon/u_stat/u_stat_cnt/g/2/u_fdre" BEL
        "PLL/chipscope/i_icon/icon/u_icon/u_stat/u_stat_cnt/g/1/u_fdre" BEL
        "PLL/chipscope/i_icon/icon/u_icon/u_stat/u_stat_cnt/g/0/u_fdre" BEL
        "PLL/chipscope/i_icon/icon/u_icon/u_stat/u_tdo" BEL
        "PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_out/0/async_out_cell/shift_reg"
        BEL
        "PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_out/0/async_out_cell/user_reg"
        BEL
        "PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_out/1/async_out_cell/shift_reg"
        BEL
        "PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_out/1/async_out_cell/user_reg"
        BEL
        "PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_out/2/async_out_cell/shift_reg"
        BEL
        "PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_out/2/async_out_cell/user_reg"
        BEL
        "PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_out/3/async_out_cell/shift_reg"
        BEL
        "PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_out/3/async_out_cell/user_reg"
        BEL
        "PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_out/4/async_out_cell/shift_reg"
        BEL
        "PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_out/4/async_out_cell/user_reg"
        BEL
        "PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_out/5/async_out_cell/shift_reg"
        BEL
        "PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_out/5/async_out_cell/user_reg"
        BEL
        "PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_out/6/async_out_cell/shift_reg"
        BEL
        "PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_out/6/async_out_cell/user_reg"
        BEL
        "PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_out/7/async_out_cell/shift_reg"
        BEL
        "PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_out/7/async_out_cell/user_reg"
        BEL
        "PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_out/8/async_out_cell/shift_reg"
        BEL
        "PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_out/8/async_out_cell/user_reg"
        BEL
        "PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_out/9/async_out_cell/shift_reg"
        BEL
        "PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_out/9/async_out_cell/user_reg"
        BEL
        "PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_out/10/async_out_cell/shift_reg"
        BEL
        "PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_out/10/async_out_cell/user_reg"
        BEL
        "PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_out/11/async_out_cell/shift_reg"
        BEL
        "PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_out/11/async_out_cell/user_reg"
        BEL
        "PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_out/12/async_out_cell/shift_reg"
        BEL
        "PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_out/12/async_out_cell/user_reg"
        BEL
        "PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_out/13/async_out_cell/shift_reg"
        BEL
        "PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_out/13/async_out_cell/user_reg"
        BEL
        "PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_out/14/async_out_cell/shift_reg"
        BEL
        "PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_out/14/async_out_cell/user_reg"
        BEL
        "PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_out/15/async_out_cell/shift_reg"
        BEL
        "PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_out/15/async_out_cell/user_reg"
        BEL
        "PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_out/16/async_out_cell/shift_reg"
        BEL
        "PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_out/16/async_out_cell/user_reg"
        BEL
        "PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_out/17/async_out_cell/shift_reg"
        BEL
        "PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_out/17/async_out_cell/user_reg"
        BEL
        "PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_out/18/async_out_cell/shift_reg"
        BEL
        "PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_out/18/async_out_cell/user_reg"
        BEL
        "PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_out/19/async_out_cell/shift_reg"
        BEL
        "PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_out/19/async_out_cell/user_reg"
        BEL
        "PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_out/20/async_out_cell/shift_reg"
        BEL
        "PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_out/20/async_out_cell/user_reg"
        BEL
        "PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_out/21/async_out_cell/shift_reg"
        BEL
        "PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_out/21/async_out_cell/user_reg"
        BEL
        "PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_out/22/async_out_cell/shift_reg"
        BEL
        "PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_out/22/async_out_cell/user_reg"
        BEL
        "PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_out/23/async_out_cell/shift_reg"
        BEL
        "PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_out/23/async_out_cell/user_reg"
        BEL
        "PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_out/24/async_out_cell/shift_reg"
        BEL
        "PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_out/25/async_out_cell/shift_reg"
        BEL
        "PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_out/26/async_out_cell/shift_reg"
        BEL
        "PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_out/27/async_out_cell/shift_reg"
        BEL
        "PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_out/28/async_out_cell/shift_reg"
        BEL
        "PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_out/29/async_out_cell/shift_reg"
        BEL
        "PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_out/30/async_out_cell/shift_reg"
        BEL
        "PLL/chipscope/i_vio_control/vio_control/i_vio/gen_async_out/31/async_out_cell/shift_reg"
        BEL
        "PLL/chipscope/i_vio_control/vio_control/i_vio/gen_update_out/32/update_cell/shift_reg"
        BEL
        "PLL/chipscope/i_vio_control/vio_control/i_vio/gen_update_out/32/update_cell/gen_no_clk/user_reg"
        BEL
        "PLL/chipscope/i_vio_control/vio_control/i_vio/gen_update_out/33/update_cell/shift_reg"
        BEL
        "PLL/chipscope/i_vio_control/vio_control/i_vio/gen_update_out/33/update_cell/gen_no_clk/user_reg"
        BEL
        "PLL/chipscope/i_vio_control/vio_control/i_vio/gen_update_out/34/update_cell/shift_reg"
        BEL
        "PLL/chipscope/i_vio_control/vio_control/i_vio/gen_update_out/34/update_cell/gen_no_clk/user_reg"
        BEL
        "PLL/chipscope/i_vio_control/vio_control/i_vio/gen_update_out/35/update_cell/shift_reg"
        BEL
        "PLL/chipscope/i_vio_control/vio_control/i_vio/gen_update_out/35/update_cell/gen_no_clk/user_reg"
        BEL
        "PLL/chipscope/i_vio_control/vio_control/i_vio/gen_update_out/36/update_cell/shift_reg"
        BEL
        "PLL/chipscope/i_vio_control/vio_control/i_vio/gen_update_out/36/update_cell/gen_no_clk/user_reg"
        BEL
        "PLL/chipscope/i_vio_control/vio_control/i_vio/gen_update_out/37/update_cell/shift_reg"
        BEL
        "PLL/chipscope/i_vio_control/vio_control/i_vio/gen_update_out/37/update_cell/gen_no_clk/user_reg"
        BEL
        "PLL/chipscope/i_vio_control/vio_control/i_vio/gen_update_out/38/update_cell/shift_reg"
        BEL
        "PLL/chipscope/i_vio_control/vio_control/i_vio/gen_update_out/38/update_cell/gen_no_clk/user_reg"
        BEL
        "PLL/chipscope/i_vio_control/vio_control/i_vio/gen_update_out/39/update_cell/shift_reg"
        BEL
        "PLL/chipscope/i_vio_control/vio_control/i_vio/gen_update_out/39/update_cell/gen_no_clk/user_reg"
        BEL
        "PLL/chipscope/i_vio_control/vio_control/i_vio/gen_update_out/40/update_cell/shift_reg"
        BEL
        "PLL/chipscope/i_vio_control/vio_control/i_vio/gen_update_out/40/update_cell/gen_no_clk/user_reg"
        BEL
        "PLL/chipscope/i_vio_control/vio_control/i_vio/gen_update_out/41/update_cell/shift_reg"
        BEL
        "PLL/chipscope/i_vio_control/vio_control/i_vio/gen_update_out/41/update_cell/gen_no_clk/user_reg"
        BEL
        "PLL/chipscope/i_vio_control/vio_control/i_vio/gen_update_out/42/update_cell/shift_reg"
        BEL
        "PLL/chipscope/i_vio_control/vio_control/i_vio/gen_update_out/42/update_cell/gen_no_clk/user_reg"
        BEL
        "PLL/chipscope/i_vio_control/vio_control/i_vio/gen_update_out/43/update_cell/shift_reg"
        BEL
        "PLL/chipscope/i_vio_control/vio_control/i_vio/gen_update_out/43/update_cell/gen_no_clk/user_reg"
        BEL
        "PLL/chipscope/i_vio_control/vio_control/i_vio/gen_update_out/44/update_cell/shift_reg"
        BEL
        "PLL/chipscope/i_vio_control/vio_control/i_vio/gen_update_out/44/update_cell/gen_no_clk/user_reg"
        BEL
        "PLL/chipscope/i_vio_control/vio_control/i_vio/gen_update_out/45/update_cell/shift_reg"
        BEL
        "PLL/chipscope/i_vio_control/vio_control/i_vio/gen_update_out/45/update_cell/gen_no_clk/user_reg"
        BEL
        "PLL/chipscope/i_vio_control/vio_control/i_vio/gen_update_out/46/update_cell/shift_reg"
        BEL
        "PLL/chipscope/i_vio_control/vio_control/i_vio/gen_update_out/46/update_cell/gen_no_clk/user_reg"
        BEL
        "PLL/chipscope/i_vio_control/vio_control/i_vio/gen_update_out/47/update_cell/shift_reg"
        BEL
        "PLL/chipscope/i_vio_control/vio_control/i_vio/gen_update_out/47/update_cell/gen_no_clk/user_reg"
        BEL
        "PLL/chipscope/i_vio_control/vio_control/i_vio/gen_update_out/48/update_cell/shift_reg"
        BEL
        "PLL/chipscope/i_vio_control/vio_control/i_vio/gen_update_out/48/update_cell/gen_no_clk/user_reg"
        BEL
        "PLL/chipscope/i_vio_control/vio_control/i_vio/gen_update_out/49/update_cell/shift_reg"
        BEL
        "PLL/chipscope/i_vio_control/vio_control/i_vio/gen_update_out/49/update_cell/gen_no_clk/user_reg"
        BEL
        "PLL/chipscope/i_vio_control/vio_control/i_vio/gen_update_out/50/update_cell/shift_reg"
        BEL
        "PLL/chipscope/i_vio_control/vio_control/i_vio/gen_update_out/50/update_cell/gen_no_clk/user_reg"
        BEL
        "PLL/chipscope/i_vio_control/vio_control/i_vio/gen_update_out/51/update_cell/shift_reg"
        BEL
        "PLL/chipscope/i_vio_control/vio_control/i_vio/gen_update_out/51/update_cell/gen_no_clk/user_reg"
        BEL
        "PLL/chipscope/i_vio_control/vio_control/i_vio/gen_update_out/52/update_cell/shift_reg"
        BEL
        "PLL/chipscope/i_vio_control/vio_control/i_vio/gen_update_out/52/update_cell/gen_no_clk/user_reg"
        BEL
        "PLL/chipscope/i_vio_control/vio_control/i_vio/gen_update_out/53/update_cell/shift_reg"
        BEL
        "PLL/chipscope/i_vio_control/vio_control/i_vio/gen_update_out/53/update_cell/gen_no_clk/user_reg"
        BEL
        "PLL/chipscope/i_vio_control/vio_control/i_vio/gen_update_out/54/update_cell/shift_reg"
        BEL
        "PLL/chipscope/i_vio_control/vio_control/i_vio/gen_update_out/54/update_cell/gen_no_clk/user_reg"
        BEL
        "PLL/chipscope/i_vio_control/vio_control/i_vio/gen_update_out/55/update_cell/shift_reg"
        BEL
        "PLL/chipscope/i_vio_control/vio_control/i_vio/gen_update_out/55/update_cell/gen_no_clk/user_reg"
        BEL
        "PLL/chipscope/i_vio_control/vio_control/i_vio/u_status/u_stat_cnt/g/6/u_fdre"
        BEL
        "PLL/chipscope/i_vio_control/vio_control/i_vio/u_status/u_stat_cnt/g/5/u_fdre"
        BEL
        "PLL/chipscope/i_vio_control/vio_control/i_vio/u_status/u_stat_cnt/g/4/u_fdre"
        BEL
        "PLL/chipscope/i_vio_control/vio_control/i_vio/u_status/u_stat_cnt/g/3/u_fdre"
        BEL
        "PLL/chipscope/i_vio_control/vio_control/i_vio/u_status/u_stat_cnt/g/2/u_fdre"
        BEL
        "PLL/chipscope/i_vio_control/vio_control/i_vio/u_status/u_stat_cnt/g/1/u_fdre"
        BEL
        "PLL/chipscope/i_vio_control/vio_control/i_vio/u_status/u_stat_cnt/g/0/u_fdre"
        BEL "PLL/chipscope/i_vio_control/vio_control/i_vio/u_status/u_tdo" BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_out/0/async_out_cell/shift_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_out/0/async_out_cell/user_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_out/1/async_out_cell/shift_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_out/1/async_out_cell/user_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_out/2/async_out_cell/shift_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_out/2/async_out_cell/user_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_out/3/async_out_cell/shift_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_out/3/async_out_cell/user_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_out/4/async_out_cell/shift_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_out/4/async_out_cell/user_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_out/5/async_out_cell/shift_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_out/5/async_out_cell/user_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_out/6/async_out_cell/shift_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_out/6/async_out_cell/user_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_out/7/async_out_cell/shift_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_out/7/async_out_cell/user_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_out/8/async_out_cell/shift_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_out/8/async_out_cell/user_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_out/9/async_out_cell/shift_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_out/9/async_out_cell/user_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_out/10/async_out_cell/shift_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_out/10/async_out_cell/user_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_out/11/async_out_cell/shift_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_out/11/async_out_cell/user_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_out/12/async_out_cell/shift_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_out/12/async_out_cell/user_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_out/13/async_out_cell/shift_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_out/13/async_out_cell/user_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_out/14/async_out_cell/shift_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_out/14/async_out_cell/user_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_out/15/async_out_cell/shift_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_out/15/async_out_cell/user_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_out/16/async_out_cell/shift_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_out/16/async_out_cell/user_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_out/17/async_out_cell/shift_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_out/17/async_out_cell/user_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_out/18/async_out_cell/shift_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_out/18/async_out_cell/user_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_out/19/async_out_cell/shift_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_out/19/async_out_cell/user_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_out/20/async_out_cell/shift_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_out/20/async_out_cell/user_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_out/21/async_out_cell/shift_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_out/21/async_out_cell/user_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_out/22/async_out_cell/shift_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_out/22/async_out_cell/user_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_out/23/async_out_cell/shift_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_out/23/async_out_cell/user_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_out/24/async_out_cell/shift_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_out/24/async_out_cell/user_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_out/25/async_out_cell/shift_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_out/25/async_out_cell/user_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_out/26/async_out_cell/shift_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_out/26/async_out_cell/user_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_out/27/async_out_cell/shift_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_out/27/async_out_cell/user_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_out/28/async_out_cell/shift_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_out/29/async_out_cell/shift_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_out/30/async_out_cell/shift_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_out/31/async_out_cell/shift_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_update_out/32/update_cell/shift_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_update_out/32/update_cell/gen_no_clk/user_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_update_out/33/update_cell/shift_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_update_out/33/update_cell/gen_no_clk/user_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_update_out/34/update_cell/shift_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_update_out/34/update_cell/gen_no_clk/user_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_update_out/35/update_cell/shift_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_update_out/35/update_cell/gen_no_clk/user_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_update_out/36/update_cell/shift_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_update_out/36/update_cell/gen_no_clk/user_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_update_out/37/update_cell/shift_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_update_out/37/update_cell/gen_no_clk/user_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_update_out/38/update_cell/shift_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_update_out/38/update_cell/gen_no_clk/user_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_update_out/39/update_cell/shift_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_update_out/39/update_cell/gen_no_clk/user_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_update_out/40/update_cell/shift_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_update_out/40/update_cell/gen_no_clk/user_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_update_out/41/update_cell/shift_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_update_out/41/update_cell/gen_no_clk/user_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_update_out/42/update_cell/shift_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_update_out/42/update_cell/gen_no_clk/user_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_update_out/43/update_cell/shift_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_update_out/43/update_cell/gen_no_clk/user_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_update_out/44/update_cell/shift_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_update_out/44/update_cell/gen_no_clk/user_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_update_out/45/update_cell/shift_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_update_out/45/update_cell/gen_no_clk/user_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_update_out/46/update_cell/shift_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_update_out/46/update_cell/gen_no_clk/user_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_update_out/47/update_cell/shift_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_update_out/47/update_cell/gen_no_clk/user_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_update_out/48/update_cell/shift_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_update_out/48/update_cell/gen_no_clk/user_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_update_out/49/update_cell/shift_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_update_out/49/update_cell/gen_no_clk/user_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_update_out/50/update_cell/shift_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_update_out/50/update_cell/gen_no_clk/user_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_update_out/51/update_cell/shift_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_update_out/51/update_cell/gen_no_clk/user_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_update_out/52/update_cell/shift_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_update_out/52/update_cell/gen_no_clk/user_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_update_out/53/update_cell/shift_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_update_out/53/update_cell/gen_no_clk/user_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_update_out/54/update_cell/shift_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_update_out/54/update_cell/gen_no_clk/user_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_update_out/55/update_cell/shift_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_update_out/55/update_cell/gen_no_clk/user_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_update_out/56/update_cell/shift_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_update_out/56/update_cell/gen_no_clk/user_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_update_out/57/update_cell/shift_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_update_out/57/update_cell/gen_no_clk/user_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_update_out/58/update_cell/shift_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_update_out/58/update_cell/gen_no_clk/user_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_update_out/59/update_cell/shift_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_update_out/59/update_cell/gen_no_clk/user_reg"
        BEL "PLL/chipscope/i_vio/vio/i_vio/reset_f_edge/u_dout0" BEL
        "PLL/chipscope/i_vio/vio/i_vio/reset_f_edge/u_dout1" BEL
        "PLL/chipscope/i_vio/vio/i_vio/reset_f_edge/i_h2l/u_dout" BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_in/0/async_in_cell/s_user_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_in/0/async_in_cell/s_async_r_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_in/0/async_in_cell/s_async_f_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_in/0/async_in_cell/s_async_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_in/1/async_in_cell/s_user_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_in/1/async_in_cell/s_async_r_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_in/1/async_in_cell/s_async_f_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_in/1/async_in_cell/s_async_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_in/2/async_in_cell/s_user_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_in/2/async_in_cell/s_async_r_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_in/2/async_in_cell/s_async_f_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_in/2/async_in_cell/s_async_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_in/3/async_in_cell/s_user_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_in/3/async_in_cell/s_async_r_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_in/3/async_in_cell/s_async_f_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_in/3/async_in_cell/s_async_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_in/4/async_in_cell/s_user_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_in/4/async_in_cell/s_async_r_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_in/4/async_in_cell/s_async_f_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_in/4/async_in_cell/s_async_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_in/5/async_in_cell/s_user_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_in/5/async_in_cell/s_async_r_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_in/5/async_in_cell/s_async_f_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_in/5/async_in_cell/s_async_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_in/6/async_in_cell/s_user_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_in/6/async_in_cell/s_async_r_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_in/6/async_in_cell/s_async_f_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_in/6/async_in_cell/s_async_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_in/7/async_in_cell/s_user_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_in/7/async_in_cell/s_async_r_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_in/7/async_in_cell/s_async_f_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_in/7/async_in_cell/s_async_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_in/8/async_in_cell/s_user_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_in/8/async_in_cell/s_async_r_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_in/8/async_in_cell/s_async_f_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_in/8/async_in_cell/s_async_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_in/9/async_in_cell/s_user_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_in/9/async_in_cell/s_async_r_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_in/9/async_in_cell/s_async_f_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_in/9/async_in_cell/s_async_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_in/10/async_in_cell/s_user_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_in/10/async_in_cell/s_async_r_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_in/10/async_in_cell/s_async_f_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_in/10/async_in_cell/s_async_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_in/11/async_in_cell/s_user_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_in/11/async_in_cell/s_async_r_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_in/11/async_in_cell/s_async_f_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_in/11/async_in_cell/s_async_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_in/12/async_in_cell/s_user_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_in/12/async_in_cell/s_async_r_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_in/12/async_in_cell/s_async_f_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_in/12/async_in_cell/s_async_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_in/13/async_in_cell/s_user_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_in/13/async_in_cell/s_async_r_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_in/13/async_in_cell/s_async_f_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_in/13/async_in_cell/s_async_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_in/14/async_in_cell/s_user_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_in/14/async_in_cell/s_async_r_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_in/14/async_in_cell/s_async_f_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_in/14/async_in_cell/s_async_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_in/15/async_in_cell/s_user_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_in/15/async_in_cell/s_async_r_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_in/15/async_in_cell/s_async_f_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_in/15/async_in_cell/s_async_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_in/16/async_in_cell/s_user_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_in/16/async_in_cell/s_async_r_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_in/16/async_in_cell/s_async_f_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_in/16/async_in_cell/s_async_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_in/17/async_in_cell/s_user_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_in/17/async_in_cell/s_async_r_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_in/17/async_in_cell/s_async_f_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_in/17/async_in_cell/s_async_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_in/18/async_in_cell/s_user_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_in/18/async_in_cell/s_async_r_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_in/18/async_in_cell/s_async_f_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_in/18/async_in_cell/s_async_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_in/19/async_in_cell/s_user_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_in/19/async_in_cell/s_async_r_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_in/19/async_in_cell/s_async_f_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_in/19/async_in_cell/s_async_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_in/20/async_in_cell/s_user_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_in/20/async_in_cell/s_async_r_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_in/20/async_in_cell/s_async_f_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_in/20/async_in_cell/s_async_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_in/21/async_in_cell/s_user_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_in/21/async_in_cell/s_async_r_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_in/21/async_in_cell/s_async_f_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_in/21/async_in_cell/s_async_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_in/22/async_in_cell/s_user_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_in/22/async_in_cell/s_async_r_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_in/22/async_in_cell/s_async_f_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_in/22/async_in_cell/s_async_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_in/23/async_in_cell/s_user_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_in/23/async_in_cell/s_async_r_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_in/23/async_in_cell/s_async_f_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_in/23/async_in_cell/s_async_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_in/24/async_in_cell/s_user_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_in/24/async_in_cell/s_async_r_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_in/24/async_in_cell/s_async_f_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_in/24/async_in_cell/s_async_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_in/25/async_in_cell/s_user_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_in/25/async_in_cell/s_async_r_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_in/25/async_in_cell/s_async_f_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_in/25/async_in_cell/s_async_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_in/26/async_in_cell/s_user_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_in/26/async_in_cell/s_async_r_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_in/26/async_in_cell/s_async_f_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_in/26/async_in_cell/s_async_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_in/27/async_in_cell/s_user_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_in/27/async_in_cell/s_async_r_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_in/27/async_in_cell/s_async_f_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_in/27/async_in_cell/s_async_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_in/28/async_in_cell/s_user_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_in/28/async_in_cell/s_async_r_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_in/28/async_in_cell/s_async_f_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_in/28/async_in_cell/s_async_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_in/29/async_in_cell/s_user_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_in/29/async_in_cell/s_async_r_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_in/29/async_in_cell/s_async_f_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_in/29/async_in_cell/s_async_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_in/30/async_in_cell/s_user_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_in/30/async_in_cell/s_async_r_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_in/30/async_in_cell/s_async_f_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_in/30/async_in_cell/s_async_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_in/31/async_in_cell/s_user_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_in/31/async_in_cell/s_async_r_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_in/31/async_in_cell/s_async_f_reg"
        BEL
        "PLL/chipscope/i_vio/vio/i_vio/gen_async_in/31/async_in_cell/s_async_reg"
        BEL "PLL/chipscope/i_vio/vio/i_vio/u_data_out" BEL
        "PLL/chipscope/i_vio/vio/i_vio/u_status/u_stat_cnt/g/6/u_fdre" BEL
        "PLL/chipscope/i_vio/vio/i_vio/u_status/u_stat_cnt/g/5/u_fdre" BEL
        "PLL/chipscope/i_vio/vio/i_vio/u_status/u_stat_cnt/g/4/u_fdre" BEL
        "PLL/chipscope/i_vio/vio/i_vio/u_status/u_stat_cnt/g/3/u_fdre" BEL
        "PLL/chipscope/i_vio/vio/i_vio/u_status/u_stat_cnt/g/2/u_fdre" BEL
        "PLL/chipscope/i_vio/vio/i_vio/u_status/u_stat_cnt/g/1/u_fdre" BEL
        "PLL/chipscope/i_vio/vio/i_vio/u_status/u_stat_cnt/g/0/u_fdre" BEL
        "PLL/chipscope/i_vio/vio/i_vio/u_status/u_tdo" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_rst/u_halt_xfer/u_tfdre"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_rst/u_arm_xfer/u_tfdre"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_trig/u_tm/g_nmu/0/u_m/u_mu/i_mut_gand/u_match/pd_rpm/i_twmod8_ne0/i_yes_rpm/i_srlt_eq_2/u_srlh"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_trig/u_tm/g_nmu/0/u_m/u_mu/i_mut_gand/u_match/pd_rpm/i_twmod8_ne0/i_yes_rpm/i_yes_muxh/u_muxh/O.SLICE_GMC15_BLACKBOX"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_trig/u_tm/g_nmu/0/u_m/u_mu/i_mut_gand/u_match/pd_rpm/i_twmod8_ne0/i_yes_rpm/i_srlt_eq_2/u_srll"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_trig/u_tc/i_tseq_neq2/u_tc_equation/i_srlt_ne_1/i_nmu_1_to_4/u_tcl/i_nmu_eq1/u_idout/i_srl_t2/u_srlc16e"
        BEL
        "PLL/chipscope/i_ila_6CH/i_yes_d/u_ila/u_trig/u_tc/i_tseq_neq2/u_tc_equation/i_srlt_ne_1/i_nmu_1_to_4/u_tcl/idout.SLICE_FMC15_BLACKBOX"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_trig/u_tc/i_storage_qual/u_storage_qual/i_srlt_ne_1/i_nmu_1_to_4/u_tcl/i_nmu_eq1/u_idout/i_srl_t2/u_srlc16e"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_stat/u_stat_cnt/g/8/u_fdre"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_stat/u_stat_cnt/g/7/u_fdre"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_stat/u_stat_cnt/g/6/u_fdre"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_stat/u_stat_cnt/g/5/u_fdre"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_stat/u_stat_cnt/g/4/u_fdre"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_stat/u_stat_cnt/g/3/u_fdre"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_stat/u_stat_cnt/g/2/u_fdre"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_stat/u_stat_cnt/g/1/u_fdre"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_stat/u_stat_cnt/g/0/u_fdre"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_stat/u_dsl1/u_tfdre"
        BEL "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_stat/u_dirty" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_stat/u_reset_edge/u_dout0"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_stat/u_reset_edge/u_dout1"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_stat/u_reset_edge/i_h2l/u_dout"
        BEL "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_stat/u_tdo" BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_0_to_64k/f_sel/0/u_sel"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_0_to_64k/f_sel/1/u_sel"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_0_to_64k/f_sel/2/u_sel"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_0_to_64k/f_sel/3/u_sel"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_0_to_64k/f_sel/4/u_sel"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_0_to_64k/f_sel/5/u_sel"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_0_to_64k/f_sel/6/u_sel"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_0_to_64k/f_sel/7/u_sel"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_0_to_64k/f_sel/8/u_sel"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_0_to_64k/f_sel/9/u_sel"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_0_to_64k/f_sel/10/u_sel"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_0_to_64k/f_sel/11/u_sel"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_0_to_64k/f_sel/12/u_sel"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_0_to_64k/f_sel/13/u_sel"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_0_to_64k/f_sel/14/u_sel"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_0_to_64k/f_sel/15/u_sel"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_0_to_64k/i_srl/u_selx"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/u_scnt_cmp/pd_rpm/i_tw_gte8/f_tw/0/i_yes_rpm/i_srlt_eq_2/u_srlh"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/u_scnt_cmp/pd_rpm/i_tw_gte8/f_tw/0/i_yes_rpm/u_muxh/O.SLICE_GMC15_BLACKBOX"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/u_scnt_cmp/pd_rpm/i_tw_gte8/f_tw/0/i_yes_rpm/i_srlt_eq_2/u_srll"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/u_scnt_cmp/pd_rpm/i_tw_gte8/f_tw/0/i_yes_rpm/u_muxh/O.SLICE_FMC15_BLACKBOX"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/u_scnt_cmp/pd_rpm/i_twmod8_ne0/i_yes_rpm/i_srlt_eq_2/u_srlh"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/u_scnt_cmp/pd_rpm/i_twmod8_ne0/i_yes_rpm/i_yes_muxh/u_muxh/O.SLICE_GMC15_BLACKBOX"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/u_scnt_cmp/pd_rpm/i_twmod8_ne0/i_yes_rpm/i_srlt_eq_2/u_srll"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/u_scnt_cmp/pd_rpm/i_twmod8_ne0/i_yes_rpm/i_yes_muxh/u_muxh/O.SLICE_FMC15_BLACKBOX"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/u_wcnt_hcmp/pd_rpm/i_tw_gte8/f_tw/0/i_yes_rpm/i_srlt_eq_2/u_srlh"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/u_wcnt_hcmp/pd_rpm/i_tw_gte8/f_tw/0/i_yes_rpm/u_muxh/O.SLICE_GMC15_BLACKBOX"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/u_wcnt_hcmp/pd_rpm/i_tw_gte8/f_tw/0/i_yes_rpm/i_srlt_eq_2/u_srll"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/u_wcnt_hcmp/pd_rpm/i_tw_gte8/f_tw/0/i_yes_rpm/u_muxh/O.SLICE_FMC15_BLACKBOX"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/u_wcnt_hcmp/pd_rpm/i_twmod8_ne0/i_yes_rpm/i_srlt_eq_2/u_srlh"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/u_wcnt_hcmp/pd_rpm/i_twmod8_ne0/i_yes_rpm/i_yes_muxh/u_muxh/O.SLICE_GMC15_BLACKBOX"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/u_wcnt_hcmp/pd_rpm/i_twmod8_ne0/i_yes_rpm/i_srlt_eq_2/u_srll"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/u_wcnt_hcmp/pd_rpm/i_twmod8_ne0/i_yes_rpm/i_yes_muxh/u_muxh/O.SLICE_FMC15_BLACKBOX"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/u_wcnt_lcmp/pd_rpm/i_tw_gte8/f_tw/0/i_yes_rpm/i_srlt_eq_2/u_srlh"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/u_wcnt_lcmp/pd_rpm/i_tw_gte8/f_tw/0/i_yes_rpm/u_muxh/O.SLICE_GMC15_BLACKBOX"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/u_wcnt_lcmp/pd_rpm/i_tw_gte8/f_tw/0/i_yes_rpm/i_srlt_eq_2/u_srll"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/u_wcnt_lcmp/pd_rpm/i_tw_gte8/f_tw/0/i_yes_rpm/u_muxh/O.SLICE_FMC15_BLACKBOX"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/u_wcnt_lcmp/pd_rpm/i_twmod8_ne0/i_yes_rpm/i_srlt_eq_2/u_srlh"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/u_wcnt_lcmp/pd_rpm/i_twmod8_ne0/i_yes_rpm/i_yes_muxh/u_muxh/O.SLICE_GMC15_BLACKBOX"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/u_wcnt_lcmp/pd_rpm/i_twmod8_ne0/i_yes_rpm/i_srlt_eq_2/u_srll"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/u_wcnt_lcmp/pd_rpm/i_twmod8_ne0/i_yes_rpm/i_yes_muxh/u_muxh/O.SLICE_FMC15_BLACKBOX"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_ns1/pd_rpm/i_srl_t2/i_yes_rpm/i_no_s3/ug3_cfglut4"
        BEL
        "PLL/chipscope/i_ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_ns1/jo_0.SLICE_GMC15_BLACKBOX"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_ns1/pd_rpm/i_srl_t2/i_yes_rpm/i_no_s3/uf3_cfglut4"
        BEL
        "PLL/chipscope/i_ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_ns1/jo_0.SLICE_FMC15_BLACKBOX"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_ns1/pd_rpm/i_srl_t2/i_yes_rpm/i_no_s3/ug2_cfglut4"
        BEL
        "PLL/chipscope/i_ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_ns1/ko_0.SLICE_GMC15_BLACKBOX"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_ns1/pd_rpm/i_srl_t2/i_yes_rpm/i_no_s3/uf2_cfglut4"
        BEL
        "PLL/chipscope/i_ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_ns1/ko_0.SLICE_FMC15_BLACKBOX"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_ns1/pd_rpm/i_srl_t2/i_yes_rpm/i_no_s3/ug1_cfglut4"
        BEL
        "PLL/chipscope/i_ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_ns1/jo_2.SLICE_GMC15_BLACKBOX"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_ns1/pd_rpm/i_srl_t2/i_yes_rpm/i_no_s3/uf1_cfglut4"
        BEL
        "PLL/chipscope/i_ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_ns1/jo_2.SLICE_FMC15_BLACKBOX"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_ns1/pd_rpm/i_srl_t2/i_yes_rpm/i_no_s3/ug0_cfglut4"
        BEL
        "PLL/chipscope/i_ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_ns1/ko_1.SLICE_GMC15_BLACKBOX"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_ns1/pd_rpm/i_srl_t2/i_yes_rpm/i_no_s3/uf0_cfglut4"
        BEL
        "PLL/chipscope/i_ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_ns1/ko_1.SLICE_FMC15_BLACKBOX"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_ns0/pd_rpm/i_srl_t2/i_yes_rpm/i_no_s3/ug3_cfglut4"
        BEL
        "PLL/chipscope/i_ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_ns0/jo_0.SLICE_GMC15_BLACKBOX"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_ns0/pd_rpm/i_srl_t2/i_yes_rpm/i_no_s3/uf3_cfglut4"
        BEL
        "PLL/chipscope/i_ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_ns0/jo_0.SLICE_FMC15_BLACKBOX"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_ns0/pd_rpm/i_srl_t2/i_yes_rpm/i_no_s3/ug2_cfglut4"
        BEL
        "PLL/chipscope/i_ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_ns0/ko_0.SLICE_GMC15_BLACKBOX"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_ns0/pd_rpm/i_srl_t2/i_yes_rpm/i_no_s3/uf2_cfglut4"
        BEL
        "PLL/chipscope/i_ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_ns0/ko_0.SLICE_FMC15_BLACKBOX"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_ns0/pd_rpm/i_srl_t2/i_yes_rpm/i_no_s3/ug1_cfglut4"
        BEL
        "PLL/chipscope/i_ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_ns0/jo_2.SLICE_GMC15_BLACKBOX"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_ns0/pd_rpm/i_srl_t2/i_yes_rpm/i_no_s3/uf1_cfglut4"
        BEL
        "PLL/chipscope/i_ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_ns0/jo_2.SLICE_FMC15_BLACKBOX"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_ns0/pd_rpm/i_srl_t2/i_yes_rpm/i_no_s3/ug0_cfglut4"
        BEL
        "PLL/chipscope/i_ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_ns0/ko_1.SLICE_GMC15_BLACKBOX"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_ns0/pd_rpm/i_srl_t2/i_yes_rpm/i_no_s3/uf0_cfglut4"
        BEL
        "PLL/chipscope/i_ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_ns0/ko_1.SLICE_FMC15_BLACKBOX"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_scrst/pd_rpm/i_srl_t2/i_yes_rpm/ug1_cfglut4"
        BEL
        "PLL/chipscope/i_ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_scrst/jo_0.SLICE_GMC15_BLACKBOX"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_scrst/pd_rpm/i_srl_t2/i_yes_rpm/uf1_cfglut4"
        BEL
        "PLL/chipscope/i_ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_scrst/jo_0.SLICE_FMC15_BLACKBOX"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_scrst/pd_rpm/i_srl_t2/i_yes_rpm/ug0_cfglut4"
        BEL
        "PLL/chipscope/i_ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/scnt_reset.SLICE_GMC15_BLACKBOX"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_scrst/pd_rpm/i_srl_t2/i_yes_rpm/uf0_cfglut4"
        BEL
        "PLL/chipscope/i_ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/scnt_reset.SLICE_FMC15_BLACKBOX"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_wce/i_srl_t2/u_srlc16e"
        BEL
        "PLL/chipscope/i_ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/scnt_ce.SLICE_GMC15_BLACKBOX"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_sce/i_srl_t2/u_srlc16e"
        BEL
        "PLL/chipscope/i_ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/scnt_ce.SLICE_FMC15_BLACKBOX"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_cmpreset/pd_rpm/i_srl_t2/i_yes_rpm/ug1_cfglut4"
        BEL
        "PLL/chipscope/i_ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_cmpreset/jo_0.SLICE_GMC15_BLACKBOX"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_cmpreset/pd_rpm/i_srl_t2/i_yes_rpm/uf1_cfglut4"
        BEL
        "PLL/chipscope/i_ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_cmpreset/jo_0.SLICE_FMC15_BLACKBOX"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_cmpreset/pd_rpm/i_srl_t2/i_yes_rpm/ug0_cfglut4"
        BEL
        "PLL/chipscope/i_ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/cmp_reset.SLICE_GMC15_BLACKBOX"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_cmpreset/pd_rpm/i_srl_t2/i_yes_rpm/uf0_cfglut4"
        BEL
        "PLL/chipscope/i_ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/cmp_reset.SLICE_FMC15_BLACKBOX"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_cdone/pd_rpm/i_srl_t2/i_yes_rpm/ug1_cfglut4"
        BEL
        "PLL/chipscope/i_ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_cdone/jo_0.SLICE_GMC15_BLACKBOX"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_cdone/pd_rpm/i_srl_t2/i_yes_rpm/uf1_cfglut4"
        BEL
        "PLL/chipscope/i_ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_cdone/jo_0.SLICE_FMC15_BLACKBOX"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_cdone/pd_rpm/i_srl_t2/i_yes_rpm/ug0_cfglut4"
        BEL
        "PLL/chipscope/i_ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_cdone/jo_1.SLICE_GMC15_BLACKBOX"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_cdone/pd_rpm/i_srl_t2/i_yes_rpm/uf0_cfglut4"
        BEL
        "PLL/chipscope/i_ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_cdone/jo_1.SLICE_FMC15_BLACKBOX"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_scmpce/pd_rpm/i_srl_t2/i_yes_rpm/ug_cfglut4"
        BEL
        "PLL/chipscope/i_ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/scnt_cmp_ce.SLICE_GMC15_BLACKBOX"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_scmpce/pd_rpm/i_srl_t2/i_yes_rpm/uf_cfglut4"
        BEL
        "PLL/chipscope/i_ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/scnt_cmp_ce.SLICE_FMC15_BLACKBOX"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_wlcmpce/pd_rpm/i_srl_t2/i_yes_rpm/ug_cfglut4"
        BEL
        "PLL/chipscope/i_ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/wcnt_lcmp_ce.SLICE_GMC15_BLACKBOX"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_wlcmpce/pd_rpm/i_srl_t2/i_yes_rpm/uf_cfglut4"
        BEL
        "PLL/chipscope/i_ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/wcnt_lcmp_ce.SLICE_FMC15_BLACKBOX"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_whcmpce/pd_rpm/i_srl_t2/i_yes_rpm/ug_cfglut4"
        BEL
        "PLL/chipscope/i_ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/wcnt_hcmp_ce.SLICE_GMC15_BLACKBOX"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_whcmpce/pd_rpm/i_srl_t2/i_yes_rpm/uf_cfglut4"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/i_rdaddr/i_ni_gt_1/ine1/u_low_count/g/5/u_fdre"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/i_rdaddr/i_ni_gt_1/ine1/u_low_count/g/4/u_fdre"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/i_rdaddr/i_ni_gt_1/ine1/u_low_count/g/3/u_fdre"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/i_rdaddr/i_ni_gt_1/ine1/u_low_count/g/2/u_fdre"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/i_rdaddr/i_ni_gt_1/ine1/u_low_count/g/1/u_fdre"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/i_rdaddr/i_ni_gt_1/ine1/u_low_count/g/0/u_fdre"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/i_rdaddr/u_hc/g/13/u_fdre"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/i_rdaddr/u_hc/g/12/u_fdre"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/i_rdaddr/u_hc/g/11/u_fdre"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/i_rdaddr/u_hc/g/10/u_fdre"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/i_rdaddr/u_hc/g/9/u_fdre"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/i_rdaddr/u_hc/g/8/u_fdre"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/i_rdaddr/u_hc/g/7/u_fdre"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/i_rdaddr/u_hc/g/6/u_fdre"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/i_rdaddr/u_hc/g/5/u_fdre"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/i_rdaddr/u_hc/g/4/u_fdre"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/i_rdaddr/u_hc/g/3/u_fdre"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/i_rdaddr/u_hc/g/2/u_fdre"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/i_rdaddr/u_hc/g/1/u_fdre"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/i_rdaddr/u_hc/g/0/u_fdre"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/i_mux/g_ff/5/u_ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/i_mux/g_ff/4/u_ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/i_mux/g_ff/3/u_ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/i_mux/g_ff/2/u_ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/i_mux/g_ff/1/u_ff"
        BEL
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/i_mux/g_ff/0/u_ff"
        PIN
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/48/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1025.A_pins<53>"
        PIN
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/47/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1029.A_pins<53>"
        PIN
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/46/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1033.A_pins<53>"
        PIN
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/45/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1037.A_pins<53>"
        PIN
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/44/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1041.A_pins<53>"
        PIN
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/43/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1045.A_pins<53>"
        PIN
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/42/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1049.A_pins<53>"
        PIN
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/41/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1053.A_pins<53>"
        PIN
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/40/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1057.A_pins<53>"
        PIN
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/39/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1061.A_pins<53>"
        PIN
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/38/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1065.A_pins<53>"
        PIN
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/37/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1069.A_pins<53>"
        PIN
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/36/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1073.A_pins<53>"
        PIN
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/35/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1077.A_pins<53>"
        PIN
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/34/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1081.A_pins<53>"
        PIN
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/33/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1085.A_pins<53>"
        PIN
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/32/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1089.A_pins<53>"
        PIN
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/31/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1093.A_pins<53>"
        PIN
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/30/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1097.A_pins<53>"
        PIN
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/29/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1101.A_pins<53>"
        PIN
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/28/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1105.A_pins<53>"
        PIN
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/27/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1109.A_pins<53>"
        PIN
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/26/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1113.A_pins<53>"
        PIN
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/25/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1117.A_pins<53>"
        PIN
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/24/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1121.A_pins<53>"
        PIN
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/23/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1125.A_pins<53>"
        PIN
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/22/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1129.A_pins<53>"
        PIN
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/21/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1133.A_pins<53>"
        PIN
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/20/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1137.A_pins<53>"
        PIN
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/19/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1141.A_pins<53>"
        PIN
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/18/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1145.A_pins<53>"
        PIN
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/17/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1149.A_pins<53>"
        PIN
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/16/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1153.A_pins<53>"
        PIN
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/15/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1157.A_pins<53>"
        PIN
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/14/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1161.A_pins<53>"
        PIN
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/13/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1165.A_pins<53>"
        PIN
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/12/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1169.A_pins<53>"
        PIN
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/11/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1173.A_pins<53>"
        PIN
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/10/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1177.A_pins<53>"
        PIN
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/9/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1181.A_pins<53>"
        PIN
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/8/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1185.A_pins<53>"
        PIN
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/7/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1189.A_pins<53>"
        PIN
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/6/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1193.A_pins<53>"
        PIN
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/5/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1197.A_pins<53>"
        PIN
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/4/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1201.A_pins<53>"
        PIN
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/3/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1205.A_pins<53>"
        PIN
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/2/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1209.A_pins<53>"
        PIN
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/1/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1213.A_pins<53>"
        PIN
        "PLL/chipscope/i_ila_6CH/ila_6CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/0/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim1217.A_pins<53>"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_rst/u_halt_xfer/u_tfdre"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_rst/u_arm_xfer/u_tfdre"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_trig/u_tm/g_nmu/0/u_m/u_mu/i_mut_gand/u_match/pd_rpm/i_twmod8_ne0/i_yes_rpm/i_srlt_eq_2/u_srlh"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_trig/u_tm/g_nmu/0/u_m/u_mu/i_mut_gand/u_match/pd_rpm/i_twmod8_ne0/i_yes_rpm/i_yes_muxh/u_muxh/O.SLICE_GMC15_BLACKBOX"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_trig/u_tm/g_nmu/0/u_m/u_mu/i_mut_gand/u_match/pd_rpm/i_twmod8_ne0/i_yes_rpm/i_srlt_eq_2/u_srll"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_trig/u_tc/i_tseq_neq2/u_tc_equation/i_srlt_ne_1/i_nmu_1_to_4/u_tcl/i_nmu_eq1/u_idout/i_srl_t2/u_srlc16e"
        BEL
        "PLL/chipscope/i_ila_2CH/i_yes_d/u_ila/u_trig/u_tc/i_tseq_neq2/u_tc_equation/i_srlt_ne_1/i_nmu_1_to_4/u_tcl/idout.SLICE_FMC15_BLACKBOX"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_trig/u_tc/i_storage_qual/u_storage_qual/i_srlt_ne_1/i_nmu_1_to_4/u_tcl/i_nmu_eq1/u_idout/i_srl_t2/u_srlc16e"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_stat/u_stat_cnt/g/8/u_fdre"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_stat/u_stat_cnt/g/7/u_fdre"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_stat/u_stat_cnt/g/6/u_fdre"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_stat/u_stat_cnt/g/5/u_fdre"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_stat/u_stat_cnt/g/4/u_fdre"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_stat/u_stat_cnt/g/3/u_fdre"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_stat/u_stat_cnt/g/2/u_fdre"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_stat/u_stat_cnt/g/1/u_fdre"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_stat/u_stat_cnt/g/0/u_fdre"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_stat/u_dsl1/u_tfdre"
        BEL "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_stat/u_dirty" BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_stat/u_reset_edge/u_dout0"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_stat/u_reset_edge/u_dout1"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_stat/u_reset_edge/i_h2l/u_dout"
        BEL "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_stat/u_tdo" BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_0_to_64k/f_sel/0/u_sel"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_0_to_64k/f_sel/1/u_sel"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_0_to_64k/f_sel/2/u_sel"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_0_to_64k/f_sel/3/u_sel"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_0_to_64k/f_sel/4/u_sel"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_0_to_64k/f_sel/5/u_sel"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_0_to_64k/f_sel/6/u_sel"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_0_to_64k/f_sel/7/u_sel"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_0_to_64k/f_sel/8/u_sel"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_0_to_64k/f_sel/9/u_sel"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_0_to_64k/f_sel/10/u_sel"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_0_to_64k/f_sel/11/u_sel"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_0_to_64k/f_sel/12/u_sel"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_0_to_64k/f_sel/13/u_sel"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_0_to_64k/f_sel/14/u_sel"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_0_to_64k/f_sel/15/u_sel"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/i_0_to_64k/i_srl/u_selx"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/u_scnt_cmp/pd_rpm/i_tw_gte8/f_tw/0/i_yes_rpm/i_srlt_eq_2/u_srlh"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/u_scnt_cmp/pd_rpm/i_tw_gte8/f_tw/0/i_yes_rpm/u_muxh/O.SLICE_GMC15_BLACKBOX"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/u_scnt_cmp/pd_rpm/i_tw_gte8/f_tw/0/i_yes_rpm/i_srlt_eq_2/u_srll"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/u_scnt_cmp/pd_rpm/i_tw_gte8/f_tw/0/i_yes_rpm/u_muxh/O.SLICE_FMC15_BLACKBOX"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/u_scnt_cmp/pd_rpm/i_twmod8_ne0/i_yes_rpm/i_srlt_eq_2/u_srlh"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/u_scnt_cmp/pd_rpm/i_twmod8_ne0/i_yes_rpm/i_yes_muxh/u_muxh/O.SLICE_GMC15_BLACKBOX"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/u_scnt_cmp/pd_rpm/i_twmod8_ne0/i_yes_rpm/i_srlt_eq_2/u_srll"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/u_scnt_cmp/pd_rpm/i_twmod8_ne0/i_yes_rpm/i_yes_muxh/u_muxh/O.SLICE_FMC15_BLACKBOX"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/u_wcnt_hcmp/pd_rpm/i_tw_gte8/f_tw/0/i_yes_rpm/i_srlt_eq_2/u_srlh"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/u_wcnt_hcmp/pd_rpm/i_tw_gte8/f_tw/0/i_yes_rpm/u_muxh/O.SLICE_GMC15_BLACKBOX"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/u_wcnt_hcmp/pd_rpm/i_tw_gte8/f_tw/0/i_yes_rpm/i_srlt_eq_2/u_srll"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/u_wcnt_hcmp/pd_rpm/i_tw_gte8/f_tw/0/i_yes_rpm/u_muxh/O.SLICE_FMC15_BLACKBOX"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/u_wcnt_hcmp/pd_rpm/i_twmod8_ne0/i_yes_rpm/i_srlt_eq_2/u_srlh"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/u_wcnt_hcmp/pd_rpm/i_twmod8_ne0/i_yes_rpm/i_yes_muxh/u_muxh/O.SLICE_GMC15_BLACKBOX"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/u_wcnt_hcmp/pd_rpm/i_twmod8_ne0/i_yes_rpm/i_srlt_eq_2/u_srll"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/u_wcnt_hcmp/pd_rpm/i_twmod8_ne0/i_yes_rpm/i_yes_muxh/u_muxh/O.SLICE_FMC15_BLACKBOX"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/u_wcnt_lcmp/pd_rpm/i_tw_gte8/f_tw/0/i_yes_rpm/i_srlt_eq_2/u_srlh"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/u_wcnt_lcmp/pd_rpm/i_tw_gte8/f_tw/0/i_yes_rpm/u_muxh/O.SLICE_GMC15_BLACKBOX"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/u_wcnt_lcmp/pd_rpm/i_tw_gte8/f_tw/0/i_yes_rpm/i_srlt_eq_2/u_srll"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/u_wcnt_lcmp/pd_rpm/i_tw_gte8/f_tw/0/i_yes_rpm/u_muxh/O.SLICE_FMC15_BLACKBOX"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/u_wcnt_lcmp/pd_rpm/i_twmod8_ne0/i_yes_rpm/i_srlt_eq_2/u_srlh"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/u_wcnt_lcmp/pd_rpm/i_twmod8_ne0/i_yes_rpm/i_yes_muxh/u_muxh/O.SLICE_GMC15_BLACKBOX"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/u_wcnt_lcmp/pd_rpm/i_twmod8_ne0/i_yes_rpm/i_srlt_eq_2/u_srll"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/u_wcnt_lcmp/pd_rpm/i_twmod8_ne0/i_yes_rpm/i_yes_muxh/u_muxh/O.SLICE_FMC15_BLACKBOX"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_ns1/pd_rpm/i_srl_t2/i_yes_rpm/i_no_s3/ug3_cfglut4"
        BEL
        "PLL/chipscope/i_ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_ns1/jo_0.SLICE_GMC15_BLACKBOX"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_ns1/pd_rpm/i_srl_t2/i_yes_rpm/i_no_s3/uf3_cfglut4"
        BEL
        "PLL/chipscope/i_ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_ns1/jo_0.SLICE_FMC15_BLACKBOX"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_ns1/pd_rpm/i_srl_t2/i_yes_rpm/i_no_s3/ug2_cfglut4"
        BEL
        "PLL/chipscope/i_ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_ns1/ko_0.SLICE_GMC15_BLACKBOX"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_ns1/pd_rpm/i_srl_t2/i_yes_rpm/i_no_s3/uf2_cfglut4"
        BEL
        "PLL/chipscope/i_ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_ns1/ko_0.SLICE_FMC15_BLACKBOX"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_ns1/pd_rpm/i_srl_t2/i_yes_rpm/i_no_s3/ug1_cfglut4"
        BEL
        "PLL/chipscope/i_ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_ns1/jo_2.SLICE_GMC15_BLACKBOX"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_ns1/pd_rpm/i_srl_t2/i_yes_rpm/i_no_s3/uf1_cfglut4"
        BEL
        "PLL/chipscope/i_ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_ns1/jo_2.SLICE_FMC15_BLACKBOX"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_ns1/pd_rpm/i_srl_t2/i_yes_rpm/i_no_s3/ug0_cfglut4"
        BEL
        "PLL/chipscope/i_ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_ns1/ko_1.SLICE_GMC15_BLACKBOX"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_ns1/pd_rpm/i_srl_t2/i_yes_rpm/i_no_s3/uf0_cfglut4"
        BEL
        "PLL/chipscope/i_ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_ns1/ko_1.SLICE_FMC15_BLACKBOX"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_ns0/pd_rpm/i_srl_t2/i_yes_rpm/i_no_s3/ug3_cfglut4"
        BEL
        "PLL/chipscope/i_ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_ns0/jo_0.SLICE_GMC15_BLACKBOX"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_ns0/pd_rpm/i_srl_t2/i_yes_rpm/i_no_s3/uf3_cfglut4"
        BEL
        "PLL/chipscope/i_ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_ns0/jo_0.SLICE_FMC15_BLACKBOX"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_ns0/pd_rpm/i_srl_t2/i_yes_rpm/i_no_s3/ug2_cfglut4"
        BEL
        "PLL/chipscope/i_ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_ns0/ko_0.SLICE_GMC15_BLACKBOX"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_ns0/pd_rpm/i_srl_t2/i_yes_rpm/i_no_s3/uf2_cfglut4"
        BEL
        "PLL/chipscope/i_ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_ns0/ko_0.SLICE_FMC15_BLACKBOX"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_ns0/pd_rpm/i_srl_t2/i_yes_rpm/i_no_s3/ug1_cfglut4"
        BEL
        "PLL/chipscope/i_ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_ns0/jo_2.SLICE_GMC15_BLACKBOX"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_ns0/pd_rpm/i_srl_t2/i_yes_rpm/i_no_s3/uf1_cfglut4"
        BEL
        "PLL/chipscope/i_ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_ns0/jo_2.SLICE_FMC15_BLACKBOX"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_ns0/pd_rpm/i_srl_t2/i_yes_rpm/i_no_s3/ug0_cfglut4"
        BEL
        "PLL/chipscope/i_ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_ns0/ko_1.SLICE_GMC15_BLACKBOX"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_ns0/pd_rpm/i_srl_t2/i_yes_rpm/i_no_s3/uf0_cfglut4"
        BEL
        "PLL/chipscope/i_ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_ns0/ko_1.SLICE_FMC15_BLACKBOX"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_scrst/pd_rpm/i_srl_t2/i_yes_rpm/ug1_cfglut4"
        BEL
        "PLL/chipscope/i_ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_scrst/jo_0.SLICE_GMC15_BLACKBOX"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_scrst/pd_rpm/i_srl_t2/i_yes_rpm/uf1_cfglut4"
        BEL
        "PLL/chipscope/i_ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_scrst/jo_0.SLICE_FMC15_BLACKBOX"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_scrst/pd_rpm/i_srl_t2/i_yes_rpm/ug0_cfglut4"
        BEL
        "PLL/chipscope/i_ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/scnt_reset.SLICE_GMC15_BLACKBOX"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_scrst/pd_rpm/i_srl_t2/i_yes_rpm/uf0_cfglut4"
        BEL
        "PLL/chipscope/i_ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/scnt_reset.SLICE_FMC15_BLACKBOX"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_wce/i_srl_t2/u_srlc16e"
        BEL
        "PLL/chipscope/i_ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/scnt_ce.SLICE_GMC15_BLACKBOX"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_sce/i_srl_t2/u_srlc16e"
        BEL
        "PLL/chipscope/i_ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/scnt_ce.SLICE_FMC15_BLACKBOX"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_cmpreset/pd_rpm/i_srl_t2/i_yes_rpm/ug1_cfglut4"
        BEL
        "PLL/chipscope/i_ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_cmpreset/jo_0.SLICE_GMC15_BLACKBOX"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_cmpreset/pd_rpm/i_srl_t2/i_yes_rpm/uf1_cfglut4"
        BEL
        "PLL/chipscope/i_ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_cmpreset/jo_0.SLICE_FMC15_BLACKBOX"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_cmpreset/pd_rpm/i_srl_t2/i_yes_rpm/ug0_cfglut4"
        BEL
        "PLL/chipscope/i_ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/cmp_reset.SLICE_GMC15_BLACKBOX"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_cmpreset/pd_rpm/i_srl_t2/i_yes_rpm/uf0_cfglut4"
        BEL
        "PLL/chipscope/i_ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/cmp_reset.SLICE_FMC15_BLACKBOX"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_cdone/pd_rpm/i_srl_t2/i_yes_rpm/ug1_cfglut4"
        BEL
        "PLL/chipscope/i_ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_cdone/jo_0.SLICE_GMC15_BLACKBOX"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_cdone/pd_rpm/i_srl_t2/i_yes_rpm/uf1_cfglut4"
        BEL
        "PLL/chipscope/i_ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_cdone/jo_0.SLICE_FMC15_BLACKBOX"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_cdone/pd_rpm/i_srl_t2/i_yes_rpm/ug0_cfglut4"
        BEL
        "PLL/chipscope/i_ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_cdone/jo_1.SLICE_GMC15_BLACKBOX"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_cdone/pd_rpm/i_srl_t2/i_yes_rpm/uf0_cfglut4"
        BEL
        "PLL/chipscope/i_ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_cdone/jo_1.SLICE_FMC15_BLACKBOX"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_scmpce/pd_rpm/i_srl_t2/i_yes_rpm/ug_cfglut4"
        BEL
        "PLL/chipscope/i_ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/scnt_cmp_ce.SLICE_GMC15_BLACKBOX"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_scmpce/pd_rpm/i_srl_t2/i_yes_rpm/uf_cfglut4"
        BEL
        "PLL/chipscope/i_ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/scnt_cmp_ce.SLICE_FMC15_BLACKBOX"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_wlcmpce/pd_rpm/i_srl_t2/i_yes_rpm/ug_cfglut4"
        BEL
        "PLL/chipscope/i_ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/wcnt_lcmp_ce.SLICE_GMC15_BLACKBOX"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_wlcmpce/pd_rpm/i_srl_t2/i_yes_rpm/uf_cfglut4"
        BEL
        "PLL/chipscope/i_ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/wcnt_lcmp_ce.SLICE_FMC15_BLACKBOX"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_whcmpce/pd_rpm/i_srl_t2/i_yes_rpm/ug_cfglut4"
        BEL
        "PLL/chipscope/i_ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/wcnt_hcmp_ce.SLICE_GMC15_BLACKBOX"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_whcmpce/pd_rpm/i_srl_t2/i_yes_rpm/uf_cfglut4"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/i_rdaddr/i_ni_gt_1/ine1/u_low_count/g/4/u_fdre"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/i_rdaddr/i_ni_gt_1/ine1/u_low_count/g/3/u_fdre"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/i_rdaddr/i_ni_gt_1/ine1/u_low_count/g/2/u_fdre"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/i_rdaddr/i_ni_gt_1/ine1/u_low_count/g/1/u_fdre"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/i_rdaddr/i_ni_gt_1/ine1/u_low_count/g/0/u_fdre"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/i_rdaddr/u_hc/g/13/u_fdre"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/i_rdaddr/u_hc/g/12/u_fdre"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/i_rdaddr/u_hc/g/11/u_fdre"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/i_rdaddr/u_hc/g/10/u_fdre"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/i_rdaddr/u_hc/g/9/u_fdre"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/i_rdaddr/u_hc/g/8/u_fdre"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/i_rdaddr/u_hc/g/7/u_fdre"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/i_rdaddr/u_hc/g/6/u_fdre"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/i_rdaddr/u_hc/g/5/u_fdre"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/i_rdaddr/u_hc/g/4/u_fdre"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/i_rdaddr/u_hc/g/3/u_fdre"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/i_rdaddr/u_hc/g/2/u_fdre"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/i_rdaddr/u_hc/g/1/u_fdre"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/i_rdaddr/u_hc/g/0/u_fdre"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/i_mux/g_ff/4/u_ff"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/i_mux/g_ff/3/u_ff"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/i_mux/g_ff/2/u_ff"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/i_mux/g_ff/1/u_ff"
        BEL
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/i_mux/g_ff/0/u_ff"
        PIN
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/24/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim844.A_pins<53>"
        PIN
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/23/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim848.A_pins<53>"
        PIN
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/22/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim852.A_pins<53>"
        PIN
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/21/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim856.A_pins<53>"
        PIN
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/20/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim860.A_pins<53>"
        PIN
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/19/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim864.A_pins<53>"
        PIN
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/18/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim868.A_pins<53>"
        PIN
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/17/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim872.A_pins<53>"
        PIN
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/16/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim876.A_pins<53>"
        PIN
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/15/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim880.A_pins<53>"
        PIN
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/14/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim884.A_pins<53>"
        PIN
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/13/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim888.A_pins<53>"
        PIN
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/12/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim892.A_pins<53>"
        PIN
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/11/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim896.A_pins<53>"
        PIN
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/10/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim900.A_pins<53>"
        PIN
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/9/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim904.A_pins<53>"
        PIN
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/8/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim908.A_pins<53>"
        PIN
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/7/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim912.A_pins<53>"
        PIN
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/6/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim916.A_pins<53>"
        PIN
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/5/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim920.A_pins<53>"
        PIN
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/4/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim924.A_pins<53>"
        PIN
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/3/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim928.A_pins<53>"
        PIN
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/2/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim932.A_pins<53>"
        PIN
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/1/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim936.A_pins<53>"
        PIN
        "PLL/chipscope/i_ila_2CH/ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/i_rt1/u_ram/g_bram/0/u_bram/ram_rt1_s1_s2_if/ram_rt1_s1_s2_i/newSim940.A_pins<53>";
TIMEGRP U_CLK = BEL "PLL/chipscope/i_icon/icon/u_icon/u_idata_cmd";
TS_J_TO_J = MAXDELAY FROM TIMEGRP "J_CLK" TO TIMEGRP "J_CLK" 30 ns;
TS_U_TO_J = MAXDELAY FROM TIMEGRP "U_CLK" TO TIMEGRP "J_CLK" 15 ns;
TS_U_TO_U = MAXDELAY FROM TIMEGRP "U_CLK" TO TIMEGRP "U_CLK" 15 ns;
PATH TS_U_TO_D_path = FROM TIMEGRP "U_CLK" TO TIMEGRP "D_CLK";
PATH "TS_U_TO_D_path" TIG;
PATH TS_J_TO_D_path = FROM TIMEGRP "J_CLK" TO TIMEGRP "D_CLK";
PATH "TS_J_TO_D_path" TIG;
PATH TS_D_TO_J_path = FROM TIMEGRP "D_CLK" TO TIMEGRP "J_CLK";
PATH "TS_D_TO_J_path" TIG;
TS_adc_clk_ppad_i = PERIOD TIMEGRP "adc_clk_ppad_i" 7 ns HIGH 50%;
PIN PLL/chipscope/i_icon/icon/u_icon/i_yes_bscan/u_bs/i_v2/u_bs_pins<5> = BEL
        "PLL/chipscope/i_icon/icon/u_icon/i_yes_bscan/u_bs/i_v2/u_bs" PINNAME
        SHIFT;
PIN "PLL/chipscope/i_icon/icon/u_icon/i_yes_bscan/u_bs/i_v2/u_bs_pins<5>" TIG;
SCHEMATIC END;