Release 8.1i par I.24 Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved. ABPC11059:: Thu Nov 16 10:14:28 2006 par -w -intstyle ise -ol std -t 1 -gf C:/DESIGNS/FPGA/Custom_Libera/Custom_libera_top_last_par.ncd -gm leverage Custom_libera_top_map.ncd Custom_libera_top.ncd Custom_libera_top.pcf Constraints file: Custom_libera_top.pcf. Loading device for application Rf_Device from file '2vp30.nph' in environment C:\Xilinx. "Custom_libera_top" is an NCD, version 3.1, device xc2vp30, package ff1152, speed -6 Initializing temperature to 85.000 Celsius. (default - Range: -40.000 to 100.000 Celsius) Initializing voltage to 1.400 Volts. (default - Range: 1.400 to 1.600 Volts) WARNING:Timing:3223 - Timing constraint PATH "TS_U_TO_D_path" TIG; ignored during timing analysis. Device speed data version: "PRODUCTION 1.92 2005-11-04". Starting Guide File Processing. Loading database for application par from file: "C:/DESIGNS/FPGA/Custom_Libera/Custom_libera_top_last_par.ncd" "Custom_libera_top" is an NCD, version 3.1, device xc2vp30, package ff1152, speed -6 Finished Guide File Processing. Xilinx Place and Route Guide Results File ========================================= Guide Summary Report: Design Totals: Components: Name matched: 2142 out of 2399 89% Total guided: 2139 out of 2142 99% Signals: Pre-Routed Nets: 67 out of 5759 1% Name matched: 5009 out of 5692 88% Total guided: 5009 out of 5009 100% Total connections guided: 12838 Ungrouped Logic: Guide mode: "leverage" Guide File: "C:/DESIGNS/FPGA/Custom_Libera/Custom_libera_top_last_par.ncd" Components: Name matched: 2142 out of 2399 89% Total guided: 2139 out of 2142 99% Signals: Pre-Routed Nets: 67 out of 5759 1% Name matched: 5009 out of 5692 88% Total guided: 5009 out of 5009 100% Total connections guided: 12838 For a detailed guide report refer to the "Custom_libera_top.grf" file. Device Utilization Summary: Number of BSCANs 1 out of 1 100% Number of BUFGMUXs 3 out of 16 18% Number of External DIFFMs 2 out of 320 1% Number of LOCed DIFFMs 2 out of 2 100% Number of External DIFFSs 2 out of 320 1% Number of LOCed DIFFSs 2 out of 2 100% Number of External IOBs 248 out of 644 38% Number of LOCed IOBs 247 out of 248 99% Number of RAMB16s 94 out of 136 69% Number of SLICEs 2049 out of 13696 14% Overall effort level (-ol): Standard Placer effort level (-pl): High Placer cost table entry (-t): 1 Router effort level (-rl): Standard Starting initial Timing Analysis. REAL time: 3 mins 52 secs Finished initial Timing Analysis. REAL time: 3 mins 52 secs WARNING:Par:276 - The signal ddr2high_ldqs_pad_io_IBUF has no load WARNING:Par:276 - The signal ddr2high_udqsn_pad_io_IBUF has no load WARNING:Par:276 - The signal ddr2high_ldqsn_pad_io_IBUF has no load WARNING:Par:276 - The signal adc_d_dat_pad_i<0>_IBUF has no load WARNING:Par:276 - The signal adc_d_dat_pad_i<1>_IBUF has no load WARNING:Par:276 - The signal adc_d_dat_pad_i<2>_IBUF has no load WARNING:Par:276 - The signal adc_d_dat_pad_i<3>_IBUF has no load WARNING:Par:276 - The signal adc_d_dat_pad_i<4>_IBUF has no load WARNING:Par:276 - The signal adc_d_dat_pad_i<5>_IBUF has no load WARNING:Par:276 - The signal adc_d_dat_pad_i<6>_IBUF has no load WARNING:Par:276 - The signal adc_d_dat_pad_i<7>_IBUF has no load WARNING:Par:276 - The signal adc_d_dat_pad_i<8>_IBUF has no load WARNING:Par:276 - The signal adc_d_dat_pad_i<9>_IBUF has no load WARNING:Par:276 - The signal ddr2low_udqs_pad_io_IBUF has no load WARNING:Par:276 - The signal ddr2high_data_pad_io<0>_IBUF has no load WARNING:Par:276 - The signal ddr2high_data_pad_io<1>_IBUF has no load WARNING:Par:276 - The signal ddr2high_data_pad_io<2>_IBUF has no load WARNING:Par:276 - The signal ddr2high_data_pad_io<3>_IBUF has no load WARNING:Par:276 - The signal ddr2high_data_pad_io<4>_IBUF has no load WARNING:Par:276 - The signal ddr2high_data_pad_io<5>_IBUF has no load WARNING:Par:276 - The signal ddr2high_data_pad_io<6>_IBUF has no load WARNING:Par:276 - The signal ddr2high_data_pad_io<7>_IBUF has no load WARNING:Par:276 - The signal ddr2high_data_pad_io<8>_IBUF has no load WARNING:Par:276 - The signal ddr2high_data_pad_io<9>_IBUF has no load WARNING:Par:276 - The signal ddr2low_ldqs_pad_io_IBUF has no load WARNING:Par:276 - The signal DIO<9>_IBUF has no load WARNING:Par:276 - The signal adc_d_dat_pad_i<10>_IBUF has no load WARNING:Par:276 - The signal adc_d_dat_pad_i<11>_IBUF has no load WARNING:Par:276 - The signal adc_d_dat_pad_i<12>_IBUF has no load WARNING:Par:276 - The signal adc_d_dat_pad_i<13>_IBUF has no load WARNING:Par:276 - The signal ddr2high_data_pad_io<10>_IBUF has no load WARNING:Par:276 - The signal ddr2high_data_pad_io<11>_IBUF has no load WARNING:Par:276 - The signal ddr2high_data_pad_io<12>_IBUF has no load WARNING:Par:276 - The signal ddr2high_data_pad_io<13>_IBUF has no load WARNING:Par:276 - The signal ddr2high_data_pad_io<14>_IBUF has no load WARNING:Par:276 - The signal ddr2high_data_pad_io<15>_IBUF has no load WARNING:Par:276 - The signal ddr2low_udqsn_pad_io_IBUF has no load WARNING:Par:276 - The signal ddr2low_ldqsn_pad_io_IBUF has no load WARNING:Par:276 - The signal DIO<10>_IBUF has no load WARNING:Par:276 - The signal DIO<11>_IBUF has no load WARNING:Par:276 - The signal DIO<12>_IBUF has no load WARNING:Par:276 - The signal DIO<21>_IBUF has no load WARNING:Par:276 - The signal DIO<13>_IBUF has no load WARNING:Par:276 - The signal DIO<22>_IBUF has no load WARNING:Par:276 - The signal DIO<14>_IBUF has no load WARNING:Par:276 - The signal DIO<23>_IBUF has no load WARNING:Par:276 - The signal DIO<15>_IBUF has no load WARNING:Par:276 - The signal DIO<16>_IBUF has no load WARNING:Par:276 - The signal DIO<24>_IBUF has no load WARNING:Par:276 - The signal DIO<18>_IBUF has no load WARNING:Par:276 - The signal ddr2low_data_pad_io<10>_IBUF has no load WARNING:Par:276 - The signal ddr2low_data_pad_io<11>_IBUF has no load WARNING:Par:276 - The signal ddr2low_data_pad_io<12>_IBUF has no load WARNING:Par:276 - The signal ddr2low_data_pad_io<13>_IBUF has no load WARNING:Par:276 - The signal ddr2low_data_pad_io<14>_IBUF has no load WARNING:Par:276 - The signal ddr2low_data_pad_io<15>_IBUF has no load WARNING:Par:276 - The signal ddr2low_data_pad_io<0>_IBUF has no load WARNING:Par:276 - The signal ddr2low_data_pad_io<1>_IBUF has no load WARNING:Par:276 - The signal ddr2low_data_pad_io<2>_IBUF has no load WARNING:Par:276 - The signal ddr2low_data_pad_io<3>_IBUF has no load WARNING:Par:276 - The signal ddr2low_data_pad_io<4>_IBUF has no load WARNING:Par:276 - The signal ddr2low_data_pad_io<5>_IBUF has no load WARNING:Par:276 - The signal ddr2low_data_pad_io<6>_IBUF has no load WARNING:Par:276 - The signal ddr2low_data_pad_io<7>_IBUF has no load WARNING:Par:276 - The signal ddr2low_data_pad_io<8>_IBUF has no load WARNING:Par:276 - The signal ddr2low_data_pad_io<9>_IBUF has no load WARNING:Par:276 - The signal ddr2high_udqs_pad_io_IBUF has no load Starting Placer WARNING:Place:490 - A clock IOB / clock component pair have been found that are not placed at an optimal clock IOB / clock site pair. The clock component is placed at site BUFGMUX7S. The clock IO site that is paired with this clock buffer using I0 inputsite is AL18. The IO component sbc_csn_pad_i is placed at site AL30. This will not allow the use of the fast path between the IO and the Clock buffer. You may want to analyze why this problem exists and correct it. This is not an error so processing will continue. WARNING:Place:490 - A clock IOB / clock component pair have been found that are not placed at an optimal clock IOB / clock site pair. The clock component is placed at site BUFGMUX6S. The clock IO site that is paired with this clock buffer using I0 inputsite is D18. The IO component adc_clk_ppad_i is placed at site M32. This will not allow the use of the fast path between the IO and the Clock buffer. You may want to analyze why this problem exists and correct it. This is not an error so processing will continue. Writing design to file Custom_libera_top.ncd Total REAL time to Placer completion: 4 mins 28 secs Total CPU time to Placer completion: 4 mins 27 secs INFO:Par:259 - Unrouted the following 17 nets to resolve overlaps: Net: PLL/chipscope/i_vio_control/i_vio/output_shift_11 Net: sbc_adr_pad_i_5_IBUF Net: sbc_adr_pad_i_3_IBUF Net: sbc_adr_pad_i_3_IBUF Net: PLL/HC_tab_addr_cnt<0> Net: sbc_adr_pad_i_5_IBUF Net: N47 Net: N47 Net: data_out<26>_map119 Net: regC<14> Net: PLL/n5<20> Net: PLL/chipscope/analyser_control<24> Net: PLL/mult_out<6> Net: PLL/chipscope/i_ila_2CH/i_yes_d/u_ila/u_capstor/i_case1/rd_addr_16 Net: PLL/chipscope/trig_timer__n0000<13> Net: PLL/chipscope/i_vio_control/i_vio/output_shift_14 Net: PLL/chipscope/i_vio/i_vio/output_shift_48 Starting Router Phase 1: 7291 unrouted; REAL time: 4 mins 41 secs Phase 2: 5971 unrouted; REAL time: 4 mins 54 secs Phase 3: 1717 unrouted; REAL time: 4 mins 58 secs Phase 4: 1717 unrouted; (14123) REAL time: 4 mins 58 secs Phase 5: 1831 unrouted; (1668) REAL time: 5 mins 3 secs Phase 6: 1837 unrouted; (736) REAL time: 5 mins 4 secs Phase 7: 0 unrouted; (834) REAL time: 5 mins 13 secs Phase 8: 0 unrouted; (834) REAL time: 5 mins 17 secs Phase 9: 0 unrouted; (184) REAL time: 5 mins 44 secs Phase 10: 0 unrouted; (135) REAL time: 6 mins 6 secs Phase 11: 0 unrouted; (135) REAL time: 11 mins 40 secs Phase 12: 0 unrouted; (135) REAL time: 11 mins 47 secs Phase 13: 0 unrouted; (135) REAL time: 11 mins 48 secs WARNING:Route:447 - CLK Net:sbc_csn_pad_i_BUFGP may have excessive skew because 1 NON-CLK pins failed to route using a CLK template. WARNING:Route:447 - CLK Net:PLL/dds_freq<31> may have excessive skew because 6 NON-CLK pins failed to route using a CLK template. WARNING:Route:447 - CLK Net:PLL/dds_freq<28> may have excessive skew because 6 NON-CLK pins failed to route using a CLK template. WARNING:Route:447 - CLK Net:PLL/dds_freq<27> may have excessive skew because 6 NON-CLK pins failed to route using a CLK template. WARNING:Route:447 - CLK Net:PLL/dds_freq<26> may have excessive skew because 6 NON-CLK pins failed to route using a CLK template. WARNING:Route:447 - CLK Net:PLL/dds_freq<22> may have excessive skew because 7 NON-CLK pins failed to route using a CLK template. WARNING:Route:447 - CLK Net:PLL/dds_freq<15> may have excessive skew because 7 NON-CLK pins failed to route using a CLK template. WARNING:Route:447 - CLK Net:PLL/dds_freq<29> may have excessive skew because 6 NON-CLK pins failed to route using a CLK template. WARNING:Route:447 - CLK Net:PLL/dds_freq<25> may have excessive skew because 6 NON-CLK pins failed to route using a CLK template. WARNING:Route:447 - CLK Net:PLL/dds_freq<17> may have excessive skew because 7 NON-CLK pins failed to route using a CLK template. WARNING:Route:447 - CLK Net:PLL/dds_freq<23> may have excessive skew because 7 NON-CLK pins failed to route using a CLK template. WARNING:Route:447 - CLK Net:PLL/dds_freq<14> may have excessive skew because 7 NON-CLK pins failed to route using a CLK template. WARNING:Route:447 - CLK Net:PLL/dds_freq<10> may have excessive skew because 7 NON-CLK pins failed to route using a CLK template. WARNING:Route:447 - CLK Net:PLL/dds_freq<7> may have excessive skew because 7 NON-CLK pins failed to route using a CLK template. WARNING:Route:447 - CLK Net:PLL/dds_freq<8> may have excessive skew because 7 NON-CLK pins failed to route using a CLK template. WARNING:Route:447 - CLK Net:PLL/dds_freq<3> may have excessive skew because 7 NON-CLK pins failed to route using a CLK template. WARNING:Route:447 - CLK Net:PLL/dds_freq<4> may have excessive skew because 7 NON-CLK pins failed to route using a CLK template. WARNING:Route:447 - CLK Net:PLL/dds_freq<5> may have excessive skew because 7 NON-CLK pins failed to route using a CLK template. WARNING:Route:447 - CLK Net:PLL/dds_freq<21> may have excessive skew because 7 NON-CLK pins failed to route using a CLK template. WARNING:Route:447 - CLK Net:PLL/dds_freq<24> may have excessive skew because 6 NON-CLK pins failed to route using a CLK template. WARNING:Route:447 - CLK Net:PLL/dds_freq<11> may have excessive skew because 7 NON-CLK pins failed to route using a CLK template. WARNING:Route:447 - CLK Net:PLL/dds_freq<2> may have excessive skew because 7 NON-CLK pins failed to route using a CLK template. WARNING:Route:447 - CLK Net:PLL/dds_freq<12> may have excessive skew because 7 NON-CLK pins failed to route using a CLK template. WARNING:Route:447 - CLK Net:PLL/dds_freq<9> may have excessive skew because 7 NON-CLK pins failed to route using a CLK template. WARNING:Route:447 - CLK Net:PLL/chipscope/clk2 may have excessive skew because 23 CLK pins and 3 NON_CLK pins failed to route using a CLK template. WARNING:Route:447 - CLK Net:PLL/dds_freq<6> may have excessive skew because 7 NON-CLK pins failed to route using a CLK template. WARNING:Route:447 - CLK Net:PLL/dds_freq<30> may have excessive skew because 6 NON-CLK pins failed to route using a CLK template. WARNING:Route:447 - CLK Net:PLL/dds_freq<18> may have excessive skew because 7 NON-CLK pins failed to route using a CLK template. WARNING:Route:447 - CLK Net:PLL/dds_freq<1> may have excessive skew because 7 NON-CLK pins failed to route using a CLK template. WARNING:Route:447 - CLK Net:PLL/dds_freq<20> may have excessive skew because 7 NON-CLK pins failed to route using a CLK template. WARNING:Route:447 - CLK Net:PLL/dds_freq<0> may have excessive skew because 7 NON-CLK pins failed to route using a CLK template. WARNING:Route:447 - CLK Net:PLL/dds_freq<16> may have excessive skew because 7 NON-CLK pins failed to route using a CLK template. WARNING:Route:447 - CLK Net:PLL/dds_freq<19> may have excessive skew because 7 NON-CLK pins failed to route using a CLK template. WARNING:Route:447 - CLK Net:PLL/dds_freq<13> may have excessive skew because 7 NON-CLK pins failed to route using a CLK template. Total REAL time to Router completion: 11 mins 48 secs Total CPU time to Router completion: 11 mins 47 secs Generating "PAR" statistics. ************************** Generating Clock Report ************************** +---------------------+--------------+------+------+------------+-------------+ | Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)| +---------------------+--------------+------+------+------------+-------------+ | DIO_2_OBUF | BUFGMUX6S| No | 782 | 0.331 | 1.435 | +---------------------+--------------+------+------+------------+-------------+ | sbc_csn_pad_i_BUFGP | BUFGMUX7S| No | 210 | 0.272 | 1.435 | +---------------------+--------------+------+------+------------+-------------+ |PLL/chipscope/contro | | | | | | | l0<0> | BUFGMUX0P| No | 425 | 0.307 | 1.434 | +---------------------+--------------+------+------+------------+-------------+ | PLL/dds_freq<0> | Local| | 9 | 0.029 | 2.817 | +---------------------+--------------+------+------+------------+-------------+ | PLL/dds_freq<1> | Local| | 9 | 0.000 | 2.337 | +---------------------+--------------+------+------+------------+-------------+ | PLL/dds_freq<2> | Local| | 9 | 0.025 | 2.190 | +---------------------+--------------+------+------+------------+-------------+ | PLL/dds_freq<3> | Local| | 9 | 0.000 | 2.530 | +---------------------+--------------+------+------+------------+-------------+ | PLL/dds_freq<4> | Local| | 9 | 0.013 | 2.938 | +---------------------+--------------+------+------+------------+-------------+ | PLL/dds_freq<5> | Local| | 9 | 0.011 | 2.846 | +---------------------+--------------+------+------+------------+-------------+ | PLL/dds_freq<6> | Local| | 9 | 0.007 | 2.548 | +---------------------+--------------+------+------+------------+-------------+ | PLL/dds_freq<7> | Local| | 9 | 0.024 | 2.190 | +---------------------+--------------+------+------+------------+-------------+ | PLL/dds_freq<8> | Local| | 9 | 0.006 | 2.556 | +---------------------+--------------+------+------+------------+-------------+ | PLL/dds_freq<9> | Local| | 9 | 0.007 | 2.776 | +---------------------+--------------+------+------+------------+-------------+ | PLL/dds_freq<10> | Local| | 9 | 0.011 | 2.976 | +---------------------+--------------+------+------+------------+-------------+ | PLL/dds_freq<11> | Local| | 9 | 0.023 | 2.706 | +---------------------+--------------+------+------+------------+-------------+ | PLL/dds_freq<12> | Local| | 9 | 0.012 | 2.631 | +---------------------+--------------+------+------+------------+-------------+ | PLL/dds_freq<13> | Local| | 9 | 0.002 | 2.738 | +---------------------+--------------+------+------+------------+-------------+ | PLL/dds_freq<14> | Local| | 9 | 0.042 | 2.599 | +---------------------+--------------+------+------+------------+-------------+ | PLL/dds_freq<15> | Local| | 9 | 0.215 | 2.736 | +---------------------+--------------+------+------+------------+-------------+ | PLL/dds_freq<16> | Local| | 9 | 0.000 | 2.573 | +---------------------+--------------+------+------+------------+-------------+ | PLL/dds_freq<17> | Local| | 9 | 0.000 | 2.586 | +---------------------+--------------+------+------+------------+-------------+ | PLL/dds_freq<18> | Local| | 9 | 0.006 | 2.356 | +---------------------+--------------+------+------+------------+-------------+ | PLL/dds_freq<19> | Local| | 9 | 0.000 | 2.735 | +---------------------+--------------+------+------+------------+-------------+ | PLL/dds_freq<20> | Local| | 9 | 0.019 | 3.146 | +---------------------+--------------+------+------+------------+-------------+ | PLL/dds_freq<21> | Local| | 9 | 0.007 | 3.201 | +---------------------+--------------+------+------+------------+-------------+ | PLL/dds_freq<22> | Local| | 9 | 0.021 | 2.876 | +---------------------+--------------+------+------+------------+-------------+ | PLL/dds_freq<23> | Local| | 9 | 0.013 | 2.746 | +---------------------+--------------+------+------+------------+-------------+ | PLL/dds_freq<24> | Local| | 8 | 0.036 | 3.212 | +---------------------+--------------+------+------+------------+-------------+ | PLL/dds_freq<25> | Local| | 8 | 0.027 | 2.954 | +---------------------+--------------+------+------+------------+-------------+ | PLL/dds_freq<26> | Local| | 8 | 0.004 | 2.972 | +---------------------+--------------+------+------+------------+-------------+ | PLL/dds_freq<27> | Local| | 8 | 0.000 | 2.981 | +---------------------+--------------+------+------+------------+-------------+ | PLL/dds_freq<28> | Local| | 8 | 0.036 | 2.964 | +---------------------+--------------+------+------+------------+-------------+ | PLL/dds_freq<29> | Local| | 8 | 0.028 | 2.767 | +---------------------+--------------+------+------+------------+-------------+ | PLL/dds_freq<30> | Local| | 8 | 0.330 | 3.080 | +---------------------+--------------+------+------+------------+-------------+ | PLL/dds_freq<31> | Local| | 8 | 0.125 | 2.987 | +---------------------+--------------+------+------+------------+-------------+ |PLL/chipscope/i_icon | | | | | | | /iupdate_out | Local| | 1 | 0.000 | 1.924 | +---------------------+--------------+------+------+------------+-------------+ | PLL/chipscope/clk2 | Local| | 165 | 2.220 | 4.653 | +---------------------+--------------+------+------+------------+-------------+ * Net Skew is the difference between the minimum and maximum routing only delays for the net. Note this is different from Clock Skew which is reported in TRCE timing report. Clock Skew is the difference between the minimum and maximum path delays which includes logic delays. The Delay Summary Report The NUMBER OF SIGNALS NOT COMPLETELY ROUTED for this design is: 0 The AVERAGE CONNECTION DELAY for this design is: 1.438 The MAXIMUM PIN DELAY IS: 8.362 The AVERAGE CONNECTION DELAY on the 10 WORST NETS is: 6.708 Listing Pin Delays by value: (nsec) d < 2.00 < d < 4.00 < d < 6.00 < d < 8.00 < d < 9.00 d >= 9.00 --------- --------- --------- --------- --------- --------- 11662 3903 544 32 2 0 Timing Score: 135 INFO:Par:62 - Your design did not meet timing. The following are some suggestions to assist you to meet timing in your design. Review the timing report using Timing Analyzer (In ISE select "Post-Place & Route Static Timing Report"). Go to the failing constraint(s) and select the "Timing Improvement Wizard" link for suggestions to correct each problem. Increase the PAR Effort Level setting to "high" Rerun Map with "-timing" (ISE process "Perform Timing -Driven Packing and Placement" Run Multi-Pass Place and Route in PAR using at least 5 "PAR Iterations" (ISE process "Multi Pass Place & Route"). Use the Xilinx "xplorer" script to try special combinations of options known to produce very good results. See http://www.xilinx.com/xplorer for details. Visit the Xilinx technical support web at http://support.xilinx.com and go to either "Troubleshoot->Tech Tips->Timing & Constraints" or " TechXclusives->Timing Closure" for tips and suggestions for meeting timing in your design. Number of Timing Constraints that were not applied: 1 Asterisk (*) preceding a constraint indicates it was not met. This may be due to a setup or hold violation. ------------------------------------------------------------------------------------------------------ Constraint | Requested | Actual | Logic | Absolute |Number of | | | Levels | Slack |errors ------------------------------------------------------------------------------------------------------ * TS_adc_clk_ppad_i = PERIOD TIMEGRP "adc_c | 7.000ns | 7.135ns | 18 | -0.135ns | 1 lk_ppad_i" 7 ns HIGH 50% | | | | | ------------------------------------------------------------------------------------------------------ TS_U_TO_J = MAXDELAY FROM TIMEGRP "U_CLK" | 15.000ns | 3.455ns | 1 | 11.545ns | 0 TO TIMEGRP "J_CLK" 15 ns | | | | | ------------------------------------------------------------------------------------------------------ TS_U_TO_U = MAXDELAY FROM TIMEGRP "U_CLK" | 15.000ns | 1.496ns | 0 | 13.504ns | 0 TO TIMEGRP "U_CLK" 15 ns | | | | | ------------------------------------------------------------------------------------------------------ TS_J_TO_J = MAXDELAY FROM TIMEGRP "J_CLK" | 30.000ns | 10.510ns | 2 | 19.490ns | 0 TO TIMEGRP "J_CLK" 30 ns | | | | | ------------------------------------------------------------------------------------------------------ PATH "TS_U_TO_D_path" TIG | N/A | N/A | N/A | N/A | N/A ------------------------------------------------------------------------------------------------------ PATH "TS_J_TO_D_path" TIG | N/A | 7.708ns | 1 | N/A | N/A ------------------------------------------------------------------------------------------------------ PATH "TS_D_TO_J_path" TIG | N/A | 4.820ns | 5 | N/A | N/A ------------------------------------------------------------------------------------------------------ 1 constraint not met. INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the constraint does not cover any paths or that it has no requested value. Generating Pad Report. All signals are completely routed. WARNING:Par:284 - There are 67 sourceless or loadless signals in this design. Total REAL time to PAR completion: 11 mins 53 secs Total CPU time to PAR completion: 11 mins 51 secs Peak Memory Usage: 297 MB Placement: Completed - No errors found. Routing: Completed - No errors found. Timing: Completed - 1 errors found. Number of error messages: 0 Number of warning messages: 105 Number of info messages: 2 Writing design to file Custom_libera_top.ncd PAR done!