page1
16 Digital
I/O lines
FPGA Data Processing
Engine
Virtex-4 based
Module controller
1 per processing
module
Boots from System
Controller
PCI Bus
Timing Bus
System Controller
2 units (1 spare)
Intelr Pentium based
with RAID disk storage
Ethernet Gigabit Switch
Digital Timing and
Test Inputs/Outputs
Analogue Inputs
Clock input
LAN
Processing Module
9 x ADC
front end
(9 Analogue
and 1 clock
inputs)
PU Processing Engine: 5 per module