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/*******************************************************************************
 *	Pupe.h		Pupe management class
 *			T.Barnaby,	BEAM Ltd,	2007-02-13
 *******************************************************************************
 */
#ifndef Pupe_H
#define Pupe_H	1

#include <TmsLib.h>
#include <TmsD.h>
#include <BThread.h>
#include <BMutex.h>
#include <PllSynth.h>
#include <admxrc2.h>

using namespace Tms;

class Control;

const int	FpgaCycleInfoTableSize		= 512;
const int	FpgaCycleTimingTableSize	= 4096;
const int	FpgaCycleTimingTableMask	= (4096-1);
const int	FpgaBunchMeanTableSize		= 4096;

class Pupe;

/// PupeInterrupt thread class
class PupeInterruptThread : public BThread {
public:
			PupeInterruptThread(Pupe& pupe);
	void*		function();
private:
	Pupe&	opupe;
};

class Pupe {
public:
	enum			{ numChan = 3 };

				Pupe(Control& control, int board);
				~Pupe();

				// Per board functions			
	BError			init();
	BError			setMaster(int on);				///< Sets this board as a master for the timing bus
	BError			status();		///< Returns the boards status

	BError			setNextCycle(UInt32 cycleNumber, BString cycleType);

				// Per Pick-Up functions
	BError			setControlInfo(PuChannel puChannel, CycleParam params);
	BError			getStatusList(PuChannel puChannel, BList<NameValue>& statusList);
	BError			getStatus(PuChannel puChannel, PuStatus& puStatus);
	BError			getData(PuChannel puChannel, DataInfo dataInfo, Data& data);

	BError			setTestMode(PuChannel puChannel, UInt32 testOutput, UInt32 timingDisableMask);
	BError			setTimingSignals(PuChannel puChannel, UInt32 timingSignals);
	BError			captureTestData(PuChannel puChannel, TestCaptureInfo captureInfo, BArray<UInt64>& data);
	BError			setTestData(PuChannel puChannel, Int32 on, BArray<UInt32> data);	///< This function will set a PU channel to sample data from memory rather than the ADC's
	BError			setPupeConfig(PuChannel puPhysChannel, PupeConfig pupeConfig);
	BError			getPupeConfig(PuChannel puPhysChannel, PupeConfig& pupeConfig);


				// Internal functions
	void			cycleStart();		///< Start of cycle event
	void			cycleStop();		///< End of cycle event
	void			cycleError(int puChan);	///< An error occured

	BError			fpgaInterruptLoop();
	void			fpgaTriggerTimingInputs(TimingSig input);	///< Trigger a timing inputs
	
	int			getBoard();
	void			dumpState();
private:
	void			setNumBunches(PuChannel puChannel, CycleParam params);
	BError			setControlInfoPickUp(PuChannel puChannel, CycleParam params);
	BError			getSimData(DataInfo dataInfo, Data& data);	///< return simulated data
	BError			checkData(UInt32 cycleNumber);
	

	BError			fpgaInit();
	BError			fpgaLoad();
	BError			fpgaConfig();
	void			fpgaClose();
	BError			fpgaGetInfo(BList<NameValue>& infoList);
	BError			fpgaReadData32(uint32_t fpgaOffset, void* toAddress, int nbytes);
	BError			fpgaReadData64(uint32_t fpgaOffset, void* toAddress, int nbytes);
	BError			fpgaWriteData64(void* fromAddress, uint32_t fpgaOffset, int nbytes);
	
	BError			fpgaDmaData(void* toAddress, uint32_t fromAddress, int nbytes);
	BError			fpgaCopyData(int pupeChan, uint32_t address, uint32_t nsamples, Data& data);

	Control&		ocontrol;
	BMutex			olock;			///< Locks access to the FPGA
	BMutex			odiagLock;		///< Diagnostics capture lock
	int			oboard;
	int			omaster;
	int			osimulate;
	PupeConfig		opupeConfig;
	int			oinitialised;		///< The board has been initialised
	BError			ostatus;		///< The boards current status
	UInt32			ocycleNumber;		///< The current PS cycle number
	UInt32			ocycleCompletedNumber;	///< The last completed PS cycle number
	UInt32			ocycleNumberNext;	///< The next PS cycle number
	UInt32			opuCycleNumbers[3];	///< The board cycle numbers matching the PS cycle number
	
	ADMXRC2_HANDLE		ofpgaCard;
	ADMXRC2_CARD_INFO	ocardInfo;
	ADMXRC2_DMADESC		odmabuf;
	int			opageSize;
	int			odmaBufferSize;		///< The DMA buffer size
	UInt64*			odmaBuffer;		///< DMA buffer
	volatile uint32_t*	ofpga;
	volatile uint32_t*	ofpgaControl;
	PupeInterruptThread	ointerruptThread;
	CycleParam		ocycleParam[3];		///< Parameters for the current cycle
	BArray<int>		onumBunches[3];		///< The number of bunches per phase
	
	PllSynth		opllSynth;		///< The Phase locked loop frequency synthesisor
	
	uint32_t		ocycleInfoTable[FpgaCycleInfoTableSize];
	uint64_t		ocycleTimingTable[FpgaCycleTimingTableSize];

	uint32_t		ocycleCount;
};

#endif