1. The phase_table_msb (MSB of the Pll Phase Table Address) appears to be inverted and thus out of phase with respect to pll_msb. ie its +ve edge appears to be in the center of an orbit not at the start/end. 2. With the diagnostics, the ability to map the timing signals to the upper 8 bits is a bit difficult to use. It would be good if they could map over the LSBits of a value. Knowing a bit more on what we need from the diagnostics can I suggest a better structure ? We could change the timing signals to appear in the lower 8 bits rather than the top 8 bits and have the following structure: diagnostics(63 downto 56) <= frev_in & pll_msb & phase_table_msb & LO_pulse1 & sigma(13 downto 11) & LO_pulse2; diagnostics(55 downto 48) <= "0" & sel_filter & rf_select2 & rf_select1 & phase_table_data(7 downto 6) & GATE_pulse & BLR_pulse diagnostics(47 downto 32) <= switch_state & sigma(13 downto 2); diagnostics(31 downto 0) <= dds_freq; diagnostics(127 downto 120) <= frev_in & pll_msb & phase_table_msb & LO_pulse1 & sigma(13 downto 11) & LO_pulse2; diagnostics(115 downto 102) <= mult_out1; diagnostics(101 downto 88) <= mult_out2; diagnostics(87 downto 64) <= f_error(23 downto 0); diagnostics(191 downto 184) <= frev_in & pll_msb & phase_table_msb & LO_pulse1 & sigma(13 downto 11) & LO_pulse2; diagnostics(183) <= GATE_pulse; diagnostics(182 downto 160) <= b0(22 downto 0); diagnostics(159 downto 128) <= SXT(result0_tmp,32); diagnostics(255) <= BLR_pulse; diagnostics(254) <= GATE_pulse; diagnostics(253 downto 240) <= sigma; diagnostics(239 downto 224) <= y0(15 downto 0); diagnostics(223 downto 208) <= e0(15 downto 0); diagnostics(207 downto 192) <= x0(15 downto 0);