Hi Andrew,

I have managed to get the PLL to lock to Sigma.
I had a look at Gregs FPGA code, which I presume is similar to the
current FPGA code, and noticed that the implementation
of the filter leaves a scaling factor of about 128 on the data. Increasing
the loop_gain to about 9 made the loop gain about right for the signals
involved.

I also noticed that the phase relationships of FREF to Simga are a bit
twisted. I have changed the phase tables to match this, but I believe
it would be better if the some changes were made to the PLL so that the
phase delays of the FREF and Sigma match and also match the Matlab simulation.
To do this the following changes are needed:

1. Change the PLL feedback to be +ve; 
	dds_freq<=dds_freq + f_error_dds;

2. Swap the sign of FREF after frev_gain is applied.
	Frev_num <= -frev_gain when F_rev_in = '0' else (frev_gain);

I also note there is a discrepancy between the FPGA filter and the
CERN Matlab simualtion's implementation. I'm not sure which one is
correct or best ....

Notes:
N1. We may need to have a gain control on the Sigma input as the PLL
	lock appears quite dependent on the PLL gain and I suspect
	that the level of Sigma varies by quite a lot. Maybe simply
	converting Sigma to a square wave would be simpler ?

N2. On recieving a CYCLE_START interrupt, I note that the TIME
	register has not been reset to 0. I would have thought that
	would have been done on CYCLE_START going high ?

N3. Im not sure when entries are added to the CycleTimingTable. I assumed they would be entered every
	ms after CycleStart, but this does not seem to be the case. Are they added only after injection
	or only when data is actually captured ?