-- Vhdl test bench created from schematic pll2.sch - Tue Feb 07 16:01:55 2006 -- -- Notes: -- 1) This testbench template has been automatically generated using types -- std_logic and std_logic_vector for the ports of the unit under test. -- Xilinx recommends that these types always be used for the top-level -- I/O of a design in order to guarantee that the testbench will bind -- correctly to the timing (post-route) simulation model. -- 2) To use this template as your testbench, change the filename to any -- name of your choice with the extension .vhd, and use the "Source->Add" -- menu in Project Navigator to import the testbench. Then -- edit the user defined section below, adding code to generate the -- stimulus for your design. -- LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; USE std.textio.all; use ieee.std_logic_unsigned.all; LIBRARY UNISIM; USE UNISIM.Vcomponents.ALL; ENTITY pll2_pll2_sch_tb IS END pll2_pll2_sch_tb; ARCHITECTURE behavioral OF pll2_pll2_sch_tb IS COMPONENT pll3 port ( loop_gain : in std_logic_vector (3 downto 0); loop_ctrl : in std_logic; clk : in std_logic; adc_a_i : in std_logic_vector (13 downto 0); adc_b_i : in std_logic_vector (13 downto 0); adc_c_i : in std_logic_vector (13 downto 0); freq_init : in std_logic_vector (31 downto 0); ph_init : in std_logic_vector (8 downto 0); init : in std_logic; phase_addr_in : in std_logic_vector (8 downto 0); phase_data_in : in std_logic_vector (3 downto 0); write_enable : in std_logic; trigger : in std_logic; result_valid : out std_logic; result_0 : out std_logic_vector (31 downto 0); result_1 : out std_logic_vector (31 downto 0); result_2 : out std_logic_vector (31 downto 0)); end component; SIGNAL phase_addr_in : STD_LOGIC_VECTOR (8 DOWNTO 0); SIGNAL phase_data_in : STD_LOGIC_VECTOR (3 DOWNTO 0); SIGNAL write_enable : STD_LOGIC; SIGNAL clk,sel,fref : STD_LOGIC; SIGNAL init : STD_LOGIC; SIGNAL data_in,data_in_div : STD_LOGIC_VECTOR (31 DOWNTO 0); SIGNAL f1_init : STD_LOGIC_VECTOR (31 DOWNTO 0); SIGNAL ram_out : STD_LOGIC_VECTOR (3 DOWNTO 0); SIGNAL result,f_error,b1_out,f1_out,p1_out : STD_LOGIC_VECTOR (31 DOWNTO 0); signal ph_init : std_logic_vector (8 downto 0); BEGIN UUT: pll3 PORT MAP( loop_gain => "0000" , clk => clk, adc_a_i => data_in(13 downto 0), adc_b_i => (others =>'0') , adc_c_i => (others =>'0') , freq_init => f1_init, init => init, phase_addr_in => phase_addr_in, phase_data_in => phase_data_in, ph_init =>ph_init, write_enable => write_enable, loop_ctrl =>'0', result_valid =>open, result_0 =>result, result_1 =>open, result_2 =>open, trigger => '0' ); -- *** Test Bench - User Defined Section *** -- f1_init<=x"011c16fd" ; f1_init<= std_logic_vector(to_signed(2300457,32)); -- ph_init<="000000000"; ph_init<= std_logic_vector(to_signed(-232,9)); selection: process begin loop sel <= '1'; WAIT FOR 10000000 ns; sel <= '1'; WAIT FOR 10000000 ns; end loop; end process; reference_frequency: Process begin LOOP Fref <= '1'; wait for 992 ns ; Fref <= '0'; wait for 992 ns; END LOOP; end process; tb : PROCESS FILE pt_infile: text open read_mode IS "ptab.txt"; FILE data_infile: text open read_mode IS "EASTB65k.txt"; -- FILE data_infile: text open read_mode IS "EASTBinj.txt"; -- FILE data_infile: text open read_mode IS "1_AD_0.TXT"; FILE outfile: text open write_mode IS "pllout.txt"; VARIABLE pt_line,data_line: line; VARIABLE outline: line; VARIABLE mar: integer; VARIABLE pt_in,pll_in,pll_out,int_gate,blr_gate: integer; VARIABLE pll_out_signed: signed(31 downto 0); BEGIN mar := 0; clk <= '0'; init <= '1'; phase_addr_in <= "000000000"; data_in <= x"00000000"; wait for 4 ns; clk <= '1'; wait for 4 ns; write_enable <= '1'; -- *** read in the phase table WHILE NOT endfile(pt_infile) LOOP readline(pt_infile,pt_line); read (pt_line,pt_in); phase_data_in <= std_logic_vector(to_signed(pt_in,4)); clk <= '0'; wait for 4 ns; clk <= '1'; mar := mar + 1; phase_addr_in <= std_logic_vector(to_unsigned(mar,9)); wait for 4 ns; END LOOP; -- *** read in the pu data write_enable <= '0'; init <= '0'; -- write (outline,"in data out data int gate bl gate"); WHILE NOT endfile(data_infile) LOOP readline(data_infile,data_line); -- readline(data_infile,data_line); read (data_line,pll_in); -- data_in <= std_logic_vector(to_signed(pll_in,32)); data_in <= std_logic_vector(to_signed(pll_in,32)); -- data_in <= data_in_div(31)& data_in_div(31)& data_in_div(31)& data_in_div(31)& data_in_div(31)& data_in_div(31)& data_in_div(31 downto 6 ); clk <= '0'; wait for 4 ns; clk <= '1'; pll_out_signed := signed(result(31 downto 0)); pll_out := to_integer(pll_out_signed); write(outline,pll_in); write(outline,string'(" ")); write(outline,pll_out); writeline(outfile,outline); wait for 4 ns; END LOOP; -- ** print it out again in order to see if the memory works fine -- pll_clk <= '0'; -- wait for 5 ns; -- pll_clk <= '1'; -- pll_reset <= '0'; -- pll_we <= '0'; -- for i in 0 to 512 loop-- wait for 5 ns; -- pll_clk <= '0'; -- wait for 5 ns; -- pll_clk <= '1'; -- end loop; -- wait; -- will wait forever END PROCESS; --sim_end: process --begin -- WAIT FOR 40 us; -- ASSERT (FALSE) REPORT -- "Simulation finished." -- SEVERITY FAILURE; -- end process; -- *** End Test Bench - User Defined Section *** END;