The following files were generated for 'spram8192x32' in directory C:\DESIGNS\FPGA\Custom_Libera: spram8192x32.asy: Graphical symbol information file. Used by the ISE tools and some third party tools to create a symbol representing the core. spram8192x32.edn: Electronic Data Netlist (EDN) file containing the information required to implement the module in a Xilinx (R) FPGA. spram8192x32.sym: Please see the core data sheet. spram8192x32.v: Verilog wrapper file provided to support functional simulation. This file contains simulation model customization data that is passed to a parameterized simulation model for the core. spram8192x32.veo: VEO template file containing code that can be used as a model for instantiating a CORE Generator module in a Verilog design. spram8192x32.vhd: VHDL wrapper file provided to support functional simulation. This file contains simulation model customization data that is passed to a parameterized simulation model for the core. spram8192x32.vho: VHO template file containing code that can be used as a model for instantiating a CORE Generator module in a VHDL design. spram8192x32.xco: CORE Generator input file containing the parameters used to regenerate a core. spram8192x32_flist.txt: Text file listing all of the output files produced when a customized core was generated in the CORE Generator. spram8192x32_readme.txt: Text file indicating the files generated and how they are used. Please see the Xilinx CORE Generator online help for further details on generated files and how to use them.