-------------------------------------------------------------------------------- Release 8.1i Trace I.24 Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved. C:\Xilinx\bin\nt\trce.exe -ise Custom_Libera.ise -intstyle ise -e 3 -l 3 -s 6 -xml Custom_libera_top Custom_libera_top.ncd -o Custom_libera_top.twr Custom_libera_top.pcf Design file: custom_libera_top.ncd Physical constraint file: custom_libera_top.pcf Device,speed: xc2vp30,-6 (PRODUCTION 1.92 2005-11-04) Report level: error report Environment Variable Effect -------------------- ------ NONE No environment variables were set -------------------------------------------------------------------------------- WARNING:Timing:3223 - Timing constraint PATH "TS_U_TO_D_path" TIG; ignored during timing analysis. INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report. ================================================================================ Timing constraint: TS_J_TO_J = MAXDELAY FROM TIMEGRP "J_CLK" TO TIMEGRP "J_CLK" 30 ns; 10299 items analyzed, 0 timing errors detected. (0 setup errors, 0 hold errors) Maximum delay is 10.510ns. -------------------------------------------------------------------------------- ================================================================================ Timing constraint: TS_U_TO_J = MAXDELAY FROM TIMEGRP "U_CLK" TO TIMEGRP "J_CLK" 15 ns; 18 items analyzed, 0 timing errors detected. (0 setup errors, 0 hold errors) Maximum delay is 3.455ns. -------------------------------------------------------------------------------- ================================================================================ Timing constraint: TS_U_TO_U = MAXDELAY FROM TIMEGRP "U_CLK" TO TIMEGRP "U_CLK" 15 ns; 1 item analyzed, 0 timing errors detected. (0 setup errors, 0 hold errors) Maximum delay is 1.496ns. -------------------------------------------------------------------------------- ================================================================================ Timing constraint: PATH "TS_U_TO_D_path" TIG; 0 items analyzed, 0 timing errors detected. -------------------------------------------------------------------------------- ================================================================================ Timing constraint: PATH "TS_J_TO_D_path" TIG; 440 items analyzed, 0 timing errors detected. (0 setup errors, 0 hold errors) -------------------------------------------------------------------------------- ================================================================================ Timing constraint: PATH "TS_D_TO_J_path" TIG; 454 items analyzed, 0 timing errors detected. (0 setup errors, 0 hold errors) -------------------------------------------------------------------------------- ================================================================================ Timing constraint: TS_adc_clk_ppad_i = PERIOD TIMEGRP "adc_clk_ppad_i" 7 ns HIGH 50%; 76382 items analyzed, 1 timing error detected. (1 setup error, 0 hold errors) Minimum period is 7.135ns. -------------------------------------------------------------------------------- Slack: -0.135ns (requirement - (data path - clock path skew + uncertainty)) Source: PLL/n6_16 (FF) Destination: PLL/dds_freq_28 (FF) Requirement: 7.000ns Data Path Delay: 7.104ns (Levels of Logic = 18) Clock Path Skew: -0.031ns Source Clock: DIO_2_OBUF rising at 0.000ns Destination Clock: DIO_2_OBUF rising at 7.000ns Clock Uncertainty: 0.000ns Data Path: PLL/n6_16 to PLL/dds_freq_28 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X4Y82.XQ Tcko 0.374 PLL/n6<16> PLL/n6_16 SLICE_X5Y80.F1 net (fanout=3) 0.429 PLL/n6<16> SLICE_X5Y80.X Tilo 0.288 PLL/Mshift_F_ERR_Sh<16> PLL/Mshift_F_ERR_Sh<16>1 SLICE_X9Y80.F2 net (fanout=4) 0.388 PLL/Mshift_F_ERR_Sh<16> SLICE_X9Y80.X Tif5x 0.653 PLL/Mshift_F_ERR_Sh<42> PLL/Mshift_F_ERR_Sh<42>281_G PLL/Mshift_F_ERR_Sh<42>281 SLICE_X9Y77.G3 net (fanout=3) 0.295 PLL/Mshift_F_ERR_Sh<42> SLICE_X9Y77.Y Tilo 0.313 PLL/chipscope/i_ila_6CH/i_dt0/1/data_dly1_75 PLL/Mshift_F_ERR_Result<2>40 SLICE_X10Y63.F3 net (fanout=3) 0.793 PLL/F_ERR<2> SLICE_X10Y63.COUT Topcyf 0.744 PLL/_n0049<2> PLL/PLL3__n0049<2>lut/LUT2_L_BUF PLL/PLL3__n0049<2>cy PLL/PLL3__n0049<3>cy SLICE_X10Y64.CIN net (fanout=1) 0.000 PLL/PLL3__n0049<3>_cyo SLICE_X10Y64.COUT Tbyp 0.083 PLL/_n0049<4> PLL/PLL3__n0049<4>cy PLL/PLL3__n0049<5>cy SLICE_X10Y65.CIN net (fanout=1) 0.000 PLL/PLL3__n0049<5>_cyo SLICE_X10Y65.COUT Tbyp 0.083 PLL/_n0049<6> PLL/PLL3__n0049<6>cy PLL/PLL3__n0049<7>cy SLICE_X10Y66.CIN net (fanout=1) 0.000 PLL/PLL3__n0049<7>_cyo SLICE_X10Y66.COUT Tbyp 0.083 PLL/_n0049<8> PLL/PLL3__n0049<8>cy PLL/PLL3__n0049<9>cy SLICE_X10Y67.CIN net (fanout=1) 0.000 PLL/PLL3__n0049<9>_cyo SLICE_X10Y67.COUT Tbyp 0.083 PLL/_n0049<10> PLL/PLL3__n0049<10>cy PLL/PLL3__n0049<11>cy SLICE_X10Y68.CIN net (fanout=1) 0.000 PLL/PLL3__n0049<11>_cyo SLICE_X10Y68.COUT Tbyp 0.083 PLL/_n0049<12> PLL/PLL3__n0049<12>cy PLL/PLL3__n0049<13>cy SLICE_X10Y69.CIN net (fanout=1) 0.000 PLL/PLL3__n0049<13>_cyo SLICE_X10Y69.COUT Tbyp 0.083 PLL/_n0049<14> PLL/PLL3__n0049<14>cy PLL/PLL3__n0049<15>cy SLICE_X10Y70.CIN net (fanout=1) 0.000 PLL/PLL3__n0049<15>_cyo SLICE_X10Y70.COUT Tbyp 0.083 PLL/_n0049<16> PLL/PLL3__n0049<16>cy PLL/PLL3__n0049<17>cy SLICE_X10Y71.CIN net (fanout=1) 0.000 PLL/PLL3__n0049<17>_cyo SLICE_X10Y71.COUT Tbyp 0.083 PLL/_n0049<18> PLL/PLL3__n0049<18>cy PLL/PLL3__n0049<19>cy SLICE_X10Y72.CIN net (fanout=1) 0.000 PLL/PLL3__n0049<19>_cyo SLICE_X10Y72.COUT Tbyp 0.083 PLL/_n0049<20> PLL/PLL3__n0049<20>cy PLL/PLL3__n0049<21>cy SLICE_X10Y73.CIN net (fanout=1) 0.000 PLL/PLL3__n0049<21>_cyo SLICE_X10Y73.COUT Tbyp 0.083 PLL/_n0049<22> PLL/PLL3__n0049<22>cy PLL/PLL3__n0049<23>cy SLICE_X10Y74.CIN net (fanout=1) 0.000 PLL/PLL3__n0049<23>_cyo SLICE_X10Y74.COUT Tbyp 0.083 PLL/_n0049<24> PLL/PLL3__n0049<24>cy PLL/PLL3__n0049<25>cy SLICE_X10Y75.CIN net (fanout=1) 0.000 PLL/PLL3__n0049<25>_cyo SLICE_X10Y75.COUT Tbyp 0.083 PLL/_n0049<26> PLL/PLL3__n0049<26>cy PLL/PLL3__n0049<27>cy SLICE_X10Y76.CIN net (fanout=1) 0.000 PLL/PLL3__n0049<27>_cyo SLICE_X10Y76.X Tcinx 0.773 PLL/_n0049<28> PLL/PLL3__n0049<28>_xor SLICE_X12Y63.G3 net (fanout=1) 0.745 PLL/_n0049<28> SLICE_X12Y63.Y Tilo 0.313 PLL/dds_freq<28> PLL/_n0033<28>37 SLICE_X12Y63.DY net (fanout=1) 0.000 PLL/_n0033<28>37/O SLICE_X12Y63.CLK Tdyck 0.000 PLL/dds_freq<28> PLL/dds_freq_28 ------------------------------------------------- --------------------------- Total 7.104ns (4.454ns logic, 2.650ns route) (62.7% logic, 37.3% route) -------------------------------------------------------------------------------- Slack: -0.121ns (requirement - (data path - clock path skew + uncertainty)) Source: PLL/n6_11 (FF) Destination: PLL/dds_freq_28 (FF) Requirement: 7.000ns Data Path Delay: 7.089ns (Levels of Logic = 18) Clock Path Skew: -0.032ns Source Clock: DIO_2_OBUF rising at 0.000ns Destination Clock: DIO_2_OBUF rising at 7.000ns Clock Uncertainty: 0.000ns Data Path: PLL/n6_11 to PLL/dds_freq_28 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X4Y79.YQ Tcko 0.374 PLL/n6<10> PLL/n6_11 SLICE_X8Y80.F2 net (fanout=7) 0.625 PLL/n6<11> SLICE_X8Y80.X Tilo 0.288 PLL/Mshift_F_ERR_Sh<10> PLL/Mshift_F_ERR_Sh<10>1 SLICE_X9Y80.G1 net (fanout=2) 0.177 PLL/Mshift_F_ERR_Sh<10> SLICE_X9Y80.X Tif5x 0.653 PLL/Mshift_F_ERR_Sh<42> PLL/Mshift_F_ERR_Sh<42>281_F PLL/Mshift_F_ERR_Sh<42>281 SLICE_X9Y77.G3 net (fanout=3) 0.295 PLL/Mshift_F_ERR_Sh<42> SLICE_X9Y77.Y Tilo 0.313 PLL/chipscope/i_ila_6CH/i_dt0/1/data_dly1_75 PLL/Mshift_F_ERR_Result<2>40 SLICE_X10Y63.F3 net (fanout=3) 0.793 PLL/F_ERR<2> SLICE_X10Y63.COUT Topcyf 0.744 PLL/_n0049<2> PLL/PLL3__n0049<2>lut/LUT2_L_BUF PLL/PLL3__n0049<2>cy PLL/PLL3__n0049<3>cy SLICE_X10Y64.CIN net (fanout=1) 0.000 PLL/PLL3__n0049<3>_cyo SLICE_X10Y64.COUT Tbyp 0.083 PLL/_n0049<4> PLL/PLL3__n0049<4>cy PLL/PLL3__n0049<5>cy SLICE_X10Y65.CIN net (fanout=1) 0.000 PLL/PLL3__n0049<5>_cyo SLICE_X10Y65.COUT Tbyp 0.083 PLL/_n0049<6> PLL/PLL3__n0049<6>cy PLL/PLL3__n0049<7>cy SLICE_X10Y66.CIN net (fanout=1) 0.000 PLL/PLL3__n0049<7>_cyo SLICE_X10Y66.COUT Tbyp 0.083 PLL/_n0049<8> PLL/PLL3__n0049<8>cy PLL/PLL3__n0049<9>cy SLICE_X10Y67.CIN net (fanout=1) 0.000 PLL/PLL3__n0049<9>_cyo SLICE_X10Y67.COUT Tbyp 0.083 PLL/_n0049<10> PLL/PLL3__n0049<10>cy PLL/PLL3__n0049<11>cy SLICE_X10Y68.CIN net (fanout=1) 0.000 PLL/PLL3__n0049<11>_cyo SLICE_X10Y68.COUT Tbyp 0.083 PLL/_n0049<12> PLL/PLL3__n0049<12>cy PLL/PLL3__n0049<13>cy SLICE_X10Y69.CIN net (fanout=1) 0.000 PLL/PLL3__n0049<13>_cyo SLICE_X10Y69.COUT Tbyp 0.083 PLL/_n0049<14> PLL/PLL3__n0049<14>cy PLL/PLL3__n0049<15>cy SLICE_X10Y70.CIN net (fanout=1) 0.000 PLL/PLL3__n0049<15>_cyo SLICE_X10Y70.COUT Tbyp 0.083 PLL/_n0049<16> PLL/PLL3__n0049<16>cy PLL/PLL3__n0049<17>cy SLICE_X10Y71.CIN net (fanout=1) 0.000 PLL/PLL3__n0049<17>_cyo SLICE_X10Y71.COUT Tbyp 0.083 PLL/_n0049<18> PLL/PLL3__n0049<18>cy PLL/PLL3__n0049<19>cy SLICE_X10Y72.CIN net (fanout=1) 0.000 PLL/PLL3__n0049<19>_cyo SLICE_X10Y72.COUT Tbyp 0.083 PLL/_n0049<20> PLL/PLL3__n0049<20>cy PLL/PLL3__n0049<21>cy SLICE_X10Y73.CIN net (fanout=1) 0.000 PLL/PLL3__n0049<21>_cyo SLICE_X10Y73.COUT Tbyp 0.083 PLL/_n0049<22> PLL/PLL3__n0049<22>cy PLL/PLL3__n0049<23>cy SLICE_X10Y74.CIN net (fanout=1) 0.000 PLL/PLL3__n0049<23>_cyo SLICE_X10Y74.COUT Tbyp 0.083 PLL/_n0049<24> PLL/PLL3__n0049<24>cy PLL/PLL3__n0049<25>cy SLICE_X10Y75.CIN net (fanout=1) 0.000 PLL/PLL3__n0049<25>_cyo SLICE_X10Y75.COUT Tbyp 0.083 PLL/_n0049<26> PLL/PLL3__n0049<26>cy PLL/PLL3__n0049<27>cy SLICE_X10Y76.CIN net (fanout=1) 0.000 PLL/PLL3__n0049<27>_cyo SLICE_X10Y76.X Tcinx 0.773 PLL/_n0049<28> PLL/PLL3__n0049<28>_xor SLICE_X12Y63.G3 net (fanout=1) 0.745 PLL/_n0049<28> SLICE_X12Y63.Y Tilo 0.313 PLL/dds_freq<28> PLL/_n0033<28>37 SLICE_X12Y63.DY net (fanout=1) 0.000 PLL/_n0033<28>37/O SLICE_X12Y63.CLK Tdyck 0.000 PLL/dds_freq<28> PLL/dds_freq_28 ------------------------------------------------- --------------------------- Total 7.089ns (4.454ns logic, 2.635ns route) (62.8% logic, 37.2% route) -------------------------------------------------------------------------------- Slack: -0.062ns (requirement - (data path - clock path skew + uncertainty)) Source: PLL/n6_10 (FF) Destination: PLL/dds_freq_28 (FF) Requirement: 7.000ns Data Path Delay: 7.030ns (Levels of Logic = 18) Clock Path Skew: -0.032ns Source Clock: DIO_2_OBUF rising at 0.000ns Destination Clock: DIO_2_OBUF rising at 7.000ns Clock Uncertainty: 0.000ns Data Path: PLL/n6_10 to PLL/dds_freq_28 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X4Y79.XQ Tcko 0.374 PLL/n6<10> PLL/n6_10 SLICE_X8Y80.F4 net (fanout=8) 0.566 PLL/n6<10> SLICE_X8Y80.X Tilo 0.288 PLL/Mshift_F_ERR_Sh<10> PLL/Mshift_F_ERR_Sh<10>1 SLICE_X9Y80.G1 net (fanout=2) 0.177 PLL/Mshift_F_ERR_Sh<10> SLICE_X9Y80.X Tif5x 0.653 PLL/Mshift_F_ERR_Sh<42> PLL/Mshift_F_ERR_Sh<42>281_F PLL/Mshift_F_ERR_Sh<42>281 SLICE_X9Y77.G3 net (fanout=3) 0.295 PLL/Mshift_F_ERR_Sh<42> SLICE_X9Y77.Y Tilo 0.313 PLL/chipscope/i_ila_6CH/i_dt0/1/data_dly1_75 PLL/Mshift_F_ERR_Result<2>40 SLICE_X10Y63.F3 net (fanout=3) 0.793 PLL/F_ERR<2> SLICE_X10Y63.COUT Topcyf 0.744 PLL/_n0049<2> PLL/PLL3__n0049<2>lut/LUT2_L_BUF PLL/PLL3__n0049<2>cy PLL/PLL3__n0049<3>cy SLICE_X10Y64.CIN net (fanout=1) 0.000 PLL/PLL3__n0049<3>_cyo SLICE_X10Y64.COUT Tbyp 0.083 PLL/_n0049<4> PLL/PLL3__n0049<4>cy PLL/PLL3__n0049<5>cy SLICE_X10Y65.CIN net (fanout=1) 0.000 PLL/PLL3__n0049<5>_cyo SLICE_X10Y65.COUT Tbyp 0.083 PLL/_n0049<6> PLL/PLL3__n0049<6>cy PLL/PLL3__n0049<7>cy SLICE_X10Y66.CIN net (fanout=1) 0.000 PLL/PLL3__n0049<7>_cyo SLICE_X10Y66.COUT Tbyp 0.083 PLL/_n0049<8> PLL/PLL3__n0049<8>cy PLL/PLL3__n0049<9>cy SLICE_X10Y67.CIN net (fanout=1) 0.000 PLL/PLL3__n0049<9>_cyo SLICE_X10Y67.COUT Tbyp 0.083 PLL/_n0049<10> PLL/PLL3__n0049<10>cy PLL/PLL3__n0049<11>cy SLICE_X10Y68.CIN net (fanout=1) 0.000 PLL/PLL3__n0049<11>_cyo SLICE_X10Y68.COUT Tbyp 0.083 PLL/_n0049<12> PLL/PLL3__n0049<12>cy PLL/PLL3__n0049<13>cy SLICE_X10Y69.CIN net (fanout=1) 0.000 PLL/PLL3__n0049<13>_cyo SLICE_X10Y69.COUT Tbyp 0.083 PLL/_n0049<14> PLL/PLL3__n0049<14>cy PLL/PLL3__n0049<15>cy SLICE_X10Y70.CIN net (fanout=1) 0.000 PLL/PLL3__n0049<15>_cyo SLICE_X10Y70.COUT Tbyp 0.083 PLL/_n0049<16> PLL/PLL3__n0049<16>cy PLL/PLL3__n0049<17>cy SLICE_X10Y71.CIN net (fanout=1) 0.000 PLL/PLL3__n0049<17>_cyo SLICE_X10Y71.COUT Tbyp 0.083 PLL/_n0049<18> PLL/PLL3__n0049<18>cy PLL/PLL3__n0049<19>cy SLICE_X10Y72.CIN net (fanout=1) 0.000 PLL/PLL3__n0049<19>_cyo SLICE_X10Y72.COUT Tbyp 0.083 PLL/_n0049<20> PLL/PLL3__n0049<20>cy PLL/PLL3__n0049<21>cy SLICE_X10Y73.CIN net (fanout=1) 0.000 PLL/PLL3__n0049<21>_cyo SLICE_X10Y73.COUT Tbyp 0.083 PLL/_n0049<22> PLL/PLL3__n0049<22>cy PLL/PLL3__n0049<23>cy SLICE_X10Y74.CIN net (fanout=1) 0.000 PLL/PLL3__n0049<23>_cyo SLICE_X10Y74.COUT Tbyp 0.083 PLL/_n0049<24> PLL/PLL3__n0049<24>cy PLL/PLL3__n0049<25>cy SLICE_X10Y75.CIN net (fanout=1) 0.000 PLL/PLL3__n0049<25>_cyo SLICE_X10Y75.COUT Tbyp 0.083 PLL/_n0049<26> PLL/PLL3__n0049<26>cy PLL/PLL3__n0049<27>cy SLICE_X10Y76.CIN net (fanout=1) 0.000 PLL/PLL3__n0049<27>_cyo SLICE_X10Y76.X Tcinx 0.773 PLL/_n0049<28> PLL/PLL3__n0049<28>_xor SLICE_X12Y63.G3 net (fanout=1) 0.745 PLL/_n0049<28> SLICE_X12Y63.Y Tilo 0.313 PLL/dds_freq<28> PLL/_n0033<28>37 SLICE_X12Y63.DY net (fanout=1) 0.000 PLL/_n0033<28>37/O SLICE_X12Y63.CLK Tdyck 0.000 PLL/dds_freq<28> PLL/dds_freq_28 ------------------------------------------------- --------------------------- Total 7.030ns (4.454ns logic, 2.576ns route) (63.4% logic, 36.6% route) -------------------------------------------------------------------------------- 1 constraint not met. Data Sheet report: ----------------- All values displayed in nanoseconds (ns) Clock to Setup on destination clock adc_clk_npad_i ---------------+---------+---------+---------+---------+ | Src:Rise| Src:Fall| Src:Rise| Src:Fall| Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| ---------------+---------+---------+---------+---------+ adc_clk_npad_i | 7.135| 2.387| 3.359| 6.915| adc_clk_ppad_i | 7.135| 2.387| 3.359| 6.915| ---------------+---------+---------+---------+---------+ Clock to Setup on destination clock adc_clk_ppad_i ---------------+---------+---------+---------+---------+ | Src:Rise| Src:Fall| Src:Rise| Src:Fall| Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| ---------------+---------+---------+---------+---------+ adc_clk_npad_i | 7.135| 2.387| 3.359| 6.915| adc_clk_ppad_i | 7.135| 2.387| 3.359| 6.915| ---------------+---------+---------+---------+---------+ Timing summary: --------------- Timing errors: 1 Score: 135 Constraints cover 87594 paths, 0 nets, and 11381 connections Design statistics: Minimum period: 10.510ns (Maximum frequency: 95.147MHz) Maximum path delay from/to any node: 10.510ns Analysis completed Thu Nov 16 10:26:39 2006 -------------------------------------------------------------------------------- Peak Memory Usage: 213 MB