AstroFft

 

Astro FFT Astronomical FFT processing system

Introduction

This is a specification for the Radio Astronomy FFT processing system (AstroFFT). Signals received from the Radio Telescope need to be processed in order to pick out the signature spectrum from the large level of noise. This requires processing large amounts of data at a fast real-time rate, integrating the results over a long period and storing the results in data files that can be further processed by researchers.

Processing System Specification

The system consists of a 4u high 19inch rack-mount processing unit with external monitor, keyboard and mouse.

The processing system consists of a dual Pentium III host computer system with two FPGA based FFT processing engines mounted in a 19inch rack case. Each FPGA processing engine has two analogue and one digital clock input. The system can be linked to other systems by means of a 10/100 BaseT Ethernet network interface. The host system has a display, keyboard and mouse for local operation and maintenance. It is possible to operate the unit locally or remotely via the network interface.

Most of the high speed processing is performed by the FPGA computer engines. The host system is responsible for overall system control, low speed data post processing and data storage and transfer.

The host runs the Linux operating system and provides the full features of this system including the ability for users to develop applications to control the system and/or process the data. However, the system can also be used as a stand-alone black box system controlled from another computer through the network interface.

Processing Engine Specification

The system consists of two separate FFT processing engines implemented on two separate FPGA based hardware boards. Each processing engine  has two Analogue to Digital samplers, feeding into a large FPGA and is connected to the PCI bus of the host computer.

In order to achieve the high number of frequency sample outputs required an analogue quadrature mixer is employed, prior to the FPGA processing engine, to convert the telescopes 25Mhz bandwidth signal into two signals in quadrature. The quadrature mixer is not required when 2048 frequency samples are required. The two quadrature signals are fed to the two analogue to digital samplers.

Each processing engine has the following features:

• Two Analogue Inputs through SMB connectors. Each input will accept a 1v p-p signal over a bandwidth of 1 KHz to 25 MHz -1dB and has a 50 ohm input impedance. Each input has a separate analogue ground fed into differential inputs.
• Each analogue input has an anti-aliasing filter with a cutoff frequency of 23Mhz (-0.5db) and at least -20db at 25 MHz with a maximum of +- 0.5db ripple within the pass band.
• Each analogue input has a single order high pass filter with a cut off frequency of 500 Hz (-3db).
• Each analogue input stage has the same physical geometry in order to minimise any phase or other differences between the two analogue input stages.
• Each processing engine has an external digital clock input through a SMB connector. This is fed to a differential input buffer and will accept a digital clock of 0-5V and has an input impedance of 100 ohm. The frequency of this clock should be 50MHz but can be reduced to 1.5625 MHz which will lower the sample rate and FFT result frequency spacing accordingly.
• The processing engines master sample clock can be derived from one of three sources by means of a jumper on the A/D board. In one setting the user input clock will be directly used, in another setting the on-board 50 MHz clock will be directly used, in the final setting a clock produced by the FPGA will be used. The FPGA generated clock is derived from either the external or on-board 50 MHz clock source, the choise of which will be software selectable. The FPGA generated clock will be able to be divided down to provide the following output frequencies: 50MHz, 25MHz, 12.5MHz, 6.25MHz, 3.125MHz and 1.5625MHz, this is software selectable. A diagram of the master clock system is shown below.

• Each filtered analogue input is sampled at the sample clock frequency by a 14 bit analogue to digital convertor. The full 14 bits are passed to the FPGA. The FPGA uses the top 12 bits of the input.
• The FPGA accepts the two 12bit sampled channels and the master sample clock and performs the FFT calculation and integration of the magnitude of the resulting frequency components.
• The FFT engine performs a continuous complex 4096 point FFT on the sampled analogue inputs.

FFT Algorithm

The FFT engine's internal data resolution is a minimum of 12 bits for each of the real and imaginary components. Adaptive scaling is used in the FPGA to improve the bit resolution of the overall FFT process. It uses a radix-4 algorithm.

The algorithm uses two's complement fixed point arithmetic. Values are thus in the range +-0.9999. In all cases where bits of data are discarded (fixed point multiplications and scaling of the data) the value of the data is rounded to the nearest value. The radix-4 butterfly operations yield higher resolution (number of bits) results. These results are either scaled down by 4 or the upper bits will be ignored depending on the adaptive scaling's prediction.

The actual adaptive scaling system is as follows: On the first FFT pass the radix-4 butterfly results are divided by 8. Each butterfly result, real and imaginary after scaling, is tested to see if its magnitude is greater than or equal to 0.125. If any result is greater than or equal to this then the butterfly results of the next pass will be divided by 8. If no result is greater than or equal to 0.125 then the butterfly results of the next pass will not be scaled, instead the top 3 bits will be discarded. On each divide by 8 scaling an overall FFT scaling flag is incremented to indicate the scaling of the resultant data.

FFT Basic Mode Functionality

The FPGA processing engine can be able to be set into one of a number of modes as listed below.

FFT Mode: In this mode a single ATD convertor samples a single analogue data stream at 50Mhz. The ATD samples are fed into the real inputs of a 4096 point FFT using fixed point math. The FFT generates 4096 complex frequency samples. The following integrator will integrate all 4096 samples although only the first 2048 are usefull. The magnitude of each complex frequency sample, formed by squareing the real and imaginary parts separately and then adding them, is added to an intergrating buffer. After a given number of FFT runs have been processed and added to the integrator the integrated results are passed to the host.

QFFT Mode: In this mode the twin ATD convertors sample the two analogue data streams at 25Mhz. The ATD samples are fed into the real and imaginary inputs of a 4096 point FFT using fixed point math. The FFT generates 4096 complex frequency samples. The following integrator integrates all of the 4096 samples separately. The magnitude of each complex frequency sample, formed by squareing the real and imaginary parts separately and then adding them, is added to the intergrating buffer. After a given number of FFT runs have been processed and added to the integrator the integrated results are passed to the host.

RFFT Mode: In this mode a single ATD convertor samples the single analogue data stream at 50Mhz. Alternate ATD samples are fed into the real and imaginary inputs of a 4096 point FFT using fixed point math. The FFT will generate 4096 mixed complex frequency samples. A following post processing filter takes these samples and produces the genuine 4096 frequency samples. The following integrator takes all of the 4096 samples. The magnitude of each complex frequency sample, formed by squareing the real and imaginary parts separately and then adding them, is added to the intergrating buffer. After a given number of FFT runs have been processed and added to the integrator the integrated results are passed to the host.

Analogue Mode: In this mode both ATD convertors sample at 50Mhz. The 14 bit samples are bit extended with 0's at the lower end to form 16 bit values. The two 16 bit values are combined into a 32 bit value and fed to the host. The FPGA also calculates the RMS power and the number of ATD peak values of each data stream and passes this to the host with each set of samples.

Processing engine configuration parameters

System Software

The FFT system software consists of a main control process, Astrofft, and two user interface applications. The main control process, Astrofft,  is responsible for managing the FPGA processing engines and data storage. The user interface applications enable users to control the this process.
The Astrofft process starts up when the system is booted and will run continually while the system is in operation. It is responsible for booting and controlling the FPGA processing engines and performing data post processing.

The Astrofft process provides a network socket interface. This enables both local user interface applications and remote computers to send commands and receive data to/from the Astro FFT system. ASCII text based commands are supported that can be sent via a Telnet session or a computer program on the remote computer.

The Astrogui process provides a graphical user Interface to the system. This X-Windows based application allows users to control the FFT system and view interim results.

The main control parameters are as follows:

The system will perform a complete run based on the parameters setup. Information on the run and the raw sample data from each channel is stored into three files on the systems disk drive. The information file contains information on the parameters used and the run start and stop times. The data files contain the data in binary or ASCII formats for each channel. The ASCII format will consists of lines each storing a complete FFT average output with comma separated sample values.

The data files are stored in the /data directory which can be mounted from a remote system using either NFS or Microsoft Windows SMB protocols. This allows remote systems to access the data from the processing runs.

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