NvmeRead: Improved system. Now working with Pcie address tracking block numbers.
authorTerry Barnaby <terry.barnaby@beam.beam.ltd.uk>
Wed, 20 May 2020 11:07:49 +0000 (12:07 +0100)
committerTerry Barnaby <terry.barnaby@beam.beam.ltd.uk>
Wed, 20 May 2020 11:07:49 +0000 (12:07 +0100)
sim/testbench/test020-write.sav
sim/testbench/test020-write.vhd
src/NvmeConfig.vhd
src/NvmeRead.vhd
src/NvmeSim.vhd
src/NvmeStreamMux.vhd
test/test_nvme.cpp

index a3bb0d8f2ca5da73cf09bd754ec969c1e56b2c42..4071ee05f34f8ca0f6188deee16f19da5c3cbb68 100644 (file)
@@ -1,15 +1,15 @@
 [*]
 [*] GTKWave Analyzer v3.3.105 (w)1999-2020 BSI
-[*] Wed May 20 06:19:38 2020
+[*] Wed May 20 09:37:37 2020
 [*]
 [dumpfile] "/src/dune/FpgaPlay/test031-nvmewrite/sim/simu/test.ghw"
-[dumpfile_mtime] "Wed May 20 06:06:17 2020"
-[dumpfile_size] 2834231
+[dumpfile_mtime] "Wed May 20 09:37:15 2020"
+[dumpfile_size] 2880561
 [savefile] "/src/dune/FpgaPlay/test031-nvmewrite/sim/testbench/test020-write.sav"
-[timestart] 378700000
+[timestart] 3952900000
 [size] 1920 1171
 [pos] -1 -1
-*-26.418455 571000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+*-26.418455 4120600000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
 [treeopen] top.
 [treeopen] top.test.
 [treeopen] top.test.axil.
@@ -19,6 +19,7 @@
 [treeopen] top.test.nvmestorage0.datain.
 [treeopen] top.test.nvmestorage0.nvme0send.
 [treeopen] top.test.nvmestorage0.nvmestorageunit0.
+[treeopen] top.test.nvmestorage0.nvmestorageunit0.gen03.
 [treeopen] top.test.nvmestorage0.nvmestorageunit0.gen03.nvmeread0.requestout.
 [treeopen] top.test.nvmestorage0.nvmestorageunit0.gen03.nvmewrite0.buffers.[0].
 [treeopen] top.test.nvmestorage0.nvmestorageunit0.gen03.nvmewrite0.buffers.[1].
@@ -38,7 +39,7 @@
 [treeopen] top.test.nvmestorage0.nvmestorageunit0.streamsend.[0].
 [treeopen] top.test.nvmestorage0.nvmestorageunit0.streamsend.[2].
 [sst_width] 259
-[signals_width] 806
+[signals_width] 726
 [sst_expanded] 1
 [sst_vpaned_height] 768
 @28
@@ -101,6 +102,10 @@ top.test.axil.tomaster.rvalid
 -Registers
 @800200
 -NvmeRead
+@28
+top.test.nvmestorage0.nvmestorageunit0.gen03.nvmeread0.enabled
+@29
+top.test.nvmestorage0.nvmestorageunit0.gen03.nvmeread0.complete
 @22
 #{top.test.nvmestorage0.nvmestorageunit0.gen03.nvmeread0.regaddress[3:0]} top.test.nvmestorage0.nvmestorageunit0.gen03.nvmeread0.regaddress[3] top.test.nvmestorage0.nvmestorageunit0.gen03.nvmeread0.regaddress[2] top.test.nvmestorage0.nvmestorageunit0.gen03.nvmeread0.regaddress[1] top.test.nvmestorage0.nvmestorageunit0.gen03.nvmeread0.regaddress[0]
 #{top.test.nvmestorage0.nvmestorageunit0.gen03.nvmeread0.control[31:0]} top.test.nvmestorage0.nvmestorageunit0.gen03.nvmeread0.control[31] top.test.nvmestorage0.nvmestorageunit0.gen03.nvmeread0.control[30] top.test.nvmestorage0.nvmestorageunit0.gen03.nvmeread0.control[29] top.test.nvmestorage0.nvmestorageunit0.gen03.nvmeread0.control[28] top.test.nvmestorage0.nvmestorageunit0.gen03.nvmeread0.control[27] top.test.nvmestorage0.nvmestorageunit0.gen03.nvmeread0.control[26] top.test.nvmestorage0.nvmestorageunit0.gen03.nvmeread0.control[25] top.test.nvmestorage0.nvmestorageunit0.gen03.nvmeread0.control[24] top.test.nvmestorage0.nvmestorageunit0.gen03.nvmeread0.control[23] top.test.nvmestorage0.nvmestorageunit0.gen03.nvmeread0.control[22] top.test.nvmestorage0.nvmestorageunit0.gen03.nvmeread0.control[21] top.test.nvmestorage0.nvmestorageunit0.gen03.nvmeread0.control[20] top.test.nvmestorage0.nvmestorageunit0.gen03.nvmeread0.control[19] top.test.nvmestorage0.nvmestorageunit0.gen03.nvmeread0.control[18] top.test.nvmestorage0.nvmestorageunit0.gen03.nvmeread0.control[17] top.test.nvmestorage0.nvmestorageunit0.gen03.nvmeread0.control[16] top.test.nvmestorage0.nvmestorageunit0.gen03.nvmeread0.control[15] top.test.nvmestorage0.nvmestorageunit0.gen03.nvmeread0.control[14] top.test.nvmestorage0.nvmestorageunit0.gen03.nvmeread0.control[13] top.test.nvmestorage0.nvmestorageunit0.gen03.nvmeread0.control[12] top.test.nvmestorage0.nvmestorageunit0.gen03.nvmeread0.control[11] top.test.nvmestorage0.nvmestorageunit0.gen03.nvmeread0.control[10] top.test.nvmestorage0.nvmestorageunit0.gen03.nvmeread0.control[9] top.test.nvmestorage0.nvmestorageunit0.gen03.nvmeread0.control[8] top.test.nvmestorage0.nvmestorageunit0.gen03.nvmeread0.control[7] top.test.nvmestorage0.nvmestorageunit0.gen03.nvmeread0.control[6] top.test.nvmestorage0.nvmestorageunit0.gen03.nvmeread0.control[5] top.test.nvmestorage0.nvmestorageunit0.gen03.nvmeread0.control[4] top.test.nvmestorage0.nvmestorageunit0.gen03.nvmeread0.control[3] top.test.nvmestorage0.nvmestorageunit0.gen03.nvmeread0.control[2] top.test.nvmestorage0.nvmestorageunit0.gen03.nvmeread0.control[1] top.test.nvmestorage0.nvmestorageunit0.gen03.nvmeread0.control[0]
@@ -166,11 +171,13 @@ top.test.nvmestorage0.data0.last
 @22
 #{top.test.nvmestorage0.data0.data[127:0]} top.test.nvmestorage0.data0.data[127] top.test.nvmestorage0.data0.data[126] top.test.nvmestorage0.data0.data[125] top.test.nvmestorage0.data0.data[124] top.test.nvmestorage0.data0.data[123] top.test.nvmestorage0.data0.data[122] top.test.nvmestorage0.data0.data[121] top.test.nvmestorage0.data0.data[120] top.test.nvmestorage0.data0.data[119] top.test.nvmestorage0.data0.data[118] top.test.nvmestorage0.data0.data[117] top.test.nvmestorage0.data0.data[116] top.test.nvmestorage0.data0.data[115] top.test.nvmestorage0.data0.data[114] top.test.nvmestorage0.data0.data[113] top.test.nvmestorage0.data0.data[112] top.test.nvmestorage0.data0.data[111] top.test.nvmestorage0.data0.data[110] top.test.nvmestorage0.data0.data[109] top.test.nvmestorage0.data0.data[108] top.test.nvmestorage0.data0.data[107] top.test.nvmestorage0.data0.data[106] top.test.nvmestorage0.data0.data[105] top.test.nvmestorage0.data0.data[104] top.test.nvmestorage0.data0.data[103] top.test.nvmestorage0.data0.data[102] top.test.nvmestorage0.data0.data[101] top.test.nvmestorage0.data0.data[100] top.test.nvmestorage0.data0.data[99] top.test.nvmestorage0.data0.data[98] top.test.nvmestorage0.data0.data[97] top.test.nvmestorage0.data0.data[96] top.test.nvmestorage0.data0.data[95] top.test.nvmestorage0.data0.data[94] top.test.nvmestorage0.data0.data[93] top.test.nvmestorage0.data0.data[92] top.test.nvmestorage0.data0.data[91] top.test.nvmestorage0.data0.data[90] top.test.nvmestorage0.data0.data[89] top.test.nvmestorage0.data0.data[88] top.test.nvmestorage0.data0.data[87] top.test.nvmestorage0.data0.data[86] top.test.nvmestorage0.data0.data[85] top.test.nvmestorage0.data0.data[84] top.test.nvmestorage0.data0.data[83] top.test.nvmestorage0.data0.data[82] top.test.nvmestorage0.data0.data[81] top.test.nvmestorage0.data0.data[80] top.test.nvmestorage0.data0.data[79] top.test.nvmestorage0.data0.data[78] top.test.nvmestorage0.data0.data[77] top.test.nvmestorage0.data0.data[76] top.test.nvmestorage0.data0.data[75] top.test.nvmestorage0.data0.data[74] top.test.nvmestorage0.data0.data[73] top.test.nvmestorage0.data0.data[72] top.test.nvmestorage0.data0.data[71] top.test.nvmestorage0.data0.data[70] top.test.nvmestorage0.data0.data[69] top.test.nvmestorage0.data0.data[68] top.test.nvmestorage0.data0.data[67] top.test.nvmestorage0.data0.data[66] top.test.nvmestorage0.data0.data[65] top.test.nvmestorage0.data0.data[64] top.test.nvmestorage0.data0.data[63] top.test.nvmestorage0.data0.data[62] top.test.nvmestorage0.data0.data[61] top.test.nvmestorage0.data0.data[60] top.test.nvmestorage0.data0.data[59] top.test.nvmestorage0.data0.data[58] top.test.nvmestorage0.data0.data[57] top.test.nvmestorage0.data0.data[56] top.test.nvmestorage0.data0.data[55] top.test.nvmestorage0.data0.data[54] top.test.nvmestorage0.data0.data[53] top.test.nvmestorage0.data0.data[52] top.test.nvmestorage0.data0.data[51] top.test.nvmestorage0.data0.data[50] top.test.nvmestorage0.data0.data[49] top.test.nvmestorage0.data0.data[48] top.test.nvmestorage0.data0.data[47] top.test.nvmestorage0.data0.data[46] top.test.nvmestorage0.data0.data[45] top.test.nvmestorage0.data0.data[44] top.test.nvmestorage0.data0.data[43] top.test.nvmestorage0.data0.data[42] top.test.nvmestorage0.data0.data[41] top.test.nvmestorage0.data0.data[40] top.test.nvmestorage0.data0.data[39] top.test.nvmestorage0.data0.data[38] top.test.nvmestorage0.data0.data[37] top.test.nvmestorage0.data0.data[36] top.test.nvmestorage0.data0.data[35] top.test.nvmestorage0.data0.data[34] top.test.nvmestorage0.data0.data[33] top.test.nvmestorage0.data0.data[32] top.test.nvmestorage0.data0.data[31] top.test.nvmestorage0.data0.data[30] top.test.nvmestorage0.data0.data[29] top.test.nvmestorage0.data0.data[28] top.test.nvmestorage0.data0.data[27] top.test.nvmestorage0.data0.data[26] top.test.nvmestorage0.data0.data[25] top.test.nvmestorage0.data0.data[24] top.test.nvmestorage0.data0.data[23] top.test.nvmestorage0.data0.data[22] top.test.nvmestorage0.data0.data[21] top.test.nvmestorage0.data0.data[20] top.test.nvmestorage0.data0.data[19] top.test.nvmestorage0.data0.data[18] top.test.nvmestorage0.data0.data[17] top.test.nvmestorage0.data0.data[16] top.test.nvmestorage0.data0.data[15] top.test.nvmestorage0.data0.data[14] top.test.nvmestorage0.data0.data[13] top.test.nvmestorage0.data0.data[12] top.test.nvmestorage0.data0.data[11] top.test.nvmestorage0.data0.data[10] top.test.nvmestorage0.data0.data[9] top.test.nvmestorage0.data0.data[8] top.test.nvmestorage0.data0.data[7] top.test.nvmestorage0.data0.data[6] top.test.nvmestorage0.data0.data[5] top.test.nvmestorage0.data0.data[4] top.test.nvmestorage0.data0.data[3] top.test.nvmestorage0.data0.data[2] top.test.nvmestorage0.data0.data[1] top.test.nvmestorage0.data0.data[0]
 @28
+top.test.nvmestorage0.nvmestreammux0.nvme1stream
 top.test.nvmestorage0.nvme0send.ready
 top.test.nvmestorage0.nvme0send.valid
 top.test.nvmestorage0.nvme1send.ready
 top.test.nvmestorage0.nvme1send.valid
 top.test.nvmestorage0.hostrecv0.ready
+top.test.nvmestorage0.hostrecv0.valid
 @1000200
 -NvmeStorage
 @800200
@@ -178,10 +185,10 @@ top.test.nvmestorage0.hostrecv0.ready
 @420
 top.test.nvmestorage0.nvmestorageunit0.pciestreammux0.muxstate
 @28
+top.test.nvmestorage0.nvmestorageunit0.hostsend.ready
+top.test.nvmestorage0.nvmestorageunit0.hostsend.valid
 top.test.nvmestorage0.nvmestorageunit0.hostrecv.ready
-@29
 top.test.nvmestorage0.nvmestorageunit0.hostrecv.valid
-@28
 top.test.nvmestorage0.nvmestorageunit0.pciestreammux0.stream2in.ready
 top.test.nvmestorage0.nvmestorageunit0.pciestreammux0.stream2in.valid
 top.test.nvmestorage0.nvmestorageunit0.pciestreammux0.stream3in.ready
@@ -303,6 +310,7 @@ top.test.nvmestorage0.nvmestorageunit0.sim.nvmesim0.state
 top.test.nvmestorage0.nvmestorageunit0.sim.nvmesim0.waitingforreply
 @22
 #{top.test.nvmestorage0.nvmestorageunit0.sim.nvmesim0.count[10:0]} top.test.nvmestorage0.nvmestorageunit0.sim.nvmesim0.count[10] top.test.nvmestorage0.nvmestorageunit0.sim.nvmesim0.count[9] top.test.nvmestorage0.nvmestorageunit0.sim.nvmesim0.count[8] top.test.nvmestorage0.nvmestorageunit0.sim.nvmesim0.count[7] top.test.nvmestorage0.nvmestorageunit0.sim.nvmesim0.count[6] top.test.nvmestorage0.nvmestorageunit0.sim.nvmesim0.count[5] top.test.nvmestorage0.nvmestorageunit0.sim.nvmesim0.count[4] top.test.nvmestorage0.nvmestorageunit0.sim.nvmesim0.count[3] top.test.nvmestorage0.nvmestorageunit0.sim.nvmesim0.count[2] top.test.nvmestorage0.nvmestorageunit0.sim.nvmesim0.count[1] top.test.nvmestorage0.nvmestorageunit0.sim.nvmesim0.count[0]
+#{top.test.nvmestorage0.nvmestorageunit0.sim.nvmesim0.chunkcount[10:0]} top.test.nvmestorage0.nvmestorageunit0.sim.nvmesim0.chunkcount[10] top.test.nvmestorage0.nvmestorageunit0.sim.nvmesim0.chunkcount[9] top.test.nvmestorage0.nvmestorageunit0.sim.nvmesim0.chunkcount[8] top.test.nvmestorage0.nvmestorageunit0.sim.nvmesim0.chunkcount[7] top.test.nvmestorage0.nvmestorageunit0.sim.nvmesim0.chunkcount[6] top.test.nvmestorage0.nvmestorageunit0.sim.nvmesim0.chunkcount[5] top.test.nvmestorage0.nvmestorageunit0.sim.nvmesim0.chunkcount[4] top.test.nvmestorage0.nvmestorageunit0.sim.nvmesim0.chunkcount[3] top.test.nvmestorage0.nvmestorageunit0.sim.nvmesim0.chunkcount[2] top.test.nvmestorage0.nvmestorageunit0.sim.nvmesim0.chunkcount[1] top.test.nvmestorage0.nvmestorageunit0.sim.nvmesim0.chunkcount[0]
 #{top.test.nvmestorage0.nvmestorageunit0.sim.nvmesim0.reg_io1_queue[31:0]} top.test.nvmestorage0.nvmestorageunit0.sim.nvmesim0.reg_io1_queue[31] top.test.nvmestorage0.nvmestorageunit0.sim.nvmesim0.reg_io1_queue[30] top.test.nvmestorage0.nvmestorageunit0.sim.nvmesim0.reg_io1_queue[29] top.test.nvmestorage0.nvmestorageunit0.sim.nvmesim0.reg_io1_queue[28] top.test.nvmestorage0.nvmestorageunit0.sim.nvmesim0.reg_io1_queue[27] top.test.nvmestorage0.nvmestorageunit0.sim.nvmesim0.reg_io1_queue[26] top.test.nvmestorage0.nvmestorageunit0.sim.nvmesim0.reg_io1_queue[25] top.test.nvmestorage0.nvmestorageunit0.sim.nvmesim0.reg_io1_queue[24] top.test.nvmestorage0.nvmestorageunit0.sim.nvmesim0.reg_io1_queue[23] top.test.nvmestorage0.nvmestorageunit0.sim.nvmesim0.reg_io1_queue[22] top.test.nvmestorage0.nvmestorageunit0.sim.nvmesim0.reg_io1_queue[21] top.test.nvmestorage0.nvmestorageunit0.sim.nvmesim0.reg_io1_queue[20] top.test.nvmestorage0.nvmestorageunit0.sim.nvmesim0.reg_io1_queue[19] top.test.nvmestorage0.nvmestorageunit0.sim.nvmesim0.reg_io1_queue[18] top.test.nvmestorage0.nvmestorageunit0.sim.nvmesim0.reg_io1_queue[17] top.test.nvmestorage0.nvmestorageunit0.sim.nvmesim0.reg_io1_queue[16] top.test.nvmestorage0.nvmestorageunit0.sim.nvmesim0.reg_io1_queue[15] top.test.nvmestorage0.nvmestorageunit0.sim.nvmesim0.reg_io1_queue[14] top.test.nvmestorage0.nvmestorageunit0.sim.nvmesim0.reg_io1_queue[13] top.test.nvmestorage0.nvmestorageunit0.sim.nvmesim0.reg_io1_queue[12] top.test.nvmestorage0.nvmestorageunit0.sim.nvmesim0.reg_io1_queue[11] top.test.nvmestorage0.nvmestorageunit0.sim.nvmesim0.reg_io1_queue[10] top.test.nvmestorage0.nvmestorageunit0.sim.nvmesim0.reg_io1_queue[9] top.test.nvmestorage0.nvmestorageunit0.sim.nvmesim0.reg_io1_queue[8] top.test.nvmestorage0.nvmestorageunit0.sim.nvmesim0.reg_io1_queue[7] top.test.nvmestorage0.nvmestorageunit0.sim.nvmesim0.reg_io1_queue[6] top.test.nvmestorage0.nvmestorageunit0.sim.nvmesim0.reg_io1_queue[5] top.test.nvmestorage0.nvmestorageunit0.sim.nvmesim0.reg_io1_queue[4] top.test.nvmestorage0.nvmestorageunit0.sim.nvmesim0.reg_io1_queue[3] top.test.nvmestorage0.nvmestorageunit0.sim.nvmesim0.reg_io1_queue[2] top.test.nvmestorage0.nvmestorageunit0.sim.nvmesim0.reg_io1_queue[1] top.test.nvmestorage0.nvmestorageunit0.sim.nvmesim0.reg_io1_queue[0]
 @28
 top.test.nvmestorage0.nvmestorageunit0.sim.nvmesim0.nvmereq.ready
index bd6b77f640afd02700ea51a41fa4aa55f682e659..2d65aa2a7c60535205fac491618a826a92265809 100644 (file)
@@ -221,7 +221,7 @@ begin
                        wait for 100 ns;
 
                        busWrite(clk, axil.toSlave, axil.toMaster, 16#0188#, 8);                -- Start blocks
-                       busWrite(clk, axil.toSlave, axil.toMaster, 16#018C#, 1);                -- Number blocks
+                       busWrite(clk, axil.toSlave, axil.toMaster, 16#018C#, 2);                -- Number blocks
                        busRead(clk, axil.toSlave, axil.toMaster, 16#0188#);
 
                        busWrite(clk, axil.toSlave, axil.toMaster, 16#0180#, 16#00000001#);     -- Start
@@ -236,12 +236,12 @@ begin
                        wait for 100 ns;
 
                        -- Write to DataQueue
-                       pcieRequestWriteHead(clk, hostReq, 1, 1, 16#02010000#, 16#22#, 16);
+                       pcieRequestWriteHead(clk, hostReq, 1, 1, 16#02020000#, 16#22#, 16);
 
                        wait until rising_edge(clk) and (hostReq.ready = '1');
                        hostReq.data <= zeros(64) & x"00000001" & x"01000002";  -- Namespace 1, From stream1, opcode 2
                        wait until rising_edge(clk) and (hostReq.ready = '1');
-                       hostReq.data <= zeros(32) & x"01F00000" & zeros(64);    -- Data source address to host
+                       hostReq.data <= zeros(32) & x"01800000" & zeros(64);    -- Data source address to host
                        wait until rising_edge(clk) and (hostReq.ready = '1');
                        hostReq.data <= zeros(32) & x"00000000" & zeros(64);    -- Block number
                        wait until rising_edge(clk) and (hostReq.ready = '1');
@@ -419,13 +419,12 @@ begin
                                                nvmeData        <= std_logic_vector(unsigned(nvmeData) + 1);
 
                                                if(nvmeChunkCount = 4) then
+                                                       nvmeReply.last  <= '0';
+                                                       nvmeReply.valid <= '0';
+
                                                        if(nvmeCount = 4) then
-                                                               nvmeReply.last  <= '0';
-                                                               nvmeReply.valid <= '0';
                                                                nvmeState       <= NVME_STATE_IDLE;
                                                        else
-                                                               nvmeReply.last  <= '0';
-                                                               nvmeReply.valid <= '0';
                                                                nvmeState       <= NVME_STATE_READHEAD;
                                                        end if;
 
index c10f01d7ba08499acc45f02e650daac04479009f..3f952e98dc9f3d14c331ececd3e43193dd1b4ad1 100644 (file)
@@ -75,7 +75,7 @@ signal state          : StateType := STATE_IDLE;
 
 --! The Configuration requests                         
 type RomType   is array(integer range <>) of std_logic_vector(127 downto 0);
-constant rom   : RomType(0 to 27) := (
+constant rom   : RomType(0 to 41) := (
        -- Set PCIe configuration command word
        setHeader(10, 16#00004#, 1, 0), to_stl(16#00010006#, 128),
        
@@ -107,13 +107,38 @@ constant rom      : RomType(0 to 27) := (
        setHeader(12, 16#02000000#, 16, 0),
                zeros(96) & x"02000001",                                        -- Dwords 3, 2, 1, 0
                zeros(32) & x"02010000" & zeros(64),                            -- DWords 7, 6, 5, 4
-               x"00000001" & to_stl(NvmeQueueNum-1, 16) & x"0001" & zeros(64), -- DWords 11, 10, 9, 8
+               x"00010001" & to_stl(NvmeQueueNum-1, 16) & x"0001" & zeros(64), -- DWords 11, 10, 9, 8
+               zeros(128),                                                     -- DWords 15, 14, 13, 12
+
+       -- Notify queue entry to Nvme
+       setHeader(1, 16#1000#, 1, 0), to_stl(2, 128),
+       
+       -- Wait for reply in queue, how to do this ???
+       
+       -- Create DataRead reply queue (8 entries)  by sending 64byte request to Admin queue
+       setHeader(12, 16#02000000#, 16, 0),
+               zeros(96) & x"02000005",                                        -- Dwords 3, 2, 1, 0
+               zeros(32) & x"02120000" & zeros(64),                            -- DWords 7, 6, 5, 4
+               x"00000001" & to_stl(NvmeQueueNum-1, 16) & x"0002" & zeros(64), -- DWords 11, 10, 9, 8
+               zeros(128),                                                     -- DWords 15, 14, 13, 12
+
+       -- Notify queue entry to Nvme
+       setHeader(1, 16#1000#, 1, 0), to_stl(1, 128),
+       
+       -- Wait for reply in queue, how to do this ???
+
+       -- Create DataRead request queue by sending 64byte request to Admin queue
+       setHeader(12, 16#02000000#, 16, 0),
+               zeros(96) & x"02000001",                                        -- Dwords 3, 2, 1, 0
+               zeros(32) & x"02020000" & zeros(64),                            -- DWords 7, 6, 5, 4
+               x"00020001" & to_stl(NvmeQueueNum-1, 16) & x"0002" & zeros(64), -- DWords 11, 10, 9, 8
                zeros(128),                                                     -- DWords 15, 14, 13, 12
 
        -- Notify queue entry to Nvme
        setHeader(1, 16#1000#, 1, 0), to_stl(2, 128),
        
        -- Wait for reply in queue, how to do this ???
+       
 
        -- Start controller
        setHeader(1, 16#0014#, 1, 0), to_stl(x"00460001", 128),
index 4543c6ff47626a47b6e28881e6f7281b487a1754..00fd25713da3870e16548d27d5f4142a4b6c3ba8 100644 (file)
@@ -81,6 +81,7 @@ signal dataSize               : RegisterType := (others => '0');      --! The data chunk size in b
 signal error           : RegisterType := (others => '0');      --! The system errors status
 
 signal enabled         : std_logic := '0';                                     --! Read is enabled
+signal complete                : std_logic := '0';                                     --! Read is complete
 signal numBlocksProc   : unsigned(31 downto 0) := (others => '0');             --! Number of block write requests sent
 signal numBlocksDone   : unsigned(31 downto 0) := (others => '0');             --! Number of block write completions received
 
@@ -91,6 +92,11 @@ begin
        return to_stl(set_PcieRequestHeadType(3, request, address, count, tag));
 end function;
 
+function pcieAddress(blocknum: unsigned) return std_logic_vector is
+begin
+       return x"01F" & to_stl(blocknum(19 - log2(BlockSize) downto 0)) & zeros(log2(BlockSize));
+end;
+
 begin
        -- Register access
        regDataOut      <= std_logic_vector(control) when(regAddress = 0)
@@ -100,8 +106,10 @@ begin
                        else std_logic_vector(error) when(regAddress = 4)
                        else ones(32);
        
-       enabled <= control(0);
-       status  <= (others => '0');
+       enabled                 <= control(0);
+       status(0)               <= enabled;
+       status(1)               <= complete;
+       status(31 downto 2)     <= (others => '0');
        
        -- Register process
        process(clk)
@@ -133,6 +141,7 @@ begin
                                requestOut.last         <= '0';
                                requestOut.keep         <= (others => '1');
                                numBlocksProc           <= (others => '0');
+                               complete                <= '0';
                                state                   <= STATE_IDLE;
                        else
                                case(state) is
@@ -149,6 +158,7 @@ begin
                                when STATE_RUN =>
                                        if(enabled = '1') then
                                                if(numBlocksProc >= dataSize) then
+                                                       complete <= '1';
                                                        state <= STATE_COMPLETE;
                                                
                                                else
@@ -157,11 +167,13 @@ begin
                                                        state                   <= STATE_QUEUE_HEAD;
                                                end if;
                                        else
+                                               complete <= '1';
                                                state <= STATE_COMPLETE;
                                        end if;
                                
                                when STATE_COMPLETE =>
                                        if(enabled = '0') then
+                                               complete <= '0';
                                                state <= STATE_IDLE;
                                        end if;
 
@@ -173,7 +185,7 @@ begin
 
                                when STATE_QUEUE_0 =>
                                        if(requestOut.valid = '1' and requestOut.ready = '1') then
-                                               requestOut.data <= zeros(32) & x"01F00000" & zeros(64); -- Data source address to host
+                                               requestOut.data <= zeros(32) & pcieAddress(numBlocksProc) & zeros(64);  -- Data source address to host
                                                state           <= STATE_QUEUE_1;
                                        end if;
 
index 52a84a797d2a0b537c4637b1a547785a79d2dc0a..d33110b4b51d0d5f88f0503613040feb46d4be7a 100644 (file)
@@ -103,7 +103,7 @@ signal queueReadOut         : integer range 0 to NumQueue-1 := 0;
 type StateType                 is (STATE_IDLE, STATE_READ_QUEUE_START, STATE_READ_QUEUE,
                                        STATE_QUEUE_REPLY_HEAD, STATE_QUEUE_REPLY_DATA,
                                        STATE_READ_DATA_START, STATE_READ_DATA_RECV_START, STATE_READ_DATA_RECV,
-                                       STATE_WRITE_DATA_START, STATE_WRITE_DATA_PACKET_START, STATE_WRITE_DATA,
+                                       STATE_WRITE_DATA_START, STATE_WRITE_DATA_HEAD, STATE_WRITE_DATA,
                                        STATE_REPLY_QUEUE);
 type QueueRequestType          is array(0 to 15) of std_logic_vector(31 downto 0);
 
@@ -122,6 +122,7 @@ signal queueRequestPos              : integer := 0;
 signal waitingForReply         : std_logic := '0';
 
 signal data                    : std_logic_vector(127 downto 0);
+signal readData                        : unsigned(127 downto 0);
 
 function queueNext(pos: integer) return integer is
 begin
@@ -152,6 +153,7 @@ begin
 
 
        nvmeReq.data            <= zeros(16)  & queueRequest(0)(31 downto 16) & zeros(96) when(state = STATE_QUEUE_REPLY_DATA)
+                                       else to_stl(readData) when(state = STATE_WRITE_DATA)
                                        else to_stl(nvmeRequestHead);
        nvmeReply1Head          <= to_PcieReplyHeadType(nvmeReply1.data);
 
@@ -366,7 +368,7 @@ begin
                                        nvmeRequestHead.tag     <= x"44";
                                        nvmeRequestHead.request <= "0000";
                                        nvmeRequestHead.count   <= to_unsigned(NumWordsRead, nvmeRequestHead.count'length);                             -- Test size of 32 DWords
-                                       
+
                                        if(nvmeReq.valid = '1' and nvmeReq.ready = '1') then
                                                count           <= nvmeRequestHead.count;       -- Note ignoring 1 DWord in first 128 bits
                                                nvmeReq.last    <= '0';
@@ -399,52 +401,64 @@ begin
                                                                state           <= STATE_READ_DATA_RECV_START;
                                                        end if;
                                                end if;
-                                               count <= count - 4;
-                                               chunkCount <= chunkCount - 4;
+
+                                               count           <= count - 4;
+                                               chunkCount      <= chunkCount - 4;
                                        end if;
 
 
                                when STATE_WRITE_DATA_START =>
                                        -- Perform bus master write request for data to write to NVMe
+                                       -- Initialise the header
                                        nvmeRequestHead.address <= unsigned(queueRequest(6));
-                                       --nvmeRequestHead.address       <= to_unsigned(16#05000000#, nvmeRequestHead.address'length);
                                        nvmeRequestHead.tag     <= x"44";
                                        nvmeRequestHead.request <= "0001";
-                                       nvmeRequestHead.count   <= to_unsigned(NumWordsRead, nvmeRequestHead.count'length);                             -- Test size of 32 DWords
+
+                                       count           <= to_unsigned(NumWordsRead, count'length);     -- Note hard coded length of 1 block
+                                       readData        <= (others => '0');
+                                       waitingForReply <= '0';
+                                       state           <= STATE_WRITE_DATA_HEAD;
+
+                               when STATE_WRITE_DATA_HEAD =>
+                                       -- Send the updated header
+
+                                       if(count > PcieMaxPayloadSize) then
+                                               nvmeRequestHead.count   <= to_unsigned(PcieMaxPayloadSize, nvmeRequestHead.count'length);
+                                               chunkCount              <= to_unsigned(PcieMaxPayloadSize, chunkCount'length);
+                                       else
+                                               nvmeRequestHead.count   <= count;
+                                               chunkCount              <= count;
+                                       end if;
                                        
                                        if(nvmeReq.valid = '1' and nvmeReq.ready = '1') then
-                                               count           <= nvmeRequestHead.count;       -- Note ignoring 1 DWord in first 128 bits
                                                nvmeReq.last    <= '0';
-                                               nvmeReq.valid   <= '0';
-                                               nvmeReply1.ready <= '1';
-                                               waitingForReply <= '0';
-                                               state           <= STATE_WRITE_DATA_PACKET_START;
+                                               state           <= STATE_WRITE_DATA;
                                        else
                                                nvmeReq.keep    <= ones(nvmeReq.keep'length);
                                                nvmeReq.last    <= '0';
                                                nvmeReq.valid   <= '1';
                                        end if;
 
-                               when STATE_WRITE_DATA_PACKET_START =>
-                                       -- Write random data
-                                       if(nvmeReply1.valid = '1' and nvmeReply1.ready = '1') then
-                                               chunkCount      <= nvmeReply1Head.count;
-                                               state           <= STATE_WRITE_DATA;
-                                       end if;
-
                                when STATE_WRITE_DATA =>
                                        -- Read in write data ignoring it
-                                       if(nvmeReply1.valid = '1' and nvmeReply1.ready = '1') then
+                                       if(nvmeReq.valid = '1' and nvmeReq.ready = '1') then
                                                if(chunkCount = 4) then
+                                                       nvmeReq.last    <= '0';
+                                                       nvmeReq.valid   <= '0';
+
                                                        if(count = 4) then
                                                                nvmeReply1.ready<= '0';
                                                                state           <= STATE_REPLY_QUEUE;
                                                        else
-                                                               state           <= STATE_WRITE_DATA_PACKET_START;
+                                                               nvmeRequestHead.address <= nvmeRequestHead.address + (nvmeRequestHead.count * 4);
+                                                               state           <= STATE_WRITE_DATA_HEAD;
                                                        end if;
+                                               elsif(chunkCount = 8) then
+                                                       nvmeReq.last    <= '1';
                                                end if;
-                                               count <= count - 4;
-                                               chunkCount <= chunkCount - 4;
+                                               readData        <= readData + 1;
+                                               count           <= count - 4;
+                                               chunkCount      <= chunkCount - 4;
                                        end if;
 
 
@@ -454,7 +468,7 @@ begin
                                        -- Send reply queue header
                                        -- Writes an entry into the DataWRite reply queue. Simply uses info in that last queued request. So only one request at a time.
                                        -- Note data sent to queue is just the header reapeated so junk data ATM.
-                                       nvmeRequestHead.address <= to_unsigned(16#02100000#, nvmeRequestHead.address'length);
+                                       nvmeRequestHead.address <= x"021" & to_unsigned(queue, 4) & zeros(16);
                                        nvmeRequestHead.tag     <= x"44";
                                        nvmeRequestHead.request <= "0001";
                                        nvmeRequestHead.count   <= to_unsigned(16#0004#, nvmeRequestHead.count'length); -- 16 Byte queue entry
index 572b488b3603171af11759a74c6a677743055b08..9d43f50fc0131e89668f5fca3b2bca50bb79fac3 100644 (file)
@@ -129,7 +129,8 @@ begin
        
        
        -- Multiplex streams. Sets the Nvme number to 1 in the Nvme1 reply streams in appropriate location for request and reply packets
-       nvme1Stream <= '0' when(((muxState = MUX_STATE_START) and (nvme0In.valid = '1')) or (muxState = MUX_STATE_SENDPACKET0)) else '1';
+       --nvme1Stream <= '0' when(((muxState = MUX_STATE_START) and (nvme0In.valid = '1')) or (muxState = MUX_STATE_SENDPACKET0)) else '1';
+       nvme1Stream <= '1' when(((muxState = MUX_STATE_START) and (nvme1In.valid = '1')) or (muxState = MUX_STATE_SENDPACKET1)) else '0';
 
        nvme1StreamData <= nvme1In.data(127 downto 81) & '1' & nvme1In.data(79 downto 0) when((muxState = MUX_STATE_START) and (nvme1In.data(95) = '1'))
                else nvme1In.data(127 downto 32) & x"1" & nvme1In.data(27 downto 0) when((muxState = MUX_STATE_START) and (nvme1In.data(95) = '0'))
@@ -151,13 +152,13 @@ begin
                        else
                                case(muxState) is
                                when MUX_STATE_START =>
-                                       if((nvme0In.valid = '1') and (nvme0In.ready = '1')) then
+                                       if((nvme0In.valid = '1') and (hostOut.ready = '1')) then
                                                if(nvme0In.last = '1') then
                                                        muxState <= MUX_STATE_START;
                                                else
                                                        muxState <= MUX_STATE_SENDPACKET0;
                                                end if;
-                                       elsif((nvme1In.valid = '1') and (nvme1In.ready = '1')) then
+                                       elsif((nvme1In.valid = '1') and (hostOut.ready = '1')) then
                                                if(nvme1In.last = '1') then
                                                        muxState <= MUX_STATE_START;
                                                else
index efdb2cb3a9834de75ddbf1060c27b93d0ac01252..dd780554701a1e381a59d9e919731809c42ad982 100644 (file)
@@ -223,7 +223,7 @@ int Control::configureNvme(){
 
                //dumpNvmeRegisters();
 
-               cmd0 = ((oqueueNum - 1) << 16) | 0x0001;
+               cmd0 = ((oqueueNum - 1) << 16);
 
 #ifdef ZAP
                // Test the queue engine
@@ -233,10 +233,10 @@ int Control::configureNvme(){
                        for(int c = 0; c < 10; c++){
                                printf("Do: %d\n", c);
 
-                               nvmeRequest(0, 0, 0x05, 0x02110000, cmd0, 0x00000001);
+                               nvmeRequest(0, 0, 0x05, 0x02110000, cmd0 | 1, 0x00000001);
                                sleep(1);
 
-                               nvmeRequest(0, 0, 0x04, 0x02110000, cmd0, 0x00000001);
+                               nvmeRequest(0, 0, 0x04, 0x02110000, cmd0 | 1, 0x00000001);
                                sleep(1);
                        }
                }
@@ -244,10 +244,10 @@ int Control::configureNvme(){
                        for(int c = 0; c < 10; c++){
                                printf("Do: %d\n", c);
 
-                               nvmeRequest(0, 0, 0x05, 0x00110000, cmd0, 0x00000001);
+                               nvmeRequest(0, 0, 0x05, 0x00110000, cmd0 | 1, 0x00000001);
                                sleep(1);
 
-                               nvmeRequest(0, 0, 0x04, 0x00110000, cmd0, 0x00000001);
+                               nvmeRequest(0, 0, 0x04, 0x00110000, cmd0 | 1, 0x00000001);
                                sleep(1);
                        }
                }
@@ -259,26 +259,50 @@ int Control::configureNvme(){
                        if(overbose)
                                printf("Create IO queue 1 for replies\n");
 
-                       nvmeRequest(1, 0, 0x05, 0x02110000, cmd0, 0x00000001);
+                       nvmeRequest(1, 0, 0x05, 0x02110000, cmd0 | 1, 0x00000001);
 
                        // Create an IO queue
                        if(overbose)
                                printf("Create IO queue 1 for requests\n");
 
-                       nvmeRequest(1, 0, 0x01, 0x02010000, cmd0, 0x00010001);
+                       nvmeRequest(1, 0, 0x01, 0x02010000, cmd0 | 1, 0x00010001);
+
+                       // Create an IO queue
+                       if(overbose)
+                               printf("Create IO queue 2 for replies\n");
+
+                       nvmeRequest(1, 0, 0x05, 0x02120000, cmd0 | 2, 0x00000001);
+
+                       // Create an IO queue
+                       if(overbose)
+                               printf("Create IO queue 1 for requests\n");
+
+                       nvmeRequest(1, 0, 0x01, 0x02020000, cmd0 | 2, 0x00020001);
                }
                else {
                        // Create an IO queue
                        if(overbose)
                                printf("Create IO queue 1 for replies\n");
 
-                       nvmeRequest(1, 0, 0x05, 0x01110000, cmd0, 0x00000001);
+                       nvmeRequest(1, 0, 0x05, 0x01110000, cmd0 | 1, 0x00000001);
 
                        // Create an IO queue
                        if(overbose)
                                printf("Create IO queue 1 for requests\n");
 
-                       nvmeRequest(1, 0, 0x01, 0x01010000, cmd0, 0x00010001);
+                       nvmeRequest(1, 0, 0x01, 0x01010000, cmd0 | 1, 0x00010001);
+
+                       // Create an IO queue
+                       if(overbose)
+                               printf("Create IO queue 2 for replies\n");
+
+                       nvmeRequest(1, 0, 0x05, 0x01120000, cmd0 | 2, 0x00000001);
+
+                       // Create an IO queue
+                       if(overbose)
+                               printf("Create IO queue 2 for requests\n");
+
+                       nvmeRequest(1, 0, 0x01, 0x01020000, cmd0 | 2, 0x00020001);
                }
        }
 #endif
@@ -332,6 +356,16 @@ int Control::test4(){
        printf("Perform block read\n");
        memset(odataBlockMem, 0x01, sizeof(odataBlockMem));
 
+#ifndef ZAP
+       // Test read of a single 512 byte block
+       numBlocks = 1;
+       nvmeRequest(1, 1, 0x02, 0x01800000, block, 0x00000000, numBlocks-1);    // Perform read
+
+       printf("DataBlock0:\n");
+       bhd32a(odataBlockMem, numBlocks*512/4);
+       return 0;
+#endif
+
        nvmeRequest(1, 1, 0x02, 0x01800000, block, 0x00000000, numBlocks-1);    // Perform read
 
        printf("DataBlock0:\n");
@@ -590,26 +624,18 @@ int Control::test10(){
        BUInt32 t;
        double  r;
        double  ts;
-       BUInt   numBlocks = 1;                  // 1 GByte
+       BUInt   numBlocks = 2;                  // 
        //BUInt numBlocks = 262144;             // 1 GByte
        //BUInt numBlocks = 2621440;            // 10 GByte
 
        //numBlocks = 8;
        //numBlocks = 2621440;          // 10 GByte
        
-       printf("Test10: Read 1 block using NvmeRead functionality\n");
-
-       setNvme(0);
-       if(e = configureNvme())
-               return e;
+       printf("Test10: Read blocks using NvmeRead functionality\n");
 
-       setNvme(1);
        if(e = configureNvme())
                return e;
 
-       //setNvme(2);
-       setNvme(0);
-
        //dumpRegs();
        
        // Set number of blocks to write