Added initial NvmeWrite functionality.
authorTerry Barnaby <terry.barnaby@beam.beam.ltd.uk>
Wed, 29 Apr 2020 08:40:13 +0000 (09:40 +0100)
committerTerry Barnaby <terry.barnaby@beam.beam.ltd.uk>
Wed, 29 Apr 2020 08:40:13 +0000 (09:40 +0100)
Many changes to the system including changing the stream numbers and addresses of things.
This code will perform FPGA driven writes to the Nvme (3 x 512 Byte blocks).

28 files changed:
docsrc/DuneNvmeStorageDesign.odt
docsrc/DuneNvmeStorageManual.odt
source/DuneNvme/sim/Makefile
source/DuneNvme/sim/testbench/TestPkg.vhd
source/DuneNvme/sim/testbench/test011-switch.sav
source/DuneNvme/sim/testbench/test011-switch.vhd
source/DuneNvme/sim/testbench/test016-fifo.sav [new file with mode: 0644]
source/DuneNvme/sim/testbench/test016-fifo.vhd [new file with mode: 0644]
source/DuneNvme/sim/testbench/test017-write.sav [new file with mode: 0644]
source/DuneNvme/sim/testbench/test017-write.vhd [new file with mode: 0644]
source/DuneNvme/src/DataFifo.vhd
source/DuneNvme/src/DuneNvmeTestTop.vhd
source/DuneNvme/src/NvmeConfig.vhd
source/DuneNvme/src/NvmeQueues.vhd
source/DuneNvme/src/NvmeSim.vhd
source/DuneNvme/src/NvmeStorageIntPkg.vhd
source/DuneNvme/src/NvmeStorageUnit.vhd
source/DuneNvme/src/NvmeWrite.vhd
source/DuneNvme/src/StreamSwitch.vhd
source/DuneNvme/src/TestData.vhd
source/DuneNvme/src/ip/Fifo32k.xci [new file with mode: 0644]
source/DuneNvme/src/ip/Fifo4k.xci [new file with mode: 0644]
source/DuneNvme/test/NvmeAccess.cpp
source/DuneNvme/test/NvmeAccess.h
source/DuneNvme/test/pciregs.txt [new file with mode: 0644]
source/DuneNvme/test/test_nvme.cpp
source/DuneNvme/vivado/Makefile
source/DuneNvme/vivado/Vivado.mk

index 5181c05113cf58c85263f8f54c5e42aa2c95faae..c72221bfe1151c348cf607c48b35ad35f2295d90 100644 (file)
Binary files a/docsrc/DuneNvmeStorageDesign.odt and b/docsrc/DuneNvmeStorageDesign.odt differ
index ccbb41b2cd6508df37c5d08b14b15cb2b5bc606b..58eccee755de90e70668675daeb871db3285c0db 100644 (file)
Binary files a/docsrc/DuneNvmeStorageManual.odt and b/docsrc/DuneNvmeStorageManual.odt differ
index 9ba196d324bb3882491d1c53deaa8fa9394d4628..94bc5b029455d2ae53e4b07cded8636bf4b15e75 100644 (file)
 #TEST  = test012-hostnvme
 #TEST  = test013-hostnvme
 #TEST  = test014-queueram
-TEST   = test015-hostnvme
+#TEST  = test015-hostnvme
+#TEST  = test016-fifo
+TEST   = test017-write
 
 # VHDL source files
 FILES_BASE     += testbench/TestPkg.vhd ../src/NvmeStoragePkg.vhd ../src/NvmeStorageIntPkg.vhd ../src/AxilClockConverter.vhd ../src/AxisClockConverter.vhd 
 FILES_BASE     += ../src/NvmeStreamMux.vhd
+FILES_BASE     += ../vivado/nvme-test.srcs/sources_1/ip/Fifo4k/Fifo4k_sim_netlist.vhdl
+FILES_BASE     += ../vivado/nvme-test.srcs/sources_1/ip/Fifo32k/Fifo32k_sim_netlist.vhdl
 FILES_SYSTEM   = ../src/NvmeStorageUnit.vhd ../src/NvmeSim.vhd ../src/NvmeConfig.vhd ../src/StreamSwitch.vhd ../src/NvmeQueues.vhd
+FILES_SYSTEM   += ../src/TestData.vhd ../src/DataFifo.vhd ../src/NvmeWrite.vhd
 
 # Test files
 FILES_test001-leds += testbench/${TEST}.vhd ${FILES_BASE} ../src/LedCount.vhd
@@ -43,6 +48,8 @@ FILES_test012-hostnvme += testbench/${TEST}.vhd ${FILES_BASE} ${FILES_SYSTEM}
 FILES_test013-hostnvme += testbench/${TEST}.vhd ${FILES_BASE} ${FILES_SYSTEM}
 FILES_test014-queueram += testbench/${TEST}.vhd ${FILES_BASE}  ../src/NvmeQueues.vhd
 FILES_test015-hostnvme += testbench/${TEST}.vhd ${FILES_BASE} ${FILES_SYSTEM}
+FILES_test016-fifo += testbench/${TEST}.vhd ${FILES_BASE} ${FILES_SYSTEM}
+FILES_test017-write += testbench/${TEST}.vhd ${FILES_BASE} ${FILES_SYSTEM}
 
 # VHDL testbench files
 STOP   = test
index 2898c636c32783eebe6dbc745a3403ad327deb01..926eaf72c3a40671cda3ec76c23b2d76c392d91c 100644 (file)
@@ -39,6 +39,7 @@ package TestPkg is
        procedure pcieRequestRead(signal clk: std_logic; signal stream: inout AxisStreamType; requesterId: in integer; request: in integer; address: in integer; tag: in integer; count: in integer);
        procedure pcieReply(signal clk: std_logic; signal stream: inout AxisStreamType; requesterId: in integer; status: in integer; address: in integer; tag: in integer; count: in integer; data: in integer);
        procedure busWrite(signal clk: std_logic; signal toSlave: out AxilToSlaveType; signal toMaster: in AxilToMasterType; address: in integer; data: in integer);
+       procedure busRead(signal clk: std_logic; signal toSlave: out AxilToSlaveType; signal toMaster: in AxilToMasterType; address: in integer);
 end;
 
 package body TestPkg is
@@ -157,4 +158,21 @@ package body TestPkg is
                wait until rising_edge(clk) and (toMaster.wready = '1');
                toSlave.wvalid <= '0';
        end procedure;
+
+       procedure busRead(signal clk: std_logic; signal toSlave: out AxilToSlaveType; signal toMaster: in AxilToMasterType; address: in integer) is
+       begin
+               -- Write address
+               wait until rising_edge(clk);
+               toSlave.araddr <= to_AxilAddress(address);
+               toSlave.arvalid <= '1';
+
+               wait until rising_edge(clk) and (toMaster.arready = '1');
+               toSlave.arvalid <= '0';
+
+               -- Read data
+               toSlave.rready <= '1';
+
+               wait until rising_edge(clk) and (toMaster.rvalid = '1');
+               toSlave.rready <= '0';
+       end procedure;
 end;
index 809abdff2715e657edc8b04ef4baf3f4ecd73db2..24cf3f7621b9662c55d82c3a98236e17cd14d4c8 100644 (file)
@@ -1,39 +1,45 @@
 [*]
 [*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI
-[*] Mon Apr 20 16:18:17 2020
+[*] Wed Apr 29 06:25:17 2020
 [*]
-[dumpfile] "/src/dune/FpgaPlay/test016-switch/sim/simu/test.ghw"
-[dumpfile_mtime] "Mon Apr 20 16:18:09 2020"
-[dumpfile_size] 9902
-[savefile] "/src/dune/FpgaPlay/test016-switch/sim/testbench/test011-switch.sav"
+[dumpfile] "/src/dune/FpgaPlay/test020-nvmeprocess/sim/simu/test.ghw"
+[dumpfile_mtime] "Wed Apr 29 06:00:37 2020"
+[dumpfile_size] 9194
+[savefile] "/src/dune/FpgaPlay/test020-nvmeprocess/sim/testbench/test011-switch.sav"
 [timestart] 0
 [size] 1920 1171
 [pos] -1 -1
-*-26.416382 29500000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+*-26.416382 310700000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
 [treeopen] top.
 [treeopen] top.test.
 [treeopen] top.test.streamrecv.
 [treeopen] top.test.streamrecv.[0].
 [treeopen] top.test.streamrecv.[1].
+[treeopen] top.test.streamrecv.[2].
 [treeopen] top.test.streamsend.
 [treeopen] top.test.streamsend.[0].
 [treeopen] top.test.streamsend.[1].
+[treeopen] top.test.streamsend.[2].
 [treeopen] top.test.streamswitch0.
 [treeopen] top.test.streamswitch0.streamin.
 [treeopen] top.test.streamswitch0.streamin.[0].
 [treeopen] top.test.streamswitch0.streamout.[1].
 [treeopen] top.test.streamswitch0.streamout.[2].
-[treeopen] top.test.streamswitch0.switchrequest.
 [sst_width] 235
 [signals_width] 675
 [sst_expanded] 1
-[sst_vpaned_height] 342
+[sst_vpaned_height] 623
 @28
 top.test.clk
 top.test.reset
-@420
+@800200
+-StreamSwitch
+@421
+top.test.streamswitch0.switchstate
 top.test.streamswitch0.switchin
 top.test.streamswitch0.switchout
+@1000200
+-StreamSwitch
 @28
 top.test.streamsend[0].ready
 top.test.streamsend[0].valid
@@ -47,18 +53,28 @@ top.test.streamrecv[0].last
 @22
 #{top.test.streamrecv[0].data[127:0]} top.test.streamrecv[0].data[127] top.test.streamrecv[0].data[126] top.test.streamrecv[0].data[125] top.test.streamrecv[0].data[124] top.test.streamrecv[0].data[123] top.test.streamrecv[0].data[122] top.test.streamrecv[0].data[121] top.test.streamrecv[0].data[120] top.test.streamrecv[0].data[119] top.test.streamrecv[0].data[118] top.test.streamrecv[0].data[117] top.test.streamrecv[0].data[116] top.test.streamrecv[0].data[115] top.test.streamrecv[0].data[114] top.test.streamrecv[0].data[113] top.test.streamrecv[0].data[112] top.test.streamrecv[0].data[111] top.test.streamrecv[0].data[110] top.test.streamrecv[0].data[109] top.test.streamrecv[0].data[108] top.test.streamrecv[0].data[107] top.test.streamrecv[0].data[106] top.test.streamrecv[0].data[105] top.test.streamrecv[0].data[104] top.test.streamrecv[0].data[103] top.test.streamrecv[0].data[102] top.test.streamrecv[0].data[101] top.test.streamrecv[0].data[100] top.test.streamrecv[0].data[99] top.test.streamrecv[0].data[98] top.test.streamrecv[0].data[97] top.test.streamrecv[0].data[96] top.test.streamrecv[0].data[95] top.test.streamrecv[0].data[94] top.test.streamrecv[0].data[93] top.test.streamrecv[0].data[92] top.test.streamrecv[0].data[91] top.test.streamrecv[0].data[90] top.test.streamrecv[0].data[89] top.test.streamrecv[0].data[88] top.test.streamrecv[0].data[87] top.test.streamrecv[0].data[86] top.test.streamrecv[0].data[85] top.test.streamrecv[0].data[84] top.test.streamrecv[0].data[83] top.test.streamrecv[0].data[82] top.test.streamrecv[0].data[81] top.test.streamrecv[0].data[80] top.test.streamrecv[0].data[79] top.test.streamrecv[0].data[78] top.test.streamrecv[0].data[77] top.test.streamrecv[0].data[76] top.test.streamrecv[0].data[75] top.test.streamrecv[0].data[74] top.test.streamrecv[0].data[73] top.test.streamrecv[0].data[72] top.test.streamrecv[0].data[71] top.test.streamrecv[0].data[70] top.test.streamrecv[0].data[69] top.test.streamrecv[0].data[68] top.test.streamrecv[0].data[67] top.test.streamrecv[0].data[66] top.test.streamrecv[0].data[65] top.test.streamrecv[0].data[64] top.test.streamrecv[0].data[63] top.test.streamrecv[0].data[62] top.test.streamrecv[0].data[61] top.test.streamrecv[0].data[60] top.test.streamrecv[0].data[59] top.test.streamrecv[0].data[58] top.test.streamrecv[0].data[57] top.test.streamrecv[0].data[56] top.test.streamrecv[0].data[55] top.test.streamrecv[0].data[54] top.test.streamrecv[0].data[53] top.test.streamrecv[0].data[52] top.test.streamrecv[0].data[51] top.test.streamrecv[0].data[50] top.test.streamrecv[0].data[49] top.test.streamrecv[0].data[48] top.test.streamrecv[0].data[47] top.test.streamrecv[0].data[46] top.test.streamrecv[0].data[45] top.test.streamrecv[0].data[44] top.test.streamrecv[0].data[43] top.test.streamrecv[0].data[42] top.test.streamrecv[0].data[41] top.test.streamrecv[0].data[40] top.test.streamrecv[0].data[39] top.test.streamrecv[0].data[38] top.test.streamrecv[0].data[37] top.test.streamrecv[0].data[36] top.test.streamrecv[0].data[35] top.test.streamrecv[0].data[34] top.test.streamrecv[0].data[33] top.test.streamrecv[0].data[32] top.test.streamrecv[0].data[31] top.test.streamrecv[0].data[30] top.test.streamrecv[0].data[29] top.test.streamrecv[0].data[28] top.test.streamrecv[0].data[27] top.test.streamrecv[0].data[26] top.test.streamrecv[0].data[25] top.test.streamrecv[0].data[24] top.test.streamrecv[0].data[23] top.test.streamrecv[0].data[22] top.test.streamrecv[0].data[21] top.test.streamrecv[0].data[20] top.test.streamrecv[0].data[19] top.test.streamrecv[0].data[18] top.test.streamrecv[0].data[17] top.test.streamrecv[0].data[16] top.test.streamrecv[0].data[15] top.test.streamrecv[0].data[14] top.test.streamrecv[0].data[13] top.test.streamrecv[0].data[12] top.test.streamrecv[0].data[11] top.test.streamrecv[0].data[10] top.test.streamrecv[0].data[9] top.test.streamrecv[0].data[8] top.test.streamrecv[0].data[7] top.test.streamrecv[0].data[6] top.test.streamrecv[0].data[5] top.test.streamrecv[0].data[4] top.test.streamrecv[0].data[3] top.test.streamrecv[0].data[2] top.test.streamrecv[0].data[1] top.test.streamrecv[0].data[0]
 @28
+top.test.streamsend[1].ready
+top.test.streamsend[1].valid
+top.test.streamsend[1].last
+@22
+#{top.test.streamsend[1].data[127:0]} top.test.streamsend[1].data[127] top.test.streamsend[1].data[126] top.test.streamsend[1].data[125] top.test.streamsend[1].data[124] top.test.streamsend[1].data[123] top.test.streamsend[1].data[122] top.test.streamsend[1].data[121] top.test.streamsend[1].data[120] top.test.streamsend[1].data[119] top.test.streamsend[1].data[118] top.test.streamsend[1].data[117] top.test.streamsend[1].data[116] top.test.streamsend[1].data[115] top.test.streamsend[1].data[114] top.test.streamsend[1].data[113] top.test.streamsend[1].data[112] top.test.streamsend[1].data[111] top.test.streamsend[1].data[110] top.test.streamsend[1].data[109] top.test.streamsend[1].data[108] top.test.streamsend[1].data[107] top.test.streamsend[1].data[106] top.test.streamsend[1].data[105] top.test.streamsend[1].data[104] top.test.streamsend[1].data[103] top.test.streamsend[1].data[102] top.test.streamsend[1].data[101] top.test.streamsend[1].data[100] top.test.streamsend[1].data[99] top.test.streamsend[1].data[98] top.test.streamsend[1].data[97] top.test.streamsend[1].data[96] top.test.streamsend[1].data[95] top.test.streamsend[1].data[94] top.test.streamsend[1].data[93] top.test.streamsend[1].data[92] top.test.streamsend[1].data[91] top.test.streamsend[1].data[90] top.test.streamsend[1].data[89] top.test.streamsend[1].data[88] top.test.streamsend[1].data[87] top.test.streamsend[1].data[86] top.test.streamsend[1].data[85] top.test.streamsend[1].data[84] top.test.streamsend[1].data[83] top.test.streamsend[1].data[82] top.test.streamsend[1].data[81] top.test.streamsend[1].data[80] top.test.streamsend[1].data[79] top.test.streamsend[1].data[78] top.test.streamsend[1].data[77] top.test.streamsend[1].data[76] top.test.streamsend[1].data[75] top.test.streamsend[1].data[74] top.test.streamsend[1].data[73] top.test.streamsend[1].data[72] top.test.streamsend[1].data[71] top.test.streamsend[1].data[70] top.test.streamsend[1].data[69] top.test.streamsend[1].data[68] top.test.streamsend[1].data[67] top.test.streamsend[1].data[66] top.test.streamsend[1].data[65] top.test.streamsend[1].data[64] top.test.streamsend[1].data[63] top.test.streamsend[1].data[62] top.test.streamsend[1].data[61] top.test.streamsend[1].data[60] top.test.streamsend[1].data[59] top.test.streamsend[1].data[58] top.test.streamsend[1].data[57] top.test.streamsend[1].data[56] top.test.streamsend[1].data[55] top.test.streamsend[1].data[54] top.test.streamsend[1].data[53] top.test.streamsend[1].data[52] top.test.streamsend[1].data[51] top.test.streamsend[1].data[50] top.test.streamsend[1].data[49] top.test.streamsend[1].data[48] top.test.streamsend[1].data[47] top.test.streamsend[1].data[46] top.test.streamsend[1].data[45] top.test.streamsend[1].data[44] top.test.streamsend[1].data[43] top.test.streamsend[1].data[42] top.test.streamsend[1].data[41] top.test.streamsend[1].data[40] top.test.streamsend[1].data[39] top.test.streamsend[1].data[38] top.test.streamsend[1].data[37] top.test.streamsend[1].data[36] top.test.streamsend[1].data[35] top.test.streamsend[1].data[34] top.test.streamsend[1].data[33] top.test.streamsend[1].data[32] top.test.streamsend[1].data[31] top.test.streamsend[1].data[30] top.test.streamsend[1].data[29] top.test.streamsend[1].data[28] top.test.streamsend[1].data[27] top.test.streamsend[1].data[26] top.test.streamsend[1].data[25] top.test.streamsend[1].data[24] top.test.streamsend[1].data[23] top.test.streamsend[1].data[22] top.test.streamsend[1].data[21] top.test.streamsend[1].data[20] top.test.streamsend[1].data[19] top.test.streamsend[1].data[18] top.test.streamsend[1].data[17] top.test.streamsend[1].data[16] top.test.streamsend[1].data[15] top.test.streamsend[1].data[14] top.test.streamsend[1].data[13] top.test.streamsend[1].data[12] top.test.streamsend[1].data[11] top.test.streamsend[1].data[10] top.test.streamsend[1].data[9] top.test.streamsend[1].data[8] top.test.streamsend[1].data[7] top.test.streamsend[1].data[6] top.test.streamsend[1].data[5] top.test.streamsend[1].data[4] top.test.streamsend[1].data[3] top.test.streamsend[1].data[2] top.test.streamsend[1].data[1] top.test.streamsend[1].data[0]
+@28
 top.test.streamrecv[1].ready
 top.test.streamrecv[1].valid
 top.test.streamrecv[1].last
-@23
-#{top.test.streamrecv[1].keep[15:0]} top.test.streamrecv[1].keep[15] top.test.streamrecv[1].keep[14] top.test.streamrecv[1].keep[13] top.test.streamrecv[1].keep[12] top.test.streamrecv[1].keep[11] top.test.streamrecv[1].keep[10] top.test.streamrecv[1].keep[9] top.test.streamrecv[1].keep[8] top.test.streamrecv[1].keep[7] top.test.streamrecv[1].keep[6] top.test.streamrecv[1].keep[5] top.test.streamrecv[1].keep[4] top.test.streamrecv[1].keep[3] top.test.streamrecv[1].keep[2] top.test.streamrecv[1].keep[1] top.test.streamrecv[1].keep[0]
 @22
 #{top.test.streamrecv[1].data[127:0]} top.test.streamrecv[1].data[127] top.test.streamrecv[1].data[126] top.test.streamrecv[1].data[125] top.test.streamrecv[1].data[124] top.test.streamrecv[1].data[123] top.test.streamrecv[1].data[122] top.test.streamrecv[1].data[121] top.test.streamrecv[1].data[120] top.test.streamrecv[1].data[119] top.test.streamrecv[1].data[118] top.test.streamrecv[1].data[117] top.test.streamrecv[1].data[116] top.test.streamrecv[1].data[115] top.test.streamrecv[1].data[114] top.test.streamrecv[1].data[113] top.test.streamrecv[1].data[112] top.test.streamrecv[1].data[111] top.test.streamrecv[1].data[110] top.test.streamrecv[1].data[109] top.test.streamrecv[1].data[108] top.test.streamrecv[1].data[107] top.test.streamrecv[1].data[106] top.test.streamrecv[1].data[105] top.test.streamrecv[1].data[104] top.test.streamrecv[1].data[103] top.test.streamrecv[1].data[102] top.test.streamrecv[1].data[101] top.test.streamrecv[1].data[100] top.test.streamrecv[1].data[99] top.test.streamrecv[1].data[98] top.test.streamrecv[1].data[97] top.test.streamrecv[1].data[96] top.test.streamrecv[1].data[95] top.test.streamrecv[1].data[94] top.test.streamrecv[1].data[93] top.test.streamrecv[1].data[92] top.test.streamrecv[1].data[91] top.test.streamrecv[1].data[90] top.test.streamrecv[1].data[89] top.test.streamrecv[1].data[88] top.test.streamrecv[1].data[87] top.test.streamrecv[1].data[86] top.test.streamrecv[1].data[85] top.test.streamrecv[1].data[84] top.test.streamrecv[1].data[83] top.test.streamrecv[1].data[82] top.test.streamrecv[1].data[81] top.test.streamrecv[1].data[80] top.test.streamrecv[1].data[79] top.test.streamrecv[1].data[78] top.test.streamrecv[1].data[77] top.test.streamrecv[1].data[76] top.test.streamrecv[1].data[75] top.test.streamrecv[1].data[74] top.test.streamrecv[1].data[73] top.test.streamrecv[1].data[72] top.test.streamrecv[1].data[71] top.test.streamrecv[1].data[70] top.test.streamrecv[1].data[69] top.test.streamrecv[1].data[68] top.test.streamrecv[1].data[67] top.test.streamrecv[1].data[66] top.test.streamrecv[1].data[65] top.test.streamrecv[1].data[64] top.test.streamrecv[1].data[63] top.test.streamrecv[1].data[62] top.test.streamrecv[1].data[61] top.test.streamrecv[1].data[60] top.test.streamrecv[1].data[59] top.test.streamrecv[1].data[58] top.test.streamrecv[1].data[57] top.test.streamrecv[1].data[56] top.test.streamrecv[1].data[55] top.test.streamrecv[1].data[54] top.test.streamrecv[1].data[53] top.test.streamrecv[1].data[52] top.test.streamrecv[1].data[51] top.test.streamrecv[1].data[50] top.test.streamrecv[1].data[49] top.test.streamrecv[1].data[48] top.test.streamrecv[1].data[47] top.test.streamrecv[1].data[46] top.test.streamrecv[1].data[45] top.test.streamrecv[1].data[44] top.test.streamrecv[1].data[43] top.test.streamrecv[1].data[42] top.test.streamrecv[1].data[41] top.test.streamrecv[1].data[40] top.test.streamrecv[1].data[39] top.test.streamrecv[1].data[38] top.test.streamrecv[1].data[37] top.test.streamrecv[1].data[36] top.test.streamrecv[1].data[35] top.test.streamrecv[1].data[34] top.test.streamrecv[1].data[33] top.test.streamrecv[1].data[32] top.test.streamrecv[1].data[31] top.test.streamrecv[1].data[30] top.test.streamrecv[1].data[29] top.test.streamrecv[1].data[28] top.test.streamrecv[1].data[27] top.test.streamrecv[1].data[26] top.test.streamrecv[1].data[25] top.test.streamrecv[1].data[24] top.test.streamrecv[1].data[23] top.test.streamrecv[1].data[22] top.test.streamrecv[1].data[21] top.test.streamrecv[1].data[20] top.test.streamrecv[1].data[19] top.test.streamrecv[1].data[18] top.test.streamrecv[1].data[17] top.test.streamrecv[1].data[16] top.test.streamrecv[1].data[15] top.test.streamrecv[1].data[14] top.test.streamrecv[1].data[13] top.test.streamrecv[1].data[12] top.test.streamrecv[1].data[11] top.test.streamrecv[1].data[10] top.test.streamrecv[1].data[9] top.test.streamrecv[1].data[8] top.test.streamrecv[1].data[7] top.test.streamrecv[1].data[6] top.test.streamrecv[1].data[5] top.test.streamrecv[1].data[4] top.test.streamrecv[1].data[3] top.test.streamrecv[1].data[2] top.test.streamrecv[1].data[1] top.test.streamrecv[1].data[0]
 @28
-top.test.streamswitch0.streamout[2].ready
-top.test.streamswitch0.streamout[2].valid
-top.test.streamswitch0.streamout[2].last
+top.test.streamsend[2].ready
+top.test.streamsend[2].valid
+top.test.streamsend[2].last
+@22
+#{top.test.streamsend[2].data[127:0]} top.test.streamsend[2].data[127] top.test.streamsend[2].data[126] top.test.streamsend[2].data[125] top.test.streamsend[2].data[124] top.test.streamsend[2].data[123] top.test.streamsend[2].data[122] top.test.streamsend[2].data[121] top.test.streamsend[2].data[120] top.test.streamsend[2].data[119] top.test.streamsend[2].data[118] top.test.streamsend[2].data[117] top.test.streamsend[2].data[116] top.test.streamsend[2].data[115] top.test.streamsend[2].data[114] top.test.streamsend[2].data[113] top.test.streamsend[2].data[112] top.test.streamsend[2].data[111] top.test.streamsend[2].data[110] top.test.streamsend[2].data[109] top.test.streamsend[2].data[108] top.test.streamsend[2].data[107] top.test.streamsend[2].data[106] top.test.streamsend[2].data[105] top.test.streamsend[2].data[104] top.test.streamsend[2].data[103] top.test.streamsend[2].data[102] top.test.streamsend[2].data[101] top.test.streamsend[2].data[100] top.test.streamsend[2].data[99] top.test.streamsend[2].data[98] top.test.streamsend[2].data[97] top.test.streamsend[2].data[96] top.test.streamsend[2].data[95] top.test.streamsend[2].data[94] top.test.streamsend[2].data[93] top.test.streamsend[2].data[92] top.test.streamsend[2].data[91] top.test.streamsend[2].data[90] top.test.streamsend[2].data[89] top.test.streamsend[2].data[88] top.test.streamsend[2].data[87] top.test.streamsend[2].data[86] top.test.streamsend[2].data[85] top.test.streamsend[2].data[84] top.test.streamsend[2].data[83] top.test.streamsend[2].data[82] top.test.streamsend[2].data[81] top.test.streamsend[2].data[80] top.test.streamsend[2].data[79] top.test.streamsend[2].data[78] top.test.streamsend[2].data[77] top.test.streamsend[2].data[76] top.test.streamsend[2].data[75] top.test.streamsend[2].data[74] top.test.streamsend[2].data[73] top.test.streamsend[2].data[72] top.test.streamsend[2].data[71] top.test.streamsend[2].data[70] top.test.streamsend[2].data[69] top.test.streamsend[2].data[68] top.test.streamsend[2].data[67] top.test.streamsend[2].data[66] top.test.streamsend[2].data[65] top.test.streamsend[2].data[64] top.test.streamsend[2].data[63] top.test.streamsend[2].data[62] top.test.streamsend[2].data[61] top.test.streamsend[2].data[60] top.test.streamsend[2].data[59] top.test.streamsend[2].data[58] top.test.streamsend[2].data[57] top.test.streamsend[2].data[56] top.test.streamsend[2].data[55] top.test.streamsend[2].data[54] top.test.streamsend[2].data[53] top.test.streamsend[2].data[52] top.test.streamsend[2].data[51] top.test.streamsend[2].data[50] top.test.streamsend[2].data[49] top.test.streamsend[2].data[48] top.test.streamsend[2].data[47] top.test.streamsend[2].data[46] top.test.streamsend[2].data[45] top.test.streamsend[2].data[44] top.test.streamsend[2].data[43] top.test.streamsend[2].data[42] top.test.streamsend[2].data[41] top.test.streamsend[2].data[40] top.test.streamsend[2].data[39] top.test.streamsend[2].data[38] top.test.streamsend[2].data[37] top.test.streamsend[2].data[36] top.test.streamsend[2].data[35] top.test.streamsend[2].data[34] top.test.streamsend[2].data[33] top.test.streamsend[2].data[32] top.test.streamsend[2].data[31] top.test.streamsend[2].data[30] top.test.streamsend[2].data[29] top.test.streamsend[2].data[28] top.test.streamsend[2].data[27] top.test.streamsend[2].data[26] top.test.streamsend[2].data[25] top.test.streamsend[2].data[24] top.test.streamsend[2].data[23] top.test.streamsend[2].data[22] top.test.streamsend[2].data[21] top.test.streamsend[2].data[20] top.test.streamsend[2].data[19] top.test.streamsend[2].data[18] top.test.streamsend[2].data[17] top.test.streamsend[2].data[16] top.test.streamsend[2].data[15] top.test.streamsend[2].data[14] top.test.streamsend[2].data[13] top.test.streamsend[2].data[12] top.test.streamsend[2].data[11] top.test.streamsend[2].data[10] top.test.streamsend[2].data[9] top.test.streamsend[2].data[8] top.test.streamsend[2].data[7] top.test.streamsend[2].data[6] top.test.streamsend[2].data[5] top.test.streamsend[2].data[4] top.test.streamsend[2].data[3] top.test.streamsend[2].data[2] top.test.streamsend[2].data[1] top.test.streamsend[2].data[0]
+@28
+top.test.streamrecv[2].ready
+top.test.streamrecv[2].valid
+top.test.streamrecv[2].last
 @22
-#{top.test.streamswitch0.streamout[2].data[127:0]} top.test.streamswitch0.streamout[2].data[127] top.test.streamswitch0.streamout[2].data[126] top.test.streamswitch0.streamout[2].data[125] top.test.streamswitch0.streamout[2].data[124] top.test.streamswitch0.streamout[2].data[123] top.test.streamswitch0.streamout[2].data[122] top.test.streamswitch0.streamout[2].data[121] top.test.streamswitch0.streamout[2].data[120] top.test.streamswitch0.streamout[2].data[119] top.test.streamswitch0.streamout[2].data[118] top.test.streamswitch0.streamout[2].data[117] top.test.streamswitch0.streamout[2].data[116] top.test.streamswitch0.streamout[2].data[115] top.test.streamswitch0.streamout[2].data[114] top.test.streamswitch0.streamout[2].data[113] top.test.streamswitch0.streamout[2].data[112] top.test.streamswitch0.streamout[2].data[111] top.test.streamswitch0.streamout[2].data[110] top.test.streamswitch0.streamout[2].data[109] top.test.streamswitch0.streamout[2].data[108] top.test.streamswitch0.streamout[2].data[107] top.test.streamswitch0.streamout[2].data[106] top.test.streamswitch0.streamout[2].data[105] top.test.streamswitch0.streamout[2].data[104] top.test.streamswitch0.streamout[2].data[103] top.test.streamswitch0.streamout[2].data[102] top.test.streamswitch0.streamout[2].data[101] top.test.streamswitch0.streamout[2].data[100] top.test.streamswitch0.streamout[2].data[99] top.test.streamswitch0.streamout[2].data[98] top.test.streamswitch0.streamout[2].data[97] top.test.streamswitch0.streamout[2].data[96] top.test.streamswitch0.streamout[2].data[95] top.test.streamswitch0.streamout[2].data[94] top.test.streamswitch0.streamout[2].data[93] top.test.streamswitch0.streamout[2].data[92] top.test.streamswitch0.streamout[2].data[91] top.test.streamswitch0.streamout[2].data[90] top.test.streamswitch0.streamout[2].data[89] top.test.streamswitch0.streamout[2].data[88] top.test.streamswitch0.streamout[2].data[87] top.test.streamswitch0.streamout[2].data[86] top.test.streamswitch0.streamout[2].data[85] top.test.streamswitch0.streamout[2].data[84] top.test.streamswitch0.streamout[2].data[83] top.test.streamswitch0.streamout[2].data[82] top.test.streamswitch0.streamout[2].data[81] top.test.streamswitch0.streamout[2].data[80] top.test.streamswitch0.streamout[2].data[79] top.test.streamswitch0.streamout[2].data[78] top.test.streamswitch0.streamout[2].data[77] top.test.streamswitch0.streamout[2].data[76] top.test.streamswitch0.streamout[2].data[75] top.test.streamswitch0.streamout[2].data[74] top.test.streamswitch0.streamout[2].data[73] top.test.streamswitch0.streamout[2].data[72] top.test.streamswitch0.streamout[2].data[71] top.test.streamswitch0.streamout[2].data[70] top.test.streamswitch0.streamout[2].data[69] top.test.streamswitch0.streamout[2].data[68] top.test.streamswitch0.streamout[2].data[67] top.test.streamswitch0.streamout[2].data[66] top.test.streamswitch0.streamout[2].data[65] top.test.streamswitch0.streamout[2].data[64] top.test.streamswitch0.streamout[2].data[63] top.test.streamswitch0.streamout[2].data[62] top.test.streamswitch0.streamout[2].data[61] top.test.streamswitch0.streamout[2].data[60] top.test.streamswitch0.streamout[2].data[59] top.test.streamswitch0.streamout[2].data[58] top.test.streamswitch0.streamout[2].data[57] top.test.streamswitch0.streamout[2].data[56] top.test.streamswitch0.streamout[2].data[55] top.test.streamswitch0.streamout[2].data[54] top.test.streamswitch0.streamout[2].data[53] top.test.streamswitch0.streamout[2].data[52] top.test.streamswitch0.streamout[2].data[51] top.test.streamswitch0.streamout[2].data[50] top.test.streamswitch0.streamout[2].data[49] top.test.streamswitch0.streamout[2].data[48] top.test.streamswitch0.streamout[2].data[47] top.test.streamswitch0.streamout[2].data[46] top.test.streamswitch0.streamout[2].data[45] top.test.streamswitch0.streamout[2].data[44] top.test.streamswitch0.streamout[2].data[43] top.test.streamswitch0.streamout[2].data[42] top.test.streamswitch0.streamout[2].data[41] top.test.streamswitch0.streamout[2].data[40] top.test.streamswitch0.streamout[2].data[39] top.test.streamswitch0.streamout[2].data[38] top.test.streamswitch0.streamout[2].data[37] top.test.streamswitch0.streamout[2].data[36] top.test.streamswitch0.streamout[2].data[35] top.test.streamswitch0.streamout[2].data[34] top.test.streamswitch0.streamout[2].data[33] top.test.streamswitch0.streamout[2].data[32] top.test.streamswitch0.streamout[2].data[31] top.test.streamswitch0.streamout[2].data[30] top.test.streamswitch0.streamout[2].data[29] top.test.streamswitch0.streamout[2].data[28] top.test.streamswitch0.streamout[2].data[27] top.test.streamswitch0.streamout[2].data[26] top.test.streamswitch0.streamout[2].data[25] top.test.streamswitch0.streamout[2].data[24] top.test.streamswitch0.streamout[2].data[23] top.test.streamswitch0.streamout[2].data[22] top.test.streamswitch0.streamout[2].data[21] top.test.streamswitch0.streamout[2].data[20] top.test.streamswitch0.streamout[2].data[19] top.test.streamswitch0.streamout[2].data[18] top.test.streamswitch0.streamout[2].data[17] top.test.streamswitch0.streamout[2].data[16] top.test.streamswitch0.streamout[2].data[15] top.test.streamswitch0.streamout[2].data[14] top.test.streamswitch0.streamout[2].data[13] top.test.streamswitch0.streamout[2].data[12] top.test.streamswitch0.streamout[2].data[11] top.test.streamswitch0.streamout[2].data[10] top.test.streamswitch0.streamout[2].data[9] top.test.streamswitch0.streamout[2].data[8] top.test.streamswitch0.streamout[2].data[7] top.test.streamswitch0.streamout[2].data[6] top.test.streamswitch0.streamout[2].data[5] top.test.streamswitch0.streamout[2].data[4] top.test.streamswitch0.streamout[2].data[3] top.test.streamswitch0.streamout[2].data[2] top.test.streamswitch0.streamout[2].data[1] top.test.streamswitch0.streamout[2].data[0]
+#{top.test.streamrecv[2].data[127:0]} top.test.streamrecv[2].data[127] top.test.streamrecv[2].data[126] top.test.streamrecv[2].data[125] top.test.streamrecv[2].data[124] top.test.streamrecv[2].data[123] top.test.streamrecv[2].data[122] top.test.streamrecv[2].data[121] top.test.streamrecv[2].data[120] top.test.streamrecv[2].data[119] top.test.streamrecv[2].data[118] top.test.streamrecv[2].data[117] top.test.streamrecv[2].data[116] top.test.streamrecv[2].data[115] top.test.streamrecv[2].data[114] top.test.streamrecv[2].data[113] top.test.streamrecv[2].data[112] top.test.streamrecv[2].data[111] top.test.streamrecv[2].data[110] top.test.streamrecv[2].data[109] top.test.streamrecv[2].data[108] top.test.streamrecv[2].data[107] top.test.streamrecv[2].data[106] top.test.streamrecv[2].data[105] top.test.streamrecv[2].data[104] top.test.streamrecv[2].data[103] top.test.streamrecv[2].data[102] top.test.streamrecv[2].data[101] top.test.streamrecv[2].data[100] top.test.streamrecv[2].data[99] top.test.streamrecv[2].data[98] top.test.streamrecv[2].data[97] top.test.streamrecv[2].data[96] top.test.streamrecv[2].data[95] top.test.streamrecv[2].data[94] top.test.streamrecv[2].data[93] top.test.streamrecv[2].data[92] top.test.streamrecv[2].data[91] top.test.streamrecv[2].data[90] top.test.streamrecv[2].data[89] top.test.streamrecv[2].data[88] top.test.streamrecv[2].data[87] top.test.streamrecv[2].data[86] top.test.streamrecv[2].data[85] top.test.streamrecv[2].data[84] top.test.streamrecv[2].data[83] top.test.streamrecv[2].data[82] top.test.streamrecv[2].data[81] top.test.streamrecv[2].data[80] top.test.streamrecv[2].data[79] top.test.streamrecv[2].data[78] top.test.streamrecv[2].data[77] top.test.streamrecv[2].data[76] top.test.streamrecv[2].data[75] top.test.streamrecv[2].data[74] top.test.streamrecv[2].data[73] top.test.streamrecv[2].data[72] top.test.streamrecv[2].data[71] top.test.streamrecv[2].data[70] top.test.streamrecv[2].data[69] top.test.streamrecv[2].data[68] top.test.streamrecv[2].data[67] top.test.streamrecv[2].data[66] top.test.streamrecv[2].data[65] top.test.streamrecv[2].data[64] top.test.streamrecv[2].data[63] top.test.streamrecv[2].data[62] top.test.streamrecv[2].data[61] top.test.streamrecv[2].data[60] top.test.streamrecv[2].data[59] top.test.streamrecv[2].data[58] top.test.streamrecv[2].data[57] top.test.streamrecv[2].data[56] top.test.streamrecv[2].data[55] top.test.streamrecv[2].data[54] top.test.streamrecv[2].data[53] top.test.streamrecv[2].data[52] top.test.streamrecv[2].data[51] top.test.streamrecv[2].data[50] top.test.streamrecv[2].data[49] top.test.streamrecv[2].data[48] top.test.streamrecv[2].data[47] top.test.streamrecv[2].data[46] top.test.streamrecv[2].data[45] top.test.streamrecv[2].data[44] top.test.streamrecv[2].data[43] top.test.streamrecv[2].data[42] top.test.streamrecv[2].data[41] top.test.streamrecv[2].data[40] top.test.streamrecv[2].data[39] top.test.streamrecv[2].data[38] top.test.streamrecv[2].data[37] top.test.streamrecv[2].data[36] top.test.streamrecv[2].data[35] top.test.streamrecv[2].data[34] top.test.streamrecv[2].data[33] top.test.streamrecv[2].data[32] top.test.streamrecv[2].data[31] top.test.streamrecv[2].data[30] top.test.streamrecv[2].data[29] top.test.streamrecv[2].data[28] top.test.streamrecv[2].data[27] top.test.streamrecv[2].data[26] top.test.streamrecv[2].data[25] top.test.streamrecv[2].data[24] top.test.streamrecv[2].data[23] top.test.streamrecv[2].data[22] top.test.streamrecv[2].data[21] top.test.streamrecv[2].data[20] top.test.streamrecv[2].data[19] top.test.streamrecv[2].data[18] top.test.streamrecv[2].data[17] top.test.streamrecv[2].data[16] top.test.streamrecv[2].data[15] top.test.streamrecv[2].data[14] top.test.streamrecv[2].data[13] top.test.streamrecv[2].data[12] top.test.streamrecv[2].data[11] top.test.streamrecv[2].data[10] top.test.streamrecv[2].data[9] top.test.streamrecv[2].data[8] top.test.streamrecv[2].data[7] top.test.streamrecv[2].data[6] top.test.streamrecv[2].data[5] top.test.streamrecv[2].data[4] top.test.streamrecv[2].data[3] top.test.streamrecv[2].data[2] top.test.streamrecv[2].data[1] top.test.streamrecv[2].data[0]
 [pattern_trace] 1
 [pattern_trace] 0
index 674e64d7bb73438a9c149b54850fdca06c63c0c8..01853f5a9a30724f67c3410ccbb2cfc24eacb9dc 100644 (file)
@@ -8,15 +8,11 @@
 library ieee ;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
---use ieee.std_logic_unsigned.all;
---use ieee.std_logic_arith.all;
---use ieee.std_logic_misc.all;
---use ieee.std_logic_textio.all;
---use std.textio.all; 
 
 library work;
-use work.AxiPkg.all;
 use work.NvmeStoragePkg.all;
+use work.NvmeStorageIntPkg.all;
+use work.TestPkg.all;
 
 entity Test is
 end;
@@ -43,113 +39,10 @@ end component;
 signal clk             : std_logic := '0';
 signal reset           : std_logic := '0';
 
-signal streamSend      : AxisArrayType(0 to NumStreams-1)      := (others => AxisOutput);
-signal streamRecv      : AxisArrayType(0 to NumStreams-1)      := (others => AxisInput);
+signal streamSend      : AxisArrayType(0 to NumStreams-1) := (others => AxisOutput);
+signal streamRecv      : AxisArrayType(0 to NumStreams-1) := (others => AxisInput);
 
-procedure pcieWriteRequest(signal stream: inout AxisStream; request: in integer; streamNum: in integer; address: in integer; tag: in integer; count: in integer; data: in integer) is
-variable packetHead    : PcieRequestHead;
-variable c             : integer;
-variable d             : integer;
 begin
-       packetHead.nvme := to_unsigned(0, packetHead.nvme'length);
-       packetHead.stream := to_unsigned(streamNum, packetHead.stream'length);
-       packetHead.address := to_unsigned(address, packetHead.address'length);
-       packetHead.tag := to_unsigned(tag, packetHead.tag'length);
-       packetHead.count := to_unsigned(count, packetHead.count'length);
-       packetHead.request := to_unsigned(request, packetHead.request'length);
-       packetHead.requesterId := to_unsigned(0, packetHead.requesterId'length);
-       c := count / 4;
-       d := data;
-       
-       -- Write address
-       wait until rising_edge(clk);
-       stream.data <= to_stl(packetHead);
-       stream.keep <= concat('1', 16);
-       stream.valid <= '1';
-
-       while(c > 0) loop
-               wait until rising_edge(clk) and (stream.ready = '1');
-               stream.data <= to_stl(0, 96) & to_stl(d, 32);
-               stream.valid <= '1';
-               d := d + 1;
-               c := c - 1;
-       end loop;
-       stream.last <= '1';
-       
-       wait until rising_edge(clk) and (stream.ready = '1');
-       stream.valid <= '0';
-       stream.last <= '0';
-end procedure;
-
-procedure pcieReadRequest(signal stream: inout AxisStream; request: in integer; streamNum: in integer; address: in integer; tag: in integer; count: in integer) is
-variable packetHead    : PcieRequestHead;
-variable c             : integer;
-variable d             : integer;
-begin
-       packetHead.nvme := to_unsigned(0, packetHead.nvme'length);
-       packetHead.stream := to_unsigned(streamNum, packetHead.stream'length);
-       packetHead.address := to_unsigned(address, packetHead.address'length);
-       packetHead.tag := to_unsigned(tag, packetHead.tag'length);
-       packetHead.count := to_unsigned(count, packetHead.count'length);
-       packetHead.request := to_unsigned(request, packetHead.request'length);
-       packetHead.requesterId := to_unsigned(0, packetHead.requesterId'length);
-
-       -- Write address
-       wait until rising_edge(clk);
-       stream.data <= to_stl(packetHead);
-       stream.keep <= concat('1', 16);
-       stream.valid <= '1';
-       stream.last <= '1';
-       
-       wait until rising_edge(clk) and (stream.ready = '1');
-       stream.valid <= '0';
-       stream.last <= '0';
-end procedure;
-
-procedure pcieReply(signal stream: inout AxisStream; status: in integer; requesterId: in integer; address: in integer; tag: in integer; count: in integer; data: in integer) is
-variable packetHead    : PcieReplyHead;
-variable c             : integer;
-variable d             : integer;
-begin
-       packetHead.byteCount := to_unsigned(0, packetHead.byteCount'length);
-       packetHead.error := to_unsigned(0, packetHead.error'length);
-       packetHead.address := to_unsigned(address, packetHead.address'length);
-       packetHead.tag := to_unsigned(tag, packetHead.tag'length);
-       packetHead.count := to_unsigned(count, packetHead.count'length);
-       packetHead.status := to_unsigned(status, packetHead.status'length);
-       packetHead.requesterId := to_unsigned(requesterId, packetHead.requesterId'length);
-       c := count / 4;
-       d := data;
-       
-       -- Write address
-       wait until rising_edge(clk);
-       stream.data <= to_stl(d, 32) &to_stl(packetHead);
-       stream.keep <= concat('1', 16);
-       stream.valid <= '1';
-       d := d + 1;
-
-       while(c > 0) loop
-               wait until rising_edge(clk) and (stream.ready = '1');
-               stream.data <= to_stl(0, 96) & to_stl(d, 32);
-               stream.valid <= '1';
-               d := d + 1;
-               c := c - 1;
-       end loop;
-       stream.last <= '1';
-       stream.keep <= concat('0', 4) & concat('1', 12);                -- Hard coded for multiple of 4 data words
-       
-       wait until rising_edge(clk) and (stream.ready = '1');
-       stream.valid <= '0';
-       stream.last <= '0';
-end procedure;
-
-begin
-       set: for i in 1 to NumStreams-1 generate
-               streamSend(i).valid     <= '0';
-               streamRecv(i).ready     <= '1';
-       end generate;
-       streamRecv(0).ready     <= '1';
-       
        streamSwitch0 : StreamSwitch
        port map (
                clk             => clk,
@@ -172,20 +65,44 @@ begin
                wait;
        end process;
        
-       run : process
+       run1 : process
        begin
+               streamSend(0).valid     <= '0';
+               streamRecv(0).ready     <= '1';
+               streamSend(1).valid     <= '0';
+               streamRecv(1).ready     <= '1';
+       
                wait until reset = '0';
                
                -- Write queue entry
-               pcieWriteRequest(streamSend(0), 1, 1, 16#00000000#, 16#44#, 16, 16#00100000#);
-               pcieWriteRequest(streamSend(0), 1, 2, 16#00000000#, 16#44#, 16, 16#00200000#);
-               pcieWriteRequest(streamSend(0), 1, 3, 16#00000000#, 16#44#, 16, 16#00300000#);
+               pcieRequestWrite(clk, streamSend(0), 0, 1, 16#01000000#, 16#44#, 16, 16#01000000#);
+               pcieRequestWrite(clk, streamSend(1), 1, 1, 16#02000000#, 16#44#, 16, 16#02000000#);
 
-               pcieReply(streamSend(0), 0, 2, 16#00000000#, 16#44#, 16, 16#00300000#);
+               pcieReply(clk, streamSend(0), 2, 16#1234#, 16#00000000#, 16#44#, 16, 16#03000000#);
+
+               -- Test ready signal block
+               streamRecv(1).ready <= '0';
+               pcieRequestWrite(clk, streamSend(0), 0, 1, 16#01000000#, 16#44#, 16, 16#04000000#);
 
                wait;
        end process;
        
+       run2 : process
+       begin
+               streamSend(2).valid     <= '0';
+               streamRecv(2).ready     <= '1';
+               streamSend(3).valid     <= '0';
+               streamRecv(3).ready     <= '1';
+       
+               wait until reset = '0';
+               wait for 300 ns;
+               
+               -- Write queue entry
+               pcieRequestWrite(clk, streamSend(2), 0, 1, 16#00000000#, 16#44#, 16, 16#05000000#);
+
+               wait;
+       end process;
+
        stop : process
        begin
                wait for 700 ns;
diff --git a/source/DuneNvme/sim/testbench/test016-fifo.sav b/source/DuneNvme/sim/testbench/test016-fifo.sav
new file mode 100644 (file)
index 0000000..ecd5207
--- /dev/null
@@ -0,0 +1,182 @@
+[*]
+[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI
+[*] Mon Apr 27 11:05:21 2020
+[*]
+[dumpfile] "/src/dune/FpgaPlay/test020-nvmeprocess/sim/simu/test.ghw"
+[dumpfile_mtime] "Mon Apr 27 10:24:05 2020"
+[dumpfile_size] 1596504
+[savefile] "/src/dune/FpgaPlay/test020-nvmeprocess/sim/testbench/test016-fifo.sav"
+[timestart] 2495200000
+[size] 1920 1171
+[pos] -1 -1
+*-26.418455 2585100000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+[treeopen] top.
+[treeopen] top.test.
+[treeopen] top.test.hostrecv.
+[treeopen] top.test.hostsend.
+[treeopen] top.test.nvmereq.
+[treeopen] top.test.nvmestorageunit0.gen03.nvmequeues0.queueinarraypos.
+[treeopen] top.test.nvmestorageunit0.gen03.nvmequeues0.ram.
+[treeopen] top.test.nvmestorageunit0.gen03.nvmequeues0.requesthead1.
+[treeopen] top.test.nvmestorageunit0.gen03.streamswitch0.
+[treeopen] top.test.nvmestorageunit0.gen03.streamswitch0.streamin.
+[treeopen] top.test.nvmestorageunit0.gen03.streamswitch0.streamin.[0].
+[treeopen] top.test.nvmestorageunit0.gen03.streamswitch0.streamout.
+[treeopen] top.test.nvmestorageunit0.gen03.streamswitch0.streamout.[0].
+[treeopen] top.test.nvmestorageunit0.sim.
+[treeopen] top.test.nvmestorageunit0.sim.nvmesim0.
+[treeopen] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.
+[treeopen] top.test.nvmestorageunit0.sim.nvmesim0.queuerequest.
+[treeopen] top.test.nvmestorageunit0.streamrecv.
+[treeopen] top.test.nvmestorageunit0.streamrecv.[0].
+[treeopen] top.test.nvmestorageunit0.streamrecv.[1].
+[treeopen] top.test.nvmestorageunit0.streamrecv.[5].
+[treeopen] top.test.nvmestorageunit0.streamsend.
+[treeopen] top.test.nvmestorageunit0.streamsend.[0].
+[treeopen] top.test.nvmestorageunit0.streamsend.[5].
+[sst_width] 294
+[signals_width] 622
+[sst_expanded] 1
+[sst_vpaned_height] 768
+@28
+top.test.clk
+top.test.reset
+@800200
+-ResetLocal
+@28
+top.test.nvmestorageunit0.reset_local_run
+top.test.nvmestorageunit0.reset_local_done
+top.test.nvmestorageunit0.reset_local_active
+@420
+top.test.nvmestorageunit0.reset_local_counter
+@28
+top.test.nvmestorageunit0.reset_local
+@1000200
+-ResetLocal
+@800200
+-Fifo32k
+@28
+top.test.fifo_wr_en
+top.test.fifo_almost_full
+@29
+top.test.fifo_full1
+@28
+top.test.fifo_full
+top.test.fifo_empty
+top.test.fifo_rd_en
+top.test.fifo_valid
+@22
+#{top.test.fifo_data_count[8:0]} top.test.fifo_data_count[8] top.test.fifo_data_count[7] top.test.fifo_data_count[6] top.test.fifo_data_count[5] top.test.fifo_data_count[4] top.test.fifo_data_count[3] top.test.fifo_data_count[2] top.test.fifo_data_count[1] top.test.fifo_data_count[0]
+#{top.test.fifo_datain[127:0]} top.test.fifo_datain[127] top.test.fifo_datain[126] top.test.fifo_datain[125] top.test.fifo_datain[124] top.test.fifo_datain[123] top.test.fifo_datain[122] top.test.fifo_datain[121] top.test.fifo_datain[120] top.test.fifo_datain[119] top.test.fifo_datain[118] top.test.fifo_datain[117] top.test.fifo_datain[116] top.test.fifo_datain[115] top.test.fifo_datain[114] top.test.fifo_datain[113] top.test.fifo_datain[112] top.test.fifo_datain[111] top.test.fifo_datain[110] top.test.fifo_datain[109] top.test.fifo_datain[108] top.test.fifo_datain[107] top.test.fifo_datain[106] top.test.fifo_datain[105] top.test.fifo_datain[104] top.test.fifo_datain[103] top.test.fifo_datain[102] top.test.fifo_datain[101] top.test.fifo_datain[100] top.test.fifo_datain[99] top.test.fifo_datain[98] top.test.fifo_datain[97] top.test.fifo_datain[96] top.test.fifo_datain[95] top.test.fifo_datain[94] top.test.fifo_datain[93] top.test.fifo_datain[92] top.test.fifo_datain[91] top.test.fifo_datain[90] top.test.fifo_datain[89] top.test.fifo_datain[88] top.test.fifo_datain[87] top.test.fifo_datain[86] top.test.fifo_datain[85] top.test.fifo_datain[84] top.test.fifo_datain[83] top.test.fifo_datain[82] top.test.fifo_datain[81] top.test.fifo_datain[80] top.test.fifo_datain[79] top.test.fifo_datain[78] top.test.fifo_datain[77] top.test.fifo_datain[76] top.test.fifo_datain[75] top.test.fifo_datain[74] top.test.fifo_datain[73] top.test.fifo_datain[72] top.test.fifo_datain[71] top.test.fifo_datain[70] top.test.fifo_datain[69] top.test.fifo_datain[68] top.test.fifo_datain[67] top.test.fifo_datain[66] top.test.fifo_datain[65] top.test.fifo_datain[64] top.test.fifo_datain[63] top.test.fifo_datain[62] top.test.fifo_datain[61] top.test.fifo_datain[60] top.test.fifo_datain[59] top.test.fifo_datain[58] top.test.fifo_datain[57] top.test.fifo_datain[56] top.test.fifo_datain[55] top.test.fifo_datain[54] top.test.fifo_datain[53] top.test.fifo_datain[52] top.test.fifo_datain[51] top.test.fifo_datain[50] top.test.fifo_datain[49] top.test.fifo_datain[48] top.test.fifo_datain[47] top.test.fifo_datain[46] top.test.fifo_datain[45] top.test.fifo_datain[44] top.test.fifo_datain[43] top.test.fifo_datain[42] top.test.fifo_datain[41] top.test.fifo_datain[40] top.test.fifo_datain[39] top.test.fifo_datain[38] top.test.fifo_datain[37] top.test.fifo_datain[36] top.test.fifo_datain[35] top.test.fifo_datain[34] top.test.fifo_datain[33] top.test.fifo_datain[32] top.test.fifo_datain[31] top.test.fifo_datain[30] top.test.fifo_datain[29] top.test.fifo_datain[28] top.test.fifo_datain[27] top.test.fifo_datain[26] top.test.fifo_datain[25] top.test.fifo_datain[24] top.test.fifo_datain[23] top.test.fifo_datain[22] top.test.fifo_datain[21] top.test.fifo_datain[20] top.test.fifo_datain[19] top.test.fifo_datain[18] top.test.fifo_datain[17] top.test.fifo_datain[16] top.test.fifo_datain[15] top.test.fifo_datain[14] top.test.fifo_datain[13] top.test.fifo_datain[12] top.test.fifo_datain[11] top.test.fifo_datain[10] top.test.fifo_datain[9] top.test.fifo_datain[8] top.test.fifo_datain[7] top.test.fifo_datain[6] top.test.fifo_datain[5] top.test.fifo_datain[4] top.test.fifo_datain[3] top.test.fifo_datain[2] top.test.fifo_datain[1] top.test.fifo_datain[0]
+#{top.test.fifo_dataout[127:0]} top.test.fifo_dataout[127] top.test.fifo_dataout[126] top.test.fifo_dataout[125] top.test.fifo_dataout[124] top.test.fifo_dataout[123] top.test.fifo_dataout[122] top.test.fifo_dataout[121] top.test.fifo_dataout[120] top.test.fifo_dataout[119] top.test.fifo_dataout[118] top.test.fifo_dataout[117] top.test.fifo_dataout[116] top.test.fifo_dataout[115] top.test.fifo_dataout[114] top.test.fifo_dataout[113] top.test.fifo_dataout[112] top.test.fifo_dataout[111] top.test.fifo_dataout[110] top.test.fifo_dataout[109] top.test.fifo_dataout[108] top.test.fifo_dataout[107] top.test.fifo_dataout[106] top.test.fifo_dataout[105] top.test.fifo_dataout[104] top.test.fifo_dataout[103] top.test.fifo_dataout[102] top.test.fifo_dataout[101] top.test.fifo_dataout[100] top.test.fifo_dataout[99] top.test.fifo_dataout[98] top.test.fifo_dataout[97] top.test.fifo_dataout[96] top.test.fifo_dataout[95] top.test.fifo_dataout[94] top.test.fifo_dataout[93] top.test.fifo_dataout[92] top.test.fifo_dataout[91] top.test.fifo_dataout[90] top.test.fifo_dataout[89] top.test.fifo_dataout[88] top.test.fifo_dataout[87] top.test.fifo_dataout[86] top.test.fifo_dataout[85] top.test.fifo_dataout[84] top.test.fifo_dataout[83] top.test.fifo_dataout[82] top.test.fifo_dataout[81] top.test.fifo_dataout[80] top.test.fifo_dataout[79] top.test.fifo_dataout[78] top.test.fifo_dataout[77] top.test.fifo_dataout[76] top.test.fifo_dataout[75] top.test.fifo_dataout[74] top.test.fifo_dataout[73] top.test.fifo_dataout[72] top.test.fifo_dataout[71] top.test.fifo_dataout[70] top.test.fifo_dataout[69] top.test.fifo_dataout[68] top.test.fifo_dataout[67] top.test.fifo_dataout[66] top.test.fifo_dataout[65] top.test.fifo_dataout[64] top.test.fifo_dataout[63] top.test.fifo_dataout[62] top.test.fifo_dataout[61] top.test.fifo_dataout[60] top.test.fifo_dataout[59] top.test.fifo_dataout[58] top.test.fifo_dataout[57] top.test.fifo_dataout[56] top.test.fifo_dataout[55] top.test.fifo_dataout[54] top.test.fifo_dataout[53] top.test.fifo_dataout[52] top.test.fifo_dataout[51] top.test.fifo_dataout[50] top.test.fifo_dataout[49] top.test.fifo_dataout[48] top.test.fifo_dataout[47] top.test.fifo_dataout[46] top.test.fifo_dataout[45] top.test.fifo_dataout[44] top.test.fifo_dataout[43] top.test.fifo_dataout[42] top.test.fifo_dataout[41] top.test.fifo_dataout[40] top.test.fifo_dataout[39] top.test.fifo_dataout[38] top.test.fifo_dataout[37] top.test.fifo_dataout[36] top.test.fifo_dataout[35] top.test.fifo_dataout[34] top.test.fifo_dataout[33] top.test.fifo_dataout[32] top.test.fifo_dataout[31] top.test.fifo_dataout[30] top.test.fifo_dataout[29] top.test.fifo_dataout[28] top.test.fifo_dataout[27] top.test.fifo_dataout[26] top.test.fifo_dataout[25] top.test.fifo_dataout[24] top.test.fifo_dataout[23] top.test.fifo_dataout[22] top.test.fifo_dataout[21] top.test.fifo_dataout[20] top.test.fifo_dataout[19] top.test.fifo_dataout[18] top.test.fifo_dataout[17] top.test.fifo_dataout[16] top.test.fifo_dataout[15] top.test.fifo_dataout[14] top.test.fifo_dataout[13] top.test.fifo_dataout[12] top.test.fifo_dataout[11] top.test.fifo_dataout[10] top.test.fifo_dataout[9] top.test.fifo_dataout[8] top.test.fifo_dataout[7] top.test.fifo_dataout[6] top.test.fifo_dataout[5] top.test.fifo_dataout[4] top.test.fifo_dataout[3] top.test.fifo_dataout[2] top.test.fifo_dataout[1] top.test.fifo_dataout[0]
+@1000200
+-Fifo32k
+@800200
+-Host
+@28
+top.test.hostsend.ready
+top.test.hostsend.valid
+top.test.hostsend.last
+@22
+#{top.test.hostsend.keep[15:0]} top.test.hostsend.keep[15] top.test.hostsend.keep[14] top.test.hostsend.keep[13] top.test.hostsend.keep[12] top.test.hostsend.keep[11] top.test.hostsend.keep[10] top.test.hostsend.keep[9] top.test.hostsend.keep[8] top.test.hostsend.keep[7] top.test.hostsend.keep[6] top.test.hostsend.keep[5] top.test.hostsend.keep[4] top.test.hostsend.keep[3] top.test.hostsend.keep[2] top.test.hostsend.keep[1] top.test.hostsend.keep[0]
+#{top.test.hostsend.data[127:0]} top.test.hostsend.data[127] top.test.hostsend.data[126] top.test.hostsend.data[125] top.test.hostsend.data[124] top.test.hostsend.data[123] top.test.hostsend.data[122] top.test.hostsend.data[121] top.test.hostsend.data[120] top.test.hostsend.data[119] top.test.hostsend.data[118] top.test.hostsend.data[117] top.test.hostsend.data[116] top.test.hostsend.data[115] top.test.hostsend.data[114] top.test.hostsend.data[113] top.test.hostsend.data[112] top.test.hostsend.data[111] top.test.hostsend.data[110] top.test.hostsend.data[109] top.test.hostsend.data[108] top.test.hostsend.data[107] top.test.hostsend.data[106] top.test.hostsend.data[105] top.test.hostsend.data[104] top.test.hostsend.data[103] top.test.hostsend.data[102] top.test.hostsend.data[101] top.test.hostsend.data[100] top.test.hostsend.data[99] top.test.hostsend.data[98] top.test.hostsend.data[97] top.test.hostsend.data[96] top.test.hostsend.data[95] top.test.hostsend.data[94] top.test.hostsend.data[93] top.test.hostsend.data[92] top.test.hostsend.data[91] top.test.hostsend.data[90] top.test.hostsend.data[89] top.test.hostsend.data[88] top.test.hostsend.data[87] top.test.hostsend.data[86] top.test.hostsend.data[85] top.test.hostsend.data[84] top.test.hostsend.data[83] top.test.hostsend.data[82] top.test.hostsend.data[81] top.test.hostsend.data[80] top.test.hostsend.data[79] top.test.hostsend.data[78] top.test.hostsend.data[77] top.test.hostsend.data[76] top.test.hostsend.data[75] top.test.hostsend.data[74] top.test.hostsend.data[73] top.test.hostsend.data[72] top.test.hostsend.data[71] top.test.hostsend.data[70] top.test.hostsend.data[69] top.test.hostsend.data[68] top.test.hostsend.data[67] top.test.hostsend.data[66] top.test.hostsend.data[65] top.test.hostsend.data[64] top.test.hostsend.data[63] top.test.hostsend.data[62] top.test.hostsend.data[61] top.test.hostsend.data[60] top.test.hostsend.data[59] top.test.hostsend.data[58] top.test.hostsend.data[57] top.test.hostsend.data[56] top.test.hostsend.data[55] top.test.hostsend.data[54] top.test.hostsend.data[53] top.test.hostsend.data[52] top.test.hostsend.data[51] top.test.hostsend.data[50] top.test.hostsend.data[49] top.test.hostsend.data[48] top.test.hostsend.data[47] top.test.hostsend.data[46] top.test.hostsend.data[45] top.test.hostsend.data[44] top.test.hostsend.data[43] top.test.hostsend.data[42] top.test.hostsend.data[41] top.test.hostsend.data[40] top.test.hostsend.data[39] top.test.hostsend.data[38] top.test.hostsend.data[37] top.test.hostsend.data[36] top.test.hostsend.data[35] top.test.hostsend.data[34] top.test.hostsend.data[33] top.test.hostsend.data[32] top.test.hostsend.data[31] top.test.hostsend.data[30] top.test.hostsend.data[29] top.test.hostsend.data[28] top.test.hostsend.data[27] top.test.hostsend.data[26] top.test.hostsend.data[25] top.test.hostsend.data[24] top.test.hostsend.data[23] top.test.hostsend.data[22] top.test.hostsend.data[21] top.test.hostsend.data[20] top.test.hostsend.data[19] top.test.hostsend.data[18] top.test.hostsend.data[17] top.test.hostsend.data[16] top.test.hostsend.data[15] top.test.hostsend.data[14] top.test.hostsend.data[13] top.test.hostsend.data[12] top.test.hostsend.data[11] top.test.hostsend.data[10] top.test.hostsend.data[9] top.test.hostsend.data[8] top.test.hostsend.data[7] top.test.hostsend.data[6] top.test.hostsend.data[5] top.test.hostsend.data[4] top.test.hostsend.data[3] top.test.hostsend.data[2] top.test.hostsend.data[1] top.test.hostsend.data[0]
+@28
+top.test.hostrecv.ready
+top.test.hostrecv.valid
+top.test.hostrecv.last
+@22
+#{top.test.hostrecv.keep[15:0]} top.test.hostrecv.keep[15] top.test.hostrecv.keep[14] top.test.hostrecv.keep[13] top.test.hostrecv.keep[12] top.test.hostrecv.keep[11] top.test.hostrecv.keep[10] top.test.hostrecv.keep[9] top.test.hostrecv.keep[8] top.test.hostrecv.keep[7] top.test.hostrecv.keep[6] top.test.hostrecv.keep[5] top.test.hostrecv.keep[4] top.test.hostrecv.keep[3] top.test.hostrecv.keep[2] top.test.hostrecv.keep[1] top.test.hostrecv.keep[0]
+#{top.test.hostrecv.data[127:0]} top.test.hostrecv.data[127] top.test.hostrecv.data[126] top.test.hostrecv.data[125] top.test.hostrecv.data[124] top.test.hostrecv.data[123] top.test.hostrecv.data[122] top.test.hostrecv.data[121] top.test.hostrecv.data[120] top.test.hostrecv.data[119] top.test.hostrecv.data[118] top.test.hostrecv.data[117] top.test.hostrecv.data[116] top.test.hostrecv.data[115] top.test.hostrecv.data[114] top.test.hostrecv.data[113] top.test.hostrecv.data[112] top.test.hostrecv.data[111] top.test.hostrecv.data[110] top.test.hostrecv.data[109] top.test.hostrecv.data[108] top.test.hostrecv.data[107] top.test.hostrecv.data[106] top.test.hostrecv.data[105] top.test.hostrecv.data[104] top.test.hostrecv.data[103] top.test.hostrecv.data[102] top.test.hostrecv.data[101] top.test.hostrecv.data[100] top.test.hostrecv.data[99] top.test.hostrecv.data[98] top.test.hostrecv.data[97] top.test.hostrecv.data[96] top.test.hostrecv.data[95] top.test.hostrecv.data[94] top.test.hostrecv.data[93] top.test.hostrecv.data[92] top.test.hostrecv.data[91] top.test.hostrecv.data[90] top.test.hostrecv.data[89] top.test.hostrecv.data[88] top.test.hostrecv.data[87] top.test.hostrecv.data[86] top.test.hostrecv.data[85] top.test.hostrecv.data[84] top.test.hostrecv.data[83] top.test.hostrecv.data[82] top.test.hostrecv.data[81] top.test.hostrecv.data[80] top.test.hostrecv.data[79] top.test.hostrecv.data[78] top.test.hostrecv.data[77] top.test.hostrecv.data[76] top.test.hostrecv.data[75] top.test.hostrecv.data[74] top.test.hostrecv.data[73] top.test.hostrecv.data[72] top.test.hostrecv.data[71] top.test.hostrecv.data[70] top.test.hostrecv.data[69] top.test.hostrecv.data[68] top.test.hostrecv.data[67] top.test.hostrecv.data[66] top.test.hostrecv.data[65] top.test.hostrecv.data[64] top.test.hostrecv.data[63] top.test.hostrecv.data[62] top.test.hostrecv.data[61] top.test.hostrecv.data[60] top.test.hostrecv.data[59] top.test.hostrecv.data[58] top.test.hostrecv.data[57] top.test.hostrecv.data[56] top.test.hostrecv.data[55] top.test.hostrecv.data[54] top.test.hostrecv.data[53] top.test.hostrecv.data[52] top.test.hostrecv.data[51] top.test.hostrecv.data[50] top.test.hostrecv.data[49] top.test.hostrecv.data[48] top.test.hostrecv.data[47] top.test.hostrecv.data[46] top.test.hostrecv.data[45] top.test.hostrecv.data[44] top.test.hostrecv.data[43] top.test.hostrecv.data[42] top.test.hostrecv.data[41] top.test.hostrecv.data[40] top.test.hostrecv.data[39] top.test.hostrecv.data[38] top.test.hostrecv.data[37] top.test.hostrecv.data[36] top.test.hostrecv.data[35] top.test.hostrecv.data[34] top.test.hostrecv.data[33] top.test.hostrecv.data[32] top.test.hostrecv.data[31] top.test.hostrecv.data[30] top.test.hostrecv.data[29] top.test.hostrecv.data[28] top.test.hostrecv.data[27] top.test.hostrecv.data[26] top.test.hostrecv.data[25] top.test.hostrecv.data[24] top.test.hostrecv.data[23] top.test.hostrecv.data[22] top.test.hostrecv.data[21] top.test.hostrecv.data[20] top.test.hostrecv.data[19] top.test.hostrecv.data[18] top.test.hostrecv.data[17] top.test.hostrecv.data[16] top.test.hostrecv.data[15] top.test.hostrecv.data[14] top.test.hostrecv.data[13] top.test.hostrecv.data[12] top.test.hostrecv.data[11] top.test.hostrecv.data[10] top.test.hostrecv.data[9] top.test.hostrecv.data[8] top.test.hostrecv.data[7] top.test.hostrecv.data[6] top.test.hostrecv.data[5] top.test.hostrecv.data[4] top.test.hostrecv.data[3] top.test.hostrecv.data[2] top.test.hostrecv.data[1] top.test.hostrecv.data[0]
+@420
+top.test.nvmestate
+@1000200
+-Host
+@800200
+-Switch
+@28
+top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].valid
+@22
+#{top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[127:0]} top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[127] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[126] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[125] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[124] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[123] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[122] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[121] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[120] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[119] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[118] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[117] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[116] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[115] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[114] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[113] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[112] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[111] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[110] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[109] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[108] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[107] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[106] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[105] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[104] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[103] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[102] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[101] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[100] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[99] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[98] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[97] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[96] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[95] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[94] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[93] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[92] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[91] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[90] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[89] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[88] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[87] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[86] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[85] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[84] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[83] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[82] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[81] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[80] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[79] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[78] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[77] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[76] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[75] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[74] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[73] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[72] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[71] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[70] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[69] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[68] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[67] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[66] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[65] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[64] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[63] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[62] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[61] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[60] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[59] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[58] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[57] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[56] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[55] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[54] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[53] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[52] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[51] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[50] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[49] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[48] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[47] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[46] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[45] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[44] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[43] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[42] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[41] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[40] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[39] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[38] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[37] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[36] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[35] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[34] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[33] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[32] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[31] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[30] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[29] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[28] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[27] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[26] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[25] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[24] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[23] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[22] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[21] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[20] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[19] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[18] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[17] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[16] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[15] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[14] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[13] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[12] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[11] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[10] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[9] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[8] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[7] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[6] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[5] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[4] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[3] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[2] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[1] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[0]
+@28
+top.test.nvmestorageunit0.gen03.streamswitch0.streamout[0].ready
+top.test.nvmestorageunit0.gen03.streamswitch0.streamin[1].valid
+top.test.nvmestorageunit0.gen03.streamswitch0.streamout[1].ready
+top.test.nvmestorageunit0.gen03.streamswitch0.streamin[5].valid
+top.test.nvmestorageunit0.gen03.streamswitch0.streamout[5].ready
+@420
+top.test.nvmestorageunit0.gen03.streamswitch0.switchstate
+top.test.nvmestorageunit0.gen03.streamswitch0.switchin
+top.test.nvmestorageunit0.gen03.streamswitch0.switchout
+@1000200
+-Switch
+@800200
+-Nvme
+@420
+top.test.nvmestorageunit0.sim.nvmesim0.state
+@28
+top.test.nvmestorageunit0.gen03.streamswitch0.streamout[0].ready
+top.test.nvmestorageunit0.gen03.streamswitch0.streamout[0].valid
+top.test.nvmestorageunit0.gen03.streamswitch0.streamout[0].last
+@22
+#{top.test.nvmestorageunit0.gen03.streamswitch0.streamout[0].keep[15:0]} top.test.nvmestorageunit0.gen03.streamswitch0.streamout[0].keep[15] top.test.nvmestorageunit0.gen03.streamswitch0.streamout[0].keep[14] top.test.nvmestorageunit0.gen03.streamswitch0.streamout[0].keep[13] top.test.nvmestorageunit0.gen03.streamswitch0.streamout[0].keep[12] top.test.nvmestorageunit0.gen03.streamswitch0.streamout[0].keep[11] top.test.nvmestorageunit0.gen03.streamswitch0.streamout[0].keep[10] top.test.nvmestorageunit0.gen03.streamswitch0.streamout[0].keep[9] top.test.nvmestorageunit0.gen03.streamswitch0.streamout[0].keep[8] top.test.nvmestorageunit0.gen03.streamswitch0.streamout[0].keep[7] top.test.nvmestorageunit0.gen03.streamswitch0.streamout[0].keep[6] top.test.nvmestorageunit0.gen03.streamswitch0.streamout[0].keep[5] top.test.nvmestorageunit0.gen03.streamswitch0.streamout[0].keep[4] top.test.nvmestorageunit0.gen03.streamswitch0.streamout[0].keep[3] top.test.nvmestorageunit0.gen03.streamswitch0.streamout[0].keep[2] top.test.nvmestorageunit0.gen03.streamswitch0.streamout[0].keep[1] top.test.nvmestorageunit0.gen03.streamswitch0.streamout[0].keep[0]
+#{top.test.nvmestorageunit0.gen03.streamswitch0.streamout[0].data[127:0]} top.test.nvmestorageunit0.gen03.streamswitch0.streamout[0].data[127] top.test.nvmestorageunit0.gen03.streamswitch0.streamout[0].data[126] top.test.nvmestorageunit0.gen03.streamswitch0.streamout[0].data[125] top.test.nvmestorageunit0.gen03.streamswitch0.streamout[0].data[124] top.test.nvmestorageunit0.gen03.streamswitch0.streamout[0].data[123] top.test.nvmestorageunit0.gen03.streamswitch0.streamout[0].data[122] top.test.nvmestorageunit0.gen03.streamswitch0.streamout[0].data[121] top.test.nvmestorageunit0.gen03.streamswitch0.streamout[0].data[120] top.test.nvmestorageunit0.gen03.streamswitch0.streamout[0].data[119] top.test.nvmestorageunit0.gen03.streamswitch0.streamout[0].data[118] top.test.nvmestorageunit0.gen03.streamswitch0.streamout[0].data[117] top.test.nvmestorageunit0.gen03.streamswitch0.streamout[0].data[116] top.test.nvmestorageunit0.gen03.streamswitch0.streamout[0].data[115] top.test.nvmestorageunit0.gen03.streamswitch0.streamout[0].data[114] top.test.nvmestorageunit0.gen03.streamswitch0.streamout[0].data[113] top.test.nvmestorageunit0.gen03.streamswitch0.streamout[0].data[112] top.test.nvmestorageunit0.gen03.streamswitch0.streamout[0].data[111] top.test.nvmestorageunit0.gen03.streamswitch0.streamout[0].data[110] top.test.nvmestorageunit0.gen03.streamswitch0.streamout[0].data[109] top.test.nvmestorageunit0.gen03.streamswitch0.streamout[0].data[108] top.test.nvmestorageunit0.gen03.streamswitch0.streamout[0].data[107] top.test.nvmestorageunit0.gen03.streamswitch0.streamout[0].data[106] top.test.nvmestorageunit0.gen03.streamswitch0.streamout[0].data[105] top.test.nvmestorageunit0.gen03.streamswitch0.streamout[0].data[104] top.test.nvmestorageunit0.gen03.streamswitch0.streamout[0].data[103] top.test.nvmestorageunit0.gen03.streamswitch0.streamout[0].data[102] top.test.nvmestorageunit0.gen03.streamswitch0.streamout[0].data[101] top.test.nvmestorageunit0.gen03.streamswitch0.streamout[0].data[100] top.test.nvmestorageunit0.gen03.streamswitch0.streamout[0].data[99] top.test.nvmestorageunit0.gen03.streamswitch0.streamout[0].data[98] top.test.nvmestorageunit0.gen03.streamswitch0.streamout[0].data[97] top.test.nvmestorageunit0.gen03.streamswitch0.streamout[0].data[96] top.test.nvmestorageunit0.gen03.streamswitch0.streamout[0].data[95] top.test.nvmestorageunit0.gen03.streamswitch0.streamout[0].data[94] top.test.nvmestorageunit0.gen03.streamswitch0.streamout[0].data[93] top.test.nvmestorageunit0.gen03.streamswitch0.streamout[0].data[92] top.test.nvmestorageunit0.gen03.streamswitch0.streamout[0].data[91] top.test.nvmestorageunit0.gen03.streamswitch0.streamout[0].data[90] top.test.nvmestorageunit0.gen03.streamswitch0.streamout[0].data[89] top.test.nvmestorageunit0.gen03.streamswitch0.streamout[0].data[88] top.test.nvmestorageunit0.gen03.streamswitch0.streamout[0].data[87] top.test.nvmestorageunit0.gen03.streamswitch0.streamout[0].data[86] top.test.nvmestorageunit0.gen03.streamswitch0.streamout[0].data[85] top.test.nvmestorageunit0.gen03.streamswitch0.streamout[0].data[84] top.test.nvmestorageunit0.gen03.streamswitch0.streamout[0].data[83] top.test.nvmestorageunit0.gen03.streamswitch0.streamout[0].data[82] top.test.nvmestorageunit0.gen03.streamswitch0.streamout[0].data[81] top.test.nvmestorageunit0.gen03.streamswitch0.streamout[0].data[80] top.test.nvmestorageunit0.gen03.streamswitch0.streamout[0].data[79] top.test.nvmestorageunit0.gen03.streamswitch0.streamout[0].data[78] top.test.nvmestorageunit0.gen03.streamswitch0.streamout[0].data[77] top.test.nvmestorageunit0.gen03.streamswitch0.streamout[0].data[76] top.test.nvmestorageunit0.gen03.streamswitch0.streamout[0].data[75] top.test.nvmestorageunit0.gen03.streamswitch0.streamout[0].data[74] top.test.nvmestorageunit0.gen03.streamswitch0.streamout[0].data[73] top.test.nvmestorageunit0.gen03.streamswitch0.streamout[0].data[72] top.test.nvmestorageunit0.gen03.streamswitch0.streamout[0].data[71] top.test.nvmestorageunit0.gen03.streamswitch0.streamout[0].data[70] top.test.nvmestorageunit0.gen03.streamswitch0.streamout[0].data[69] top.test.nvmestorageunit0.gen03.streamswitch0.streamout[0].data[68] top.test.nvmestorageunit0.gen03.streamswitch0.streamout[0].data[67] top.test.nvmestorageunit0.gen03.streamswitch0.streamout[0].data[66] top.test.nvmestorageunit0.gen03.streamswitch0.streamout[0].data[65] top.test.nvmestorageunit0.gen03.streamswitch0.streamout[0].data[64] top.test.nvmestorageunit0.gen03.streamswitch0.streamout[0].data[63] top.test.nvmestorageunit0.gen03.streamswitch0.streamout[0].data[62] top.test.nvmestorageunit0.gen03.streamswitch0.streamout[0].data[61] top.test.nvmestorageunit0.gen03.streamswitch0.streamout[0].data[60] top.test.nvmestorageunit0.gen03.streamswitch0.streamout[0].data[59] top.test.nvmestorageunit0.gen03.streamswitch0.streamout[0].data[58] top.test.nvmestorageunit0.gen03.streamswitch0.streamout[0].data[57] top.test.nvmestorageunit0.gen03.streamswitch0.streamout[0].data[56] top.test.nvmestorageunit0.gen03.streamswitch0.streamout[0].data[55] top.test.nvmestorageunit0.gen03.streamswitch0.streamout[0].data[54] top.test.nvmestorageunit0.gen03.streamswitch0.streamout[0].data[53] top.test.nvmestorageunit0.gen03.streamswitch0.streamout[0].data[52] top.test.nvmestorageunit0.gen03.streamswitch0.streamout[0].data[51] top.test.nvmestorageunit0.gen03.streamswitch0.streamout[0].data[50] top.test.nvmestorageunit0.gen03.streamswitch0.streamout[0].data[49] top.test.nvmestorageunit0.gen03.streamswitch0.streamout[0].data[48] top.test.nvmestorageunit0.gen03.streamswitch0.streamout[0].data[47] top.test.nvmestorageunit0.gen03.streamswitch0.streamout[0].data[46] top.test.nvmestorageunit0.gen03.streamswitch0.streamout[0].data[45] top.test.nvmestorageunit0.gen03.streamswitch0.streamout[0].data[44] top.test.nvmestorageunit0.gen03.streamswitch0.streamout[0].data[43] top.test.nvmestorageunit0.gen03.streamswitch0.streamout[0].data[42] top.test.nvmestorageunit0.gen03.streamswitch0.streamout[0].data[41] top.test.nvmestorageunit0.gen03.streamswitch0.streamout[0].data[40] top.test.nvmestorageunit0.gen03.streamswitch0.streamout[0].data[39] top.test.nvmestorageunit0.gen03.streamswitch0.streamout[0].data[38] top.test.nvmestorageunit0.gen03.streamswitch0.streamout[0].data[37] top.test.nvmestorageunit0.gen03.streamswitch0.streamout[0].data[36] top.test.nvmestorageunit0.gen03.streamswitch0.streamout[0].data[35] top.test.nvmestorageunit0.gen03.streamswitch0.streamout[0].data[34] top.test.nvmestorageunit0.gen03.streamswitch0.streamout[0].data[33] top.test.nvmestorageunit0.gen03.streamswitch0.streamout[0].data[32] top.test.nvmestorageunit0.gen03.streamswitch0.streamout[0].data[31] top.test.nvmestorageunit0.gen03.streamswitch0.streamout[0].data[30] top.test.nvmestorageunit0.gen03.streamswitch0.streamout[0].data[29] top.test.nvmestorageunit0.gen03.streamswitch0.streamout[0].data[28] top.test.nvmestorageunit0.gen03.streamswitch0.streamout[0].data[27] top.test.nvmestorageunit0.gen03.streamswitch0.streamout[0].data[26] top.test.nvmestorageunit0.gen03.streamswitch0.streamout[0].data[25] top.test.nvmestorageunit0.gen03.streamswitch0.streamout[0].data[24] top.test.nvmestorageunit0.gen03.streamswitch0.streamout[0].data[23] top.test.nvmestorageunit0.gen03.streamswitch0.streamout[0].data[22] top.test.nvmestorageunit0.gen03.streamswitch0.streamout[0].data[21] top.test.nvmestorageunit0.gen03.streamswitch0.streamout[0].data[20] top.test.nvmestorageunit0.gen03.streamswitch0.streamout[0].data[19] top.test.nvmestorageunit0.gen03.streamswitch0.streamout[0].data[18] top.test.nvmestorageunit0.gen03.streamswitch0.streamout[0].data[17] top.test.nvmestorageunit0.gen03.streamswitch0.streamout[0].data[16] top.test.nvmestorageunit0.gen03.streamswitch0.streamout[0].data[15] top.test.nvmestorageunit0.gen03.streamswitch0.streamout[0].data[14] top.test.nvmestorageunit0.gen03.streamswitch0.streamout[0].data[13] top.test.nvmestorageunit0.gen03.streamswitch0.streamout[0].data[12] top.test.nvmestorageunit0.gen03.streamswitch0.streamout[0].data[11] top.test.nvmestorageunit0.gen03.streamswitch0.streamout[0].data[10] top.test.nvmestorageunit0.gen03.streamswitch0.streamout[0].data[9] top.test.nvmestorageunit0.gen03.streamswitch0.streamout[0].data[8] top.test.nvmestorageunit0.gen03.streamswitch0.streamout[0].data[7] top.test.nvmestorageunit0.gen03.streamswitch0.streamout[0].data[6] top.test.nvmestorageunit0.gen03.streamswitch0.streamout[0].data[5] top.test.nvmestorageunit0.gen03.streamswitch0.streamout[0].data[4] top.test.nvmestorageunit0.gen03.streamswitch0.streamout[0].data[3] top.test.nvmestorageunit0.gen03.streamswitch0.streamout[0].data[2] top.test.nvmestorageunit0.gen03.streamswitch0.streamout[0].data[1] top.test.nvmestorageunit0.gen03.streamswitch0.streamout[0].data[0]
+@28
+top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].ready
+top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].valid
+top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].last
+@22
+#{top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].keep[15:0]} top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].keep[15] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].keep[14] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].keep[13] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].keep[12] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].keep[11] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].keep[10] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].keep[9] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].keep[8] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].keep[7] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].keep[6] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].keep[5] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].keep[4] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].keep[3] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].keep[2] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].keep[1] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].keep[0]
+#{top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[127:0]} top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[127] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[126] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[125] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[124] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[123] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[122] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[121] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[120] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[119] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[118] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[117] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[116] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[115] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[114] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[113] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[112] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[111] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[110] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[109] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[108] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[107] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[106] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[105] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[104] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[103] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[102] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[101] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[100] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[99] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[98] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[97] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[96] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[95] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[94] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[93] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[92] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[91] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[90] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[89] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[88] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[87] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[86] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[85] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[84] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[83] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[82] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[81] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[80] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[79] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[78] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[77] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[76] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[75] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[74] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[73] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[72] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[71] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[70] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[69] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[68] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[67] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[66] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[65] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[64] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[63] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[62] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[61] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[60] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[59] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[58] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[57] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[56] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[55] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[54] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[53] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[52] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[51] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[50] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[49] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[48] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[47] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[46] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[45] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[44] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[43] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[42] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[41] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[40] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[39] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[38] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[37] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[36] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[35] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[34] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[33] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[32] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[31] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[30] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[29] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[28] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[27] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[26] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[25] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[24] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[23] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[22] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[21] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[20] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[19] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[18] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[17] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[16] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[15] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[14] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[13] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[12] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[11] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[10] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[9] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[8] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[7] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[6] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[5] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[4] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[3] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[2] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[1] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[0]
+#{top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[0][31:0]} top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[0][31] top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[0][30] top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[0][29] top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[0][28] top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[0][27] top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[0][26] top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[0][25] top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[0][24] top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[0][23] top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[0][22] top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[0][21] top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[0][20] top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[0][19] top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[0][18] top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[0][17] top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[0][16] top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[0][15] top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[0][14] top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[0][13] top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[0][12] top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[0][11] top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[0][10] top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[0][9] top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[0][8] top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[0][7] top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[0][6] top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[0][5] top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[0][4] top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[0][3] top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[0][2] top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[0][1] top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[0][0]
+@1000200
+-Nvme
+@28
+top.test.nvmestorageunit0.configstart
+@800200
+-QueueRam
+@420
+top.test.nvmestorageunit0.gen03.nvmequeues0.state
+@28
+top.test.nvmestorageunit0.streamrecv[5].ready
+top.test.nvmestorageunit0.streamrecv[5].valid
+top.test.nvmestorageunit0.streamrecv[5].last
+@22
+#{top.test.nvmestorageunit0.streamrecv[5].data[127:0]} top.test.nvmestorageunit0.streamrecv[5].data[127] top.test.nvmestorageunit0.streamrecv[5].data[126] top.test.nvmestorageunit0.streamrecv[5].data[125] top.test.nvmestorageunit0.streamrecv[5].data[124] top.test.nvmestorageunit0.streamrecv[5].data[123] top.test.nvmestorageunit0.streamrecv[5].data[122] top.test.nvmestorageunit0.streamrecv[5].data[121] top.test.nvmestorageunit0.streamrecv[5].data[120] top.test.nvmestorageunit0.streamrecv[5].data[119] top.test.nvmestorageunit0.streamrecv[5].data[118] top.test.nvmestorageunit0.streamrecv[5].data[117] top.test.nvmestorageunit0.streamrecv[5].data[116] top.test.nvmestorageunit0.streamrecv[5].data[115] top.test.nvmestorageunit0.streamrecv[5].data[114] top.test.nvmestorageunit0.streamrecv[5].data[113] top.test.nvmestorageunit0.streamrecv[5].data[112] top.test.nvmestorageunit0.streamrecv[5].data[111] top.test.nvmestorageunit0.streamrecv[5].data[110] top.test.nvmestorageunit0.streamrecv[5].data[109] top.test.nvmestorageunit0.streamrecv[5].data[108] top.test.nvmestorageunit0.streamrecv[5].data[107] top.test.nvmestorageunit0.streamrecv[5].data[106] top.test.nvmestorageunit0.streamrecv[5].data[105] top.test.nvmestorageunit0.streamrecv[5].data[104] top.test.nvmestorageunit0.streamrecv[5].data[103] top.test.nvmestorageunit0.streamrecv[5].data[102] top.test.nvmestorageunit0.streamrecv[5].data[101] top.test.nvmestorageunit0.streamrecv[5].data[100] top.test.nvmestorageunit0.streamrecv[5].data[99] top.test.nvmestorageunit0.streamrecv[5].data[98] top.test.nvmestorageunit0.streamrecv[5].data[97] top.test.nvmestorageunit0.streamrecv[5].data[96] top.test.nvmestorageunit0.streamrecv[5].data[95] top.test.nvmestorageunit0.streamrecv[5].data[94] top.test.nvmestorageunit0.streamrecv[5].data[93] top.test.nvmestorageunit0.streamrecv[5].data[92] top.test.nvmestorageunit0.streamrecv[5].data[91] top.test.nvmestorageunit0.streamrecv[5].data[90] top.test.nvmestorageunit0.streamrecv[5].data[89] top.test.nvmestorageunit0.streamrecv[5].data[88] top.test.nvmestorageunit0.streamrecv[5].data[87] top.test.nvmestorageunit0.streamrecv[5].data[86] top.test.nvmestorageunit0.streamrecv[5].data[85] top.test.nvmestorageunit0.streamrecv[5].data[84] top.test.nvmestorageunit0.streamrecv[5].data[83] top.test.nvmestorageunit0.streamrecv[5].data[82] top.test.nvmestorageunit0.streamrecv[5].data[81] top.test.nvmestorageunit0.streamrecv[5].data[80] top.test.nvmestorageunit0.streamrecv[5].data[79] top.test.nvmestorageunit0.streamrecv[5].data[78] top.test.nvmestorageunit0.streamrecv[5].data[77] top.test.nvmestorageunit0.streamrecv[5].data[76] top.test.nvmestorageunit0.streamrecv[5].data[75] top.test.nvmestorageunit0.streamrecv[5].data[74] top.test.nvmestorageunit0.streamrecv[5].data[73] top.test.nvmestorageunit0.streamrecv[5].data[72] top.test.nvmestorageunit0.streamrecv[5].data[71] top.test.nvmestorageunit0.streamrecv[5].data[70] top.test.nvmestorageunit0.streamrecv[5].data[69] top.test.nvmestorageunit0.streamrecv[5].data[68] top.test.nvmestorageunit0.streamrecv[5].data[67] top.test.nvmestorageunit0.streamrecv[5].data[66] top.test.nvmestorageunit0.streamrecv[5].data[65] top.test.nvmestorageunit0.streamrecv[5].data[64] top.test.nvmestorageunit0.streamrecv[5].data[63] top.test.nvmestorageunit0.streamrecv[5].data[62] top.test.nvmestorageunit0.streamrecv[5].data[61] top.test.nvmestorageunit0.streamrecv[5].data[60] top.test.nvmestorageunit0.streamrecv[5].data[59] top.test.nvmestorageunit0.streamrecv[5].data[58] top.test.nvmestorageunit0.streamrecv[5].data[57] top.test.nvmestorageunit0.streamrecv[5].data[56] top.test.nvmestorageunit0.streamrecv[5].data[55] top.test.nvmestorageunit0.streamrecv[5].data[54] top.test.nvmestorageunit0.streamrecv[5].data[53] top.test.nvmestorageunit0.streamrecv[5].data[52] top.test.nvmestorageunit0.streamrecv[5].data[51] top.test.nvmestorageunit0.streamrecv[5].data[50] top.test.nvmestorageunit0.streamrecv[5].data[49] top.test.nvmestorageunit0.streamrecv[5].data[48] top.test.nvmestorageunit0.streamrecv[5].data[47] top.test.nvmestorageunit0.streamrecv[5].data[46] top.test.nvmestorageunit0.streamrecv[5].data[45] top.test.nvmestorageunit0.streamrecv[5].data[44] top.test.nvmestorageunit0.streamrecv[5].data[43] top.test.nvmestorageunit0.streamrecv[5].data[42] top.test.nvmestorageunit0.streamrecv[5].data[41] top.test.nvmestorageunit0.streamrecv[5].data[40] top.test.nvmestorageunit0.streamrecv[5].data[39] top.test.nvmestorageunit0.streamrecv[5].data[38] top.test.nvmestorageunit0.streamrecv[5].data[37] top.test.nvmestorageunit0.streamrecv[5].data[36] top.test.nvmestorageunit0.streamrecv[5].data[35] top.test.nvmestorageunit0.streamrecv[5].data[34] top.test.nvmestorageunit0.streamrecv[5].data[33] top.test.nvmestorageunit0.streamrecv[5].data[32] top.test.nvmestorageunit0.streamrecv[5].data[31] top.test.nvmestorageunit0.streamrecv[5].data[30] top.test.nvmestorageunit0.streamrecv[5].data[29] top.test.nvmestorageunit0.streamrecv[5].data[28] top.test.nvmestorageunit0.streamrecv[5].data[27] top.test.nvmestorageunit0.streamrecv[5].data[26] top.test.nvmestorageunit0.streamrecv[5].data[25] top.test.nvmestorageunit0.streamrecv[5].data[24] top.test.nvmestorageunit0.streamrecv[5].data[23] top.test.nvmestorageunit0.streamrecv[5].data[22] top.test.nvmestorageunit0.streamrecv[5].data[21] top.test.nvmestorageunit0.streamrecv[5].data[20] top.test.nvmestorageunit0.streamrecv[5].data[19] top.test.nvmestorageunit0.streamrecv[5].data[18] top.test.nvmestorageunit0.streamrecv[5].data[17] top.test.nvmestorageunit0.streamrecv[5].data[16] top.test.nvmestorageunit0.streamrecv[5].data[15] top.test.nvmestorageunit0.streamrecv[5].data[14] top.test.nvmestorageunit0.streamrecv[5].data[13] top.test.nvmestorageunit0.streamrecv[5].data[12] top.test.nvmestorageunit0.streamrecv[5].data[11] top.test.nvmestorageunit0.streamrecv[5].data[10] top.test.nvmestorageunit0.streamrecv[5].data[9] top.test.nvmestorageunit0.streamrecv[5].data[8] top.test.nvmestorageunit0.streamrecv[5].data[7] top.test.nvmestorageunit0.streamrecv[5].data[6] top.test.nvmestorageunit0.streamrecv[5].data[5] top.test.nvmestorageunit0.streamrecv[5].data[4] top.test.nvmestorageunit0.streamrecv[5].data[3] top.test.nvmestorageunit0.streamrecv[5].data[2] top.test.nvmestorageunit0.streamrecv[5].data[1] top.test.nvmestorageunit0.streamrecv[5].data[0]
+@28
+top.test.nvmestorageunit0.streamsend[5].ready
+top.test.nvmestorageunit0.streamsend[5].valid
+top.test.nvmestorageunit0.streamsend[5].last
+@22
+#{top.test.nvmestorageunit0.streamsend[5].data[127:0]} top.test.nvmestorageunit0.streamsend[5].data[127] top.test.nvmestorageunit0.streamsend[5].data[126] top.test.nvmestorageunit0.streamsend[5].data[125] top.test.nvmestorageunit0.streamsend[5].data[124] top.test.nvmestorageunit0.streamsend[5].data[123] top.test.nvmestorageunit0.streamsend[5].data[122] top.test.nvmestorageunit0.streamsend[5].data[121] top.test.nvmestorageunit0.streamsend[5].data[120] top.test.nvmestorageunit0.streamsend[5].data[119] top.test.nvmestorageunit0.streamsend[5].data[118] top.test.nvmestorageunit0.streamsend[5].data[117] top.test.nvmestorageunit0.streamsend[5].data[116] top.test.nvmestorageunit0.streamsend[5].data[115] top.test.nvmestorageunit0.streamsend[5].data[114] top.test.nvmestorageunit0.streamsend[5].data[113] top.test.nvmestorageunit0.streamsend[5].data[112] top.test.nvmestorageunit0.streamsend[5].data[111] top.test.nvmestorageunit0.streamsend[5].data[110] top.test.nvmestorageunit0.streamsend[5].data[109] top.test.nvmestorageunit0.streamsend[5].data[108] top.test.nvmestorageunit0.streamsend[5].data[107] top.test.nvmestorageunit0.streamsend[5].data[106] top.test.nvmestorageunit0.streamsend[5].data[105] top.test.nvmestorageunit0.streamsend[5].data[104] top.test.nvmestorageunit0.streamsend[5].data[103] top.test.nvmestorageunit0.streamsend[5].data[102] top.test.nvmestorageunit0.streamsend[5].data[101] top.test.nvmestorageunit0.streamsend[5].data[100] top.test.nvmestorageunit0.streamsend[5].data[99] top.test.nvmestorageunit0.streamsend[5].data[98] top.test.nvmestorageunit0.streamsend[5].data[97] top.test.nvmestorageunit0.streamsend[5].data[96] top.test.nvmestorageunit0.streamsend[5].data[95] top.test.nvmestorageunit0.streamsend[5].data[94] top.test.nvmestorageunit0.streamsend[5].data[93] top.test.nvmestorageunit0.streamsend[5].data[92] top.test.nvmestorageunit0.streamsend[5].data[91] top.test.nvmestorageunit0.streamsend[5].data[90] top.test.nvmestorageunit0.streamsend[5].data[89] top.test.nvmestorageunit0.streamsend[5].data[88] top.test.nvmestorageunit0.streamsend[5].data[87] top.test.nvmestorageunit0.streamsend[5].data[86] top.test.nvmestorageunit0.streamsend[5].data[85] top.test.nvmestorageunit0.streamsend[5].data[84] top.test.nvmestorageunit0.streamsend[5].data[83] top.test.nvmestorageunit0.streamsend[5].data[82] top.test.nvmestorageunit0.streamsend[5].data[81] top.test.nvmestorageunit0.streamsend[5].data[80] top.test.nvmestorageunit0.streamsend[5].data[79] top.test.nvmestorageunit0.streamsend[5].data[78] top.test.nvmestorageunit0.streamsend[5].data[77] top.test.nvmestorageunit0.streamsend[5].data[76] top.test.nvmestorageunit0.streamsend[5].data[75] top.test.nvmestorageunit0.streamsend[5].data[74] top.test.nvmestorageunit0.streamsend[5].data[73] top.test.nvmestorageunit0.streamsend[5].data[72] top.test.nvmestorageunit0.streamsend[5].data[71] top.test.nvmestorageunit0.streamsend[5].data[70] top.test.nvmestorageunit0.streamsend[5].data[69] top.test.nvmestorageunit0.streamsend[5].data[68] top.test.nvmestorageunit0.streamsend[5].data[67] top.test.nvmestorageunit0.streamsend[5].data[66] top.test.nvmestorageunit0.streamsend[5].data[65] top.test.nvmestorageunit0.streamsend[5].data[64] top.test.nvmestorageunit0.streamsend[5].data[63] top.test.nvmestorageunit0.streamsend[5].data[62] top.test.nvmestorageunit0.streamsend[5].data[61] top.test.nvmestorageunit0.streamsend[5].data[60] top.test.nvmestorageunit0.streamsend[5].data[59] top.test.nvmestorageunit0.streamsend[5].data[58] top.test.nvmestorageunit0.streamsend[5].data[57] top.test.nvmestorageunit0.streamsend[5].data[56] top.test.nvmestorageunit0.streamsend[5].data[55] top.test.nvmestorageunit0.streamsend[5].data[54] top.test.nvmestorageunit0.streamsend[5].data[53] top.test.nvmestorageunit0.streamsend[5].data[52] top.test.nvmestorageunit0.streamsend[5].data[51] top.test.nvmestorageunit0.streamsend[5].data[50] top.test.nvmestorageunit0.streamsend[5].data[49] top.test.nvmestorageunit0.streamsend[5].data[48] top.test.nvmestorageunit0.streamsend[5].data[47] top.test.nvmestorageunit0.streamsend[5].data[46] top.test.nvmestorageunit0.streamsend[5].data[45] top.test.nvmestorageunit0.streamsend[5].data[44] top.test.nvmestorageunit0.streamsend[5].data[43] top.test.nvmestorageunit0.streamsend[5].data[42] top.test.nvmestorageunit0.streamsend[5].data[41] top.test.nvmestorageunit0.streamsend[5].data[40] top.test.nvmestorageunit0.streamsend[5].data[39] top.test.nvmestorageunit0.streamsend[5].data[38] top.test.nvmestorageunit0.streamsend[5].data[37] top.test.nvmestorageunit0.streamsend[5].data[36] top.test.nvmestorageunit0.streamsend[5].data[35] top.test.nvmestorageunit0.streamsend[5].data[34] top.test.nvmestorageunit0.streamsend[5].data[33] top.test.nvmestorageunit0.streamsend[5].data[32] top.test.nvmestorageunit0.streamsend[5].data[31] top.test.nvmestorageunit0.streamsend[5].data[30] top.test.nvmestorageunit0.streamsend[5].data[29] top.test.nvmestorageunit0.streamsend[5].data[28] top.test.nvmestorageunit0.streamsend[5].data[27] top.test.nvmestorageunit0.streamsend[5].data[26] top.test.nvmestorageunit0.streamsend[5].data[25] top.test.nvmestorageunit0.streamsend[5].data[24] top.test.nvmestorageunit0.streamsend[5].data[23] top.test.nvmestorageunit0.streamsend[5].data[22] top.test.nvmestorageunit0.streamsend[5].data[21] top.test.nvmestorageunit0.streamsend[5].data[20] top.test.nvmestorageunit0.streamsend[5].data[19] top.test.nvmestorageunit0.streamsend[5].data[18] top.test.nvmestorageunit0.streamsend[5].data[17] top.test.nvmestorageunit0.streamsend[5].data[16] top.test.nvmestorageunit0.streamsend[5].data[15] top.test.nvmestorageunit0.streamsend[5].data[14] top.test.nvmestorageunit0.streamsend[5].data[13] top.test.nvmestorageunit0.streamsend[5].data[12] top.test.nvmestorageunit0.streamsend[5].data[11] top.test.nvmestorageunit0.streamsend[5].data[10] top.test.nvmestorageunit0.streamsend[5].data[9] top.test.nvmestorageunit0.streamsend[5].data[8] top.test.nvmestorageunit0.streamsend[5].data[7] top.test.nvmestorageunit0.streamsend[5].data[6] top.test.nvmestorageunit0.streamsend[5].data[5] top.test.nvmestorageunit0.streamsend[5].data[4] top.test.nvmestorageunit0.streamsend[5].data[3] top.test.nvmestorageunit0.streamsend[5].data[2] top.test.nvmestorageunit0.streamsend[5].data[1] top.test.nvmestorageunit0.streamsend[5].data[0]
+#{top.test.nvmestorageunit0.gen03.nvmequeues0.requesthead1.requesterid[15:0]} top.test.nvmestorageunit0.gen03.nvmequeues0.requesthead1.requesterid[15] top.test.nvmestorageunit0.gen03.nvmequeues0.requesthead1.requesterid[14] top.test.nvmestorageunit0.gen03.nvmequeues0.requesthead1.requesterid[13] top.test.nvmestorageunit0.gen03.nvmequeues0.requesthead1.requesterid[12] top.test.nvmestorageunit0.gen03.nvmequeues0.requesthead1.requesterid[11] top.test.nvmestorageunit0.gen03.nvmequeues0.requesthead1.requesterid[10] top.test.nvmestorageunit0.gen03.nvmequeues0.requesthead1.requesterid[9] top.test.nvmestorageunit0.gen03.nvmequeues0.requesthead1.requesterid[8] top.test.nvmestorageunit0.gen03.nvmequeues0.requesthead1.requesterid[7] top.test.nvmestorageunit0.gen03.nvmequeues0.requesthead1.requesterid[6] top.test.nvmestorageunit0.gen03.nvmequeues0.requesthead1.requesterid[5] top.test.nvmestorageunit0.gen03.nvmequeues0.requesthead1.requesterid[4] top.test.nvmestorageunit0.gen03.nvmequeues0.requesthead1.requesterid[3] top.test.nvmestorageunit0.gen03.nvmequeues0.requesthead1.requesterid[2] top.test.nvmestorageunit0.gen03.nvmequeues0.requesthead1.requesterid[1] top.test.nvmestorageunit0.gen03.nvmequeues0.requesthead1.requesterid[0]
+@420
+top.test.nvmestorageunit0.gen03.nvmequeues0.ramaddress
+@1000200
+-QueueRam
+@800200
+-NvmeQueue
+@22
+#{top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][127:0]} top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][127] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][126] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][125] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][124] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][123] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][122] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][121] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][120] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][119] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][118] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][117] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][116] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][115] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][114] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][113] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][112] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][111] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][110] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][109] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][108] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][107] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][106] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][105] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][104] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][103] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][102] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][101] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][100] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][99] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][98] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][97] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][96] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][95] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][94] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][93] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][92] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][91] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][90] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][89] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][88] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][87] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][86] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][85] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][84] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][83] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][82] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][81] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][80] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][79] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][78] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][77] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][76] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][75] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][74] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][73] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][72] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][71] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][70] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][69] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][68] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][67] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][66] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][65] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][64] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][63] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][62] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][61] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][60] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][59] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][58] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][57] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][56] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][55] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][54] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][53] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][52] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][51] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][50] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][49] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][48] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][47] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][46] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][45] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][44] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][43] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][42] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][41] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][40] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][39] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][38] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][37] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][36] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][35] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][34] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][33] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][32] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][31] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][30] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][29] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][28] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][27] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][26] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][25] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][24] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][23] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][22] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][21] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][20] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][19] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][18] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][17] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][16] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][15] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][14] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][13] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][12] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][11] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][10] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][9] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][8] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][7] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][6] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][5] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][4] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][3] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][2] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][1] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][0]
+#{top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][127:0]} top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][127] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][126] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][125] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][124] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][123] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][122] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][121] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][120] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][119] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][118] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][117] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][116] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][115] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][114] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][113] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][112] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][111] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][110] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][109] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][108] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][107] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][106] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][105] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][104] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][103] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][102] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][101] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][100] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][99] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][98] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][97] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][96] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][95] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][94] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][93] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][92] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][91] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][90] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][89] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][88] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][87] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][86] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][85] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][84] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][83] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][82] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][81] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][80] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][79] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][78] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][77] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][76] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][75] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][74] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][73] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][72] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][71] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][70] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][69] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][68] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][67] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][66] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][65] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][64] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][63] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][62] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][61] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][60] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][59] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][58] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][57] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][56] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][55] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][54] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][53] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][52] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][51] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][50] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][49] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][48] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][47] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][46] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][45] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][44] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][43] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][42] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][41] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][40] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][39] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][38] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][37] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][36] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][35] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][34] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][33] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][32] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][31] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][30] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][29] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][28] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][27] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][26] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][25] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][24] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][23] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][22] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][21] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][20] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][19] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][18] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][17] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][16] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][15] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][14] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][13] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][12] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][11] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][10] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][9] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][8] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][7] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][6] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][5] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][4] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][3] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][2] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][1] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][0]
+@1000200
+-NvmeQueue
+@800200
+-NvmeSim
+@420
+top.test.nvmestorageunit0.sim.nvmesim0.state
+@22
+#{top.test.nvmestorageunit0.sim.nvmesim0.count[10:0]} top.test.nvmestorageunit0.sim.nvmesim0.count[10] top.test.nvmestorageunit0.sim.nvmesim0.count[9] top.test.nvmestorageunit0.sim.nvmesim0.count[8] top.test.nvmestorageunit0.sim.nvmesim0.count[7] top.test.nvmestorageunit0.sim.nvmesim0.count[6] top.test.nvmestorageunit0.sim.nvmesim0.count[5] top.test.nvmestorageunit0.sim.nvmesim0.count[4] top.test.nvmestorageunit0.sim.nvmesim0.count[3] top.test.nvmestorageunit0.sim.nvmesim0.count[2] top.test.nvmestorageunit0.sim.nvmesim0.count[1] top.test.nvmestorageunit0.sim.nvmesim0.count[0]
+@28
+top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.ready
+top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.valid
+top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.last
+@22
+#{top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[127:0]} top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[127] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[126] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[125] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[124] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[123] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[122] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[121] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[120] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[119] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[118] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[117] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[116] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[115] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[114] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[113] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[112] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[111] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[110] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[109] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[108] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[107] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[106] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[105] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[104] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[103] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[102] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[101] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[100] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[99] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[98] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[97] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[96] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[95] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[94] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[93] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[92] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[91] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[90] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[89] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[88] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[87] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[86] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[85] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[84] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[83] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[82] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[81] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[80] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[79] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[78] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[77] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[76] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[75] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[74] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[73] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[72] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[71] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[70] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[69] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[68] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[67] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[66] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[65] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[64] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[63] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[62] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[61] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[60] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[59] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[58] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[57] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[56] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[55] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[54] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[53] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[52] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[51] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[50] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[49] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[48] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[47] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[46] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[45] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[44] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[43] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[42] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[41] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[40] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[39] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[38] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[37] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[36] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[35] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[34] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[33] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[32] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[31] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[30] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[29] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[28] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[27] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[26] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[25] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[24] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[23] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[22] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[21] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[20] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[19] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[18] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[17] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[16] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[15] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[14] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[13] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[12] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[11] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[10] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[9] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[8] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[7] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[6] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[5] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[4] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[3] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[2] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[1] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[0]
+#{top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[0][127:0]} top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[0][31] top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[0][30] top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[0][29] top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[0][28] top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[0][27] top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[0][26] top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[0][25] top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[0][24] top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[0][23] top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[0][22] top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[0][21] top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[0][20] top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[0][19] top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[0][18] top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[0][17] top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[0][16] top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[0][15] top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[0][14] top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[0][13] top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[0][12] top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[0][11] top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[0][10] top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[0][9] top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[0][8] top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[0][7] top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[0][6] top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[0][5] top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[0][4] top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[0][3] top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[0][2] top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[0][1] top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[0][0]
+#{top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[1][127:0]} top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[1][31] top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[1][30] top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[1][29] top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[1][28] top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[1][27] top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[1][26] top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[1][25] top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[1][24] top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[1][23] top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[1][22] top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[1][21] top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[1][20] top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[1][19] top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[1][18] top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[1][17] top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[1][16] top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[1][15] top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[1][14] top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[1][13] top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[1][12] top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[1][11] top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[1][10] top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[1][9] top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[1][8] top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[1][7] top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[1][6] top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[1][5] top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[1][4] top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[1][3] top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[1][2] top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[1][1] top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[1][0]
+@1000200
+-NvmeSim
+@22
+#{top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[127:0]} top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[127] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[126] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[125] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[124] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[123] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[122] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[121] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[120] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[119] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[118] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[117] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[116] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[115] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[114] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[113] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[112] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[111] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[110] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[109] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[108] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[107] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[106] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[105] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[104] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[103] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[102] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[101] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[100] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[99] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[98] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[97] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[96] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[95] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[94] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[93] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[92] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[91] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[90] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[89] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[88] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[87] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[86] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[85] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[84] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[83] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[82] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[81] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[80] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[79] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[78] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[77] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[76] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[75] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[74] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[73] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[72] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[71] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[70] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[69] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[68] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[67] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[66] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[65] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[64] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[63] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[62] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[61] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[60] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[59] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[58] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[57] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[56] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[55] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[54] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[53] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[52] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[51] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[50] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[49] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[48] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[47] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[46] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[45] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[44] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[43] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[42] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[41] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[40] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[39] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[38] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[37] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[36] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[35] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[34] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[33] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[32] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[31] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[30] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[29] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[28] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[27] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[26] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[25] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[24] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[23] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[22] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[21] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[20] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[19] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[18] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[17] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[16] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[15] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[14] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[13] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[12] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[11] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[10] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[9] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[8] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[7] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[6] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[5] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[4] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[3] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[2] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[1] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[0]
+[pattern_trace] 1
+[pattern_trace] 0
diff --git a/source/DuneNvme/sim/testbench/test016-fifo.vhd b/source/DuneNvme/sim/testbench/test016-fifo.vhd
new file mode 100644 (file)
index 0000000..1b2de31
--- /dev/null
@@ -0,0 +1,385 @@
+--------------------------------------------------------------------------------
+--     Test009-packets.vhd     Simple nvme interface tests
+--     T.Barnaby,      Beam Ltd.       2020-04-14
+--------------------------------------------------------------------------------
+--
+--
+--
+library ieee ;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.NvmeStoragePkg.all;
+use work.NvmeStorageIntPkg.all;
+use work.TestPkg.all;
+
+entity Test is
+end;
+
+architecture sim of Test is
+
+component NvmeStorageUnit is
+generic(
+       Simulate        : boolean       := True;                --! Generate simulation core
+       ClockPeriod     : time          := 10 ms                --! Clock period for timers (125 MHz)
+);
+port (
+       clk             : in std_logic;                         --! The interface clock line
+       reset           : in std_logic;                         --! The active high reset line
+
+       -- Control and status interface
+       axilIn          : in AxilToSlaveType;                   --! Axil bus input signals
+       axilOut         : out AxilToMasterType;                 --! Axil bus output signals
+
+       -- From host to NVMe request/reply streams
+       hostSend        : inout AxisStreamType := AxisInput;    --! Host request stream
+       hostRecv        : inout AxisStreamType := AxisOutput;   --! Host reply stream
+
+       -- AXIS data stream input
+       --dataRx        : inout AxisStreamType  := AxisInput;   --! Raw data to save stream
+
+       -- NVMe interface
+       nvme_clk_p      : in std_logic;                         --! Nvme external clock +ve
+       nvme_clk_n      : in std_logic;                         --! Nvme external clock -ve
+       nvme_reset_n    : out std_logic;                        --! Nvme reset output to reset NVMe devices
+       nvme_exp_txp    : out std_logic_vector(3 downto 0);     --! Nvme PCIe TX plus lanes
+       nvme_exp_txn    : out std_logic_vector(3 downto 0);     --! Nvme PCIe TX minus lanes
+       nvme_exp_rxp    : in std_logic_vector(3 downto 0);      --! Nvme PCIe RX plus lanes
+       nvme_exp_rxn    : in std_logic_vector(3 downto 0);      --! Nvme PCIe RX minus lanes
+
+       -- Debug
+       leds            : out std_logic_vector(3 downto 0)
+);
+end component;
+
+component NvmeStreamMux is
+port (
+       clk             : in std_logic;                         --! The interface clock line
+       reset           : in std_logic;                         --! The active high reset line
+       
+       stream1In       : inout AxisStreamType := AxisInput;    --! Single multiplexed Input stream
+       stream1Out      : inout AxisStreamType := AxisOutput;   --! Single multiplexed Ouput stream
+
+       stream2In       : inout AxisStreamType := AxisInput;    --! Host Replies input stream
+       stream2Out      : inout AxisStreamType := AxisOutput;   --! Host Requests output stream
+
+       stream3In       : inout AxisStreamType := AxisInput;    --! Nvme Requests input stream
+       stream3Out      : inout AxisStreamType := AxisOutput    --! Nvme replies output stream
+);
+end component;
+
+component Fifo4k
+port (
+       clk : in std_logic;
+       srst : in std_logic;
+       din : in std_logic_vector(127 downto 0);
+       wr_en : in std_logic;
+       rd_en : in std_logic;
+       dout : out std_logic_vector(127 downto 0);
+       almost_full : out std_logic;
+       full : out std_logic;
+       empty : out std_logic;
+       valid : out std_logic;
+       wr_rst_busy : out std_logic;
+       rd_rst_busy : out std_logic;
+       data_count : out std_logic_vector(8 downto 0)
+);
+end component;
+
+constant TCQ           : time := 1 ns;
+constant CHUNK_SIZE    : integer := 32;                        -- The data write chunk size in DWords due to PCIe packet size limitations
+
+signal clk             : std_logic := '0';
+signal reset           : std_logic := '0';
+
+signal axil            : AxilBusType;
+signal hostSend                : AxisStreamType        := AxisOutput;
+signal hostRecv                : AxisStreamType        := AxisInput;
+
+signal leds            : std_logic_vector(3 downto 0);
+
+signal hostReply       : AxisStreamType        := AxisInput;
+signal hostReq         : AxisStreamType        := AxisOutput;
+signal nvmeReq         : AxisStreamType        := AxisInput;
+signal nvmeReply       : AxisStreamType        := AxisOutput;
+
+type NvmeStateType is (NVME_STATE_IDLE, NVME_STATE_WRITEDATA, NVME_STATE_READDATA_START, NVME_STATE_READDATA);
+signal nvmeState       : NvmeStateType := NVME_STATE_IDLE;
+signal nvmeRequestHead : PcieRequestHeadType;
+signal nvmeRequestHead1        : PcieRequestHeadType;
+signal nvmeReplyHead   : PcieReplyHeadType;
+signal nvmeCount       : unsigned(10 downto 0);                        -- DWord data send count
+signal nvmeChunkCount  : unsigned(10 downto 0);                        -- DWord data send within a chunk count
+signal nvmeByteCount   : integer;
+signal nvmeData                : std_logic_vector(127 downto 0);
+
+signal sendData                : std_logic := '0';
+
+signal fifo_wr_en      : std_logic := '0';
+signal fifo_wr_rst_busy        : std_logic := '0';
+signal fifo_rd_en      : std_logic := '0';
+signal fifo_full       : std_logic := '0';
+signal fifo_full1      : std_logic := '0';
+signal fifo_almost_full        : std_logic := '0';
+signal fifo_data_count : std_logic_vector(8 downto 0);
+signal fifo_empty      : std_logic := '0';
+signal fifo_valid      : std_logic := '0';
+signal fifo_dataIn     : unsigned(127 downto 0) := (others => '0');
+signal fifo_dataOut    : std_logic_vector(127 downto 0) := (others => '0');
+signal fifo_start_read : std_logic := '0';
+signal fifo_start_write        : std_logic := '0';
+
+
+begin
+       hostReply.ready <= '1';
+       
+       NvmeStorageUnit0 : NvmeStorageUnit
+       port map (
+               clk             => clk,
+               reset           => reset,
+
+               axilIn          => axil.toSlave,
+               axilOut         => axil.toMaster,
+
+               hostSend        => hostSend,
+               hostRecv        => hostRecv,
+
+               -- NVMe interface
+               nvme_clk_p      => '0',
+               nvme_clk_n      => '0',
+               --nvme_exp_txp  : out std_logic_vector(0 downto 0);
+               --nvme_exp_txn  : out std_logic_vector(0 downto 0);
+               nvme_exp_rxp    => "0000",
+               nvme_exp_rxn    => "0000",
+
+               leds            => leds
+       );
+
+       clock : process
+       begin
+               wait for 5 ns; clk  <= not clk;
+       end process clock;
+
+       init : process
+       begin
+               reset   <= '1';
+               wait for 20 ns;
+               reset   <= '0';
+               wait;
+       end process;
+
+       fifo_full1 <= '1' when(unsigned(fifo_data_count) >= 256) else '0';
+
+       fifo0: Fifo4k
+       port map (
+               clk             => clk,
+               srst            => reset,
+               din             => std_logic_vector(fifo_dataIn),
+               wr_en           => fifo_wr_en,
+               rd_en           => fifo_rd_en,
+               dout            => fifo_dataOut,
+               almost_full     => fifo_almost_full,
+               full            => fifo_full,
+               empty           => fifo_empty,
+               valid           => fifo_valid,
+               wr_rst_busy     => fifo_wr_rst_busy,
+               --rd_rst_busy   =>
+               data_count      => fifo_data_count
+       );
+
+       runFifo : process(clk)
+       begin
+               if(rising_edge(clk)) then
+                       if(reset = '1') then
+                               fifo_wr_en              <= '0';
+                               --fifo_rd_en            <= '0';
+                               fifo_dataIn             <= (others => '0');
+                               fifo_start_write        <= '1';
+                               fifo_start_read         <= '0';
+                       else
+                               if(fifo_wr_en = '1') then
+                                       if(fifo_full = '1') then
+                                               fifo_wr_en      <= '0';
+                                               fifo_start_read <= '1';
+                                       else
+                                               fifo_dataIn <= fifo_dataIn + 1;
+                                       end if;
+                               end if;
+                               
+                               if(fifo_start_write = '1') then
+                                       if(fifo_wr_en = '0') then
+                                               fifo_wr_en      <= '1';
+                                       else
+                                               --fifo_wr_en    <= '0';
+                                       end if;
+                               end if;
+
+                               --if(fifo_start_read = '1') then
+                               --      fifo_rd_en      <= '1';
+                               --      fifo_start_read <= '0';
+                               --end if;
+                       end if;
+               end if;
+       end process;
+
+       runFifoRead : process
+       begin
+               fifo_rd_en              <= '0';
+               wait until fifo_start_read = '1';
+               wait until rising_edge(clk);
+               wait until rising_edge(clk);
+               
+               while true loop
+                       fifo_rd_en      <= '1';
+                       wait until rising_edge(clk) and fifo_valid = '1';
+                       wait until rising_edge(clk) and fifo_valid = '1';
+                       fifo_rd_en      <= '0';
+                       wait until rising_edge(clk);
+                       wait until rising_edge(clk);
+                       wait until rising_edge(clk);
+               end loop;
+       end process;
+       
+       run : process
+       begin
+               wait;
+               wait until reset = '0';
+               --wait for 1000 ns;
+               
+               -- Perform local reset
+               busWrite(clk, axil.toSlave, axil.toMaster, 4, 16#00000001#);
+               wait for 1000 ns;
+
+               -- Set PCIe configuration command register to 0x06
+               --pcieRequestWrite(clk, hostReq, 1, 10, 4, 16#44#, 1, 16#00100006#);
+               
+               -- Read PCIe configuration command register
+               --pcieRequestRead(clk, hostReq, 1, 8, 4, 16#55#, 1);
+               
+               -- Test Mux with Write to Nvmeregister 0
+               --pcieRequestWrite(clk, hostReq, 1, 1, 16#0000#, 16#22#, 1, 16#40#);
+
+               -- Write to AdminQueue doorbell register
+               --pcieRequestWrite(clk, hostReq, 1, 1, 16#1000#, 16#22#, 1, 16#40#);
+
+               -- Write to AdminQueue
+               --pcieRequestWrite(clk, hostReq, 1, 1, 16#05000000#, 16#22#, 16, 16#00000010#);
+
+               -- Write to DataQueue
+               pcieRequestWrite(clk, hostReq, 1, 1, 16#05010000#, 16#22#, 16, 16#00000010#);
+
+               -- Perform NVMe data write
+               -- Write to DataWriteQueue doorbell register
+               --pcieRequestWrite(clk, hostReq, 1, 1, 16#1008#, 16#23#, 1, 16#40#);
+               wait;
+       end process;
+       
+       -- Host to Nvme stream Mux/DeMux
+       nvmeStreamMux0 : NvmeStreamMux
+       port map (
+               clk             => clk,
+               reset           => reset,
+
+               stream1In       => hostRecv,
+               stream1Out      => hostSend,
+               
+               stream2In       => nvmeReply,
+               stream2Out      => nvmeReq,
+
+               stream3In       => hostReq,
+               stream3Out      => hostReply
+       );
+
+
+       nvmeRequestHead <= to_PcieRequestHeadType(nvmeReq.data);
+       nvmeReply.data <= nvmeData when(nvmeState = NVME_STATE_READDATA) else concat('0', 32) & to_stl(nvmeReplyHead);
+       
+       requests : process(clk)
+       begin
+               if(rising_edge(clk)) then
+                       if(reset = '1') then
+                               nvmeReq.ready   <= '0';
+                               nvmeReply.valid <= '0';
+                               nvmeReply.last  <= '0';
+                               nvmeReply.keep  <= (others => '1');
+                               nvmeData        <= (others => '0');
+                               nvmeState       <= NVME_STATE_IDLE;
+                       else
+                               case (nvmeState) is
+                               when NVME_STATE_IDLE =>
+                                       if(nvmeReq.ready = '1' and nvmeReq.valid = '1') then
+                                               nvmeRequestHead1        <= nvmeRequestHead;
+                                               nvmeCount               <= nvmeRequestHead.count;
+
+                                               if(nvmeRequestHead.request = 1) then
+                                                       nvmeState <= NVME_STATE_WRITEDATA;
+                                               elsif(nvmeRequestHead.request = 0) then
+                                                       nvmeState <= NVME_STATE_READDATA_START;
+                                               end if;
+                                       else
+                                               nvmeReq.ready <= '1';
+                                       end if;
+
+                               when NVME_STATE_WRITEDATA =>
+                                       if((nvmeReq.ready = '1') and (nvmeReq.valid = '1') and (nvmeReq.last = '1')) then
+                                               nvmeState <= NVME_STATE_IDLE;
+                                       end if;
+                               
+                               
+                               when NVME_STATE_READDATA_START =>
+                                       nvmeReq.ready                   <= '0';
+                                       nvmeReplyHead.byteCount         <= nvmeRequestHead1.count & "00";
+                                       nvmeReplyHead.address           <= nvmeRequestHead1.address(nvmeReplyHead.address'length - 1 downto 0);
+                                       nvmeReplyHead.error             <= (others => '0');
+                                       nvmeReplyHead.status            <= (others => '0');
+                                       nvmeReplyHead.tag               <= nvmeRequestHead1.tag;
+                                       nvmeReplyHead.requesterId       <= nvmeRequestHead1.requesterId;
+
+                                       if(nvmeCount > CHUNK_SIZE) then
+                                               nvmeReplyHead.count     <= to_unsigned(CHUNK_SIZE-1, nvmeReplyHead.count'length);
+                                               nvmeChunkCount          <= to_unsigned(CHUNK_SIZE, nvmeReplyHead.count'length);
+                                       else
+                                               nvmeReplyHead.count     <= nvmeCount - 1;
+                                               nvmeChunkCount          <= nvmeCount;
+                                       end if;
+
+                                       nvmeByteCount           <= (to_integer(nvmeRequestHead1.count) + 1) * 4;
+                                       nvmeReply.valid         <= '1';
+
+                                       if(nvmeReply.ready = '1' and nvmeReply.valid = '1') then
+                                               nvmeData        <= std_logic_vector(unsigned(nvmeData) + 1);
+                                               nvmeState       <= NVME_STATE_READDATA;
+                                       end if;
+
+                               when NVME_STATE_READDATA =>
+                                       if(nvmeReply.ready = '1' and nvmeReply.valid = '1') then
+                                               nvmeData        <= std_logic_vector(unsigned(nvmeData) + 1);
+                                               if(nvmeChunkCount = 4) then
+                                                       if(nvmeCount = 4) then
+                                                               nvmeReply.valid <= '0';
+                                                               nvmeReply.last  <= '0';
+                                                               nvmeState       <= NVME_STATE_IDLE;
+                                                       else
+                                                               nvmeReply.last  <= '0';
+                                                               nvmeState       <= NVME_STATE_READDATA_START;
+                                                       end if;
+                                               elsif(nvmeChunkCount = 8) then
+                                                       nvmeReply.last <= '1';
+                                               else
+                                                       nvmeReply.last <= '0';
+                                               end if;
+                                               nvmeChunkCount  <= nvmeChunkCount - 4;
+                                               nvmeCount       <= nvmeCount - 4;
+                                       end if;
+                               end case;
+                       end if;
+               end if;
+       end process;
+
+       stop : process
+       begin
+               wait for 10000 ns;
+               assert false report "simulation ended ok" severity failure;
+       end process;
+end;
diff --git a/source/DuneNvme/sim/testbench/test017-write.sav b/source/DuneNvme/sim/testbench/test017-write.sav
new file mode 100644 (file)
index 0000000..bc68b3e
--- /dev/null
@@ -0,0 +1,221 @@
+[*]
+[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI
+[*] Wed Apr 29 07:52:26 2020
+[*]
+[dumpfile] "/src/dune/FpgaPlay/test020-nvmeprocess/sim/simu/test.ghw"
+[dumpfile_mtime] "Wed Apr 29 07:50:34 2020"
+[dumpfile_size] 3605877
+[savefile] "/src/dune/FpgaPlay/test020-nvmeprocess/sim/testbench/test017-write.sav"
+[timestart] 4100000
+[size] 1920 1171
+[pos] -1 -1
+*-26.418455 509500000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+[treeopen] top.
+[treeopen] top.test.
+[treeopen] top.test.axil.
+[treeopen] top.test.axil.tomaster.
+[treeopen] top.test.hostrecv.
+[treeopen] top.test.hostsend.
+[treeopen] top.test.nvmereq.
+[treeopen] top.test.nvmestorageunit0.gen03.
+[treeopen] top.test.nvmestorageunit0.gen03.nvmequeues0.
+[treeopen] top.test.nvmestorageunit0.gen03.nvmequeues0.queueinarraypos.
+[treeopen] top.test.nvmestorageunit0.gen03.nvmequeues0.ram.
+[treeopen] top.test.nvmestorageunit0.gen03.nvmequeues0.requesthead1.
+[treeopen] top.test.nvmestorageunit0.gen03.nvmewrite0.
+[treeopen] top.test.nvmestorageunit0.gen03.nvmewrite0.datafifo0.
+[treeopen] top.test.nvmestorageunit0.gen03.nvmewrite0.datafifo0.datain.
+[treeopen] top.test.nvmestorageunit0.gen03.nvmewrite0.datafifo0.dataout.
+[treeopen] top.test.nvmestorageunit0.gen03.nvmewrite0.memreplyout.
+[treeopen] top.test.nvmestorageunit0.gen03.nvmewrite0.memreqin.
+[treeopen] top.test.nvmestorageunit0.gen03.nvmewrite0.replyin.
+[treeopen] top.test.nvmestorageunit0.gen03.nvmewrite0.requestout.
+[treeopen] top.test.nvmestorageunit0.gen03.streamswitch0.
+[treeopen] top.test.nvmestorageunit0.gen03.streamswitch0.streamin.
+[treeopen] top.test.nvmestorageunit0.gen03.streamswitch0.streamin.[0].
+[treeopen] top.test.nvmestorageunit0.gen03.streamswitch0.streamout.
+[treeopen] top.test.nvmestorageunit0.gen03.streamswitch0.streamout.[0].
+[treeopen] top.test.nvmestorageunit0.sim.
+[treeopen] top.test.nvmestorageunit0.sim.nvmesim0.nvmereply.
+[treeopen] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.
+[treeopen] top.test.nvmestorageunit0.streamrecv.[0].
+[treeopen] top.test.nvmestorageunit0.streamrecv.[1].
+[treeopen] top.test.nvmestorageunit0.streamrecv.[2].
+[treeopen] top.test.nvmestorageunit0.streamsend.[0].
+[treeopen] top.test.nvmestorageunit0.streamsend.[2].
+[treeopen] top.test.testdata0.
+[sst_width] 294
+[signals_width] 622
+[sst_expanded] 1
+[sst_vpaned_height] 768
+@28
+top.test.clk
+top.test.reset
+@c00200
+-ResetLocal
+@28
+top.test.nvmestorageunit0.reset_local_run
+top.test.nvmestorageunit0.reset_local_done
+top.test.nvmestorageunit0.reset_local_active
+@420
+top.test.nvmestorageunit0.reset_local_counter
+@28
+top.test.nvmestorageunit0.reset_local
+@1401200
+-ResetLocal
+@800200
+-Host
+@28
+top.test.hostsend.ready
+top.test.hostsend.valid
+top.test.hostsend.last
+@22
+#{top.test.hostsend.keep[15:0]} top.test.hostsend.keep[15] top.test.hostsend.keep[14] top.test.hostsend.keep[13] top.test.hostsend.keep[12] top.test.hostsend.keep[11] top.test.hostsend.keep[10] top.test.hostsend.keep[9] top.test.hostsend.keep[8] top.test.hostsend.keep[7] top.test.hostsend.keep[6] top.test.hostsend.keep[5] top.test.hostsend.keep[4] top.test.hostsend.keep[3] top.test.hostsend.keep[2] top.test.hostsend.keep[1] top.test.hostsend.keep[0]
+#{top.test.hostsend.data[127:0]} top.test.hostsend.data[127] top.test.hostsend.data[126] top.test.hostsend.data[125] top.test.hostsend.data[124] top.test.hostsend.data[123] top.test.hostsend.data[122] top.test.hostsend.data[121] top.test.hostsend.data[120] top.test.hostsend.data[119] top.test.hostsend.data[118] top.test.hostsend.data[117] top.test.hostsend.data[116] top.test.hostsend.data[115] top.test.hostsend.data[114] top.test.hostsend.data[113] top.test.hostsend.data[112] top.test.hostsend.data[111] top.test.hostsend.data[110] top.test.hostsend.data[109] top.test.hostsend.data[108] top.test.hostsend.data[107] top.test.hostsend.data[106] top.test.hostsend.data[105] top.test.hostsend.data[104] top.test.hostsend.data[103] top.test.hostsend.data[102] top.test.hostsend.data[101] top.test.hostsend.data[100] top.test.hostsend.data[99] top.test.hostsend.data[98] top.test.hostsend.data[97] top.test.hostsend.data[96] top.test.hostsend.data[95] top.test.hostsend.data[94] top.test.hostsend.data[93] top.test.hostsend.data[92] top.test.hostsend.data[91] top.test.hostsend.data[90] top.test.hostsend.data[89] top.test.hostsend.data[88] top.test.hostsend.data[87] top.test.hostsend.data[86] top.test.hostsend.data[85] top.test.hostsend.data[84] top.test.hostsend.data[83] top.test.hostsend.data[82] top.test.hostsend.data[81] top.test.hostsend.data[80] top.test.hostsend.data[79] top.test.hostsend.data[78] top.test.hostsend.data[77] top.test.hostsend.data[76] top.test.hostsend.data[75] top.test.hostsend.data[74] top.test.hostsend.data[73] top.test.hostsend.data[72] top.test.hostsend.data[71] top.test.hostsend.data[70] top.test.hostsend.data[69] top.test.hostsend.data[68] top.test.hostsend.data[67] top.test.hostsend.data[66] top.test.hostsend.data[65] top.test.hostsend.data[64] top.test.hostsend.data[63] top.test.hostsend.data[62] top.test.hostsend.data[61] top.test.hostsend.data[60] top.test.hostsend.data[59] top.test.hostsend.data[58] top.test.hostsend.data[57] top.test.hostsend.data[56] top.test.hostsend.data[55] top.test.hostsend.data[54] top.test.hostsend.data[53] top.test.hostsend.data[52] top.test.hostsend.data[51] top.test.hostsend.data[50] top.test.hostsend.data[49] top.test.hostsend.data[48] top.test.hostsend.data[47] top.test.hostsend.data[46] top.test.hostsend.data[45] top.test.hostsend.data[44] top.test.hostsend.data[43] top.test.hostsend.data[42] top.test.hostsend.data[41] top.test.hostsend.data[40] top.test.hostsend.data[39] top.test.hostsend.data[38] top.test.hostsend.data[37] top.test.hostsend.data[36] top.test.hostsend.data[35] top.test.hostsend.data[34] top.test.hostsend.data[33] top.test.hostsend.data[32] top.test.hostsend.data[31] top.test.hostsend.data[30] top.test.hostsend.data[29] top.test.hostsend.data[28] top.test.hostsend.data[27] top.test.hostsend.data[26] top.test.hostsend.data[25] top.test.hostsend.data[24] top.test.hostsend.data[23] top.test.hostsend.data[22] top.test.hostsend.data[21] top.test.hostsend.data[20] top.test.hostsend.data[19] top.test.hostsend.data[18] top.test.hostsend.data[17] top.test.hostsend.data[16] top.test.hostsend.data[15] top.test.hostsend.data[14] top.test.hostsend.data[13] top.test.hostsend.data[12] top.test.hostsend.data[11] top.test.hostsend.data[10] top.test.hostsend.data[9] top.test.hostsend.data[8] top.test.hostsend.data[7] top.test.hostsend.data[6] top.test.hostsend.data[5] top.test.hostsend.data[4] top.test.hostsend.data[3] top.test.hostsend.data[2] top.test.hostsend.data[1] top.test.hostsend.data[0]
+@28
+top.test.hostrecv.ready
+top.test.hostrecv.valid
+top.test.hostrecv.last
+@22
+#{top.test.hostrecv.keep[15:0]} top.test.hostrecv.keep[15] top.test.hostrecv.keep[14] top.test.hostrecv.keep[13] top.test.hostrecv.keep[12] top.test.hostrecv.keep[11] top.test.hostrecv.keep[10] top.test.hostrecv.keep[9] top.test.hostrecv.keep[8] top.test.hostrecv.keep[7] top.test.hostrecv.keep[6] top.test.hostrecv.keep[5] top.test.hostrecv.keep[4] top.test.hostrecv.keep[3] top.test.hostrecv.keep[2] top.test.hostrecv.keep[1] top.test.hostrecv.keep[0]
+#{top.test.hostrecv.data[127:0]} top.test.hostrecv.data[127] top.test.hostrecv.data[126] top.test.hostrecv.data[125] top.test.hostrecv.data[124] top.test.hostrecv.data[123] top.test.hostrecv.data[122] top.test.hostrecv.data[121] top.test.hostrecv.data[120] top.test.hostrecv.data[119] top.test.hostrecv.data[118] top.test.hostrecv.data[117] top.test.hostrecv.data[116] top.test.hostrecv.data[115] top.test.hostrecv.data[114] top.test.hostrecv.data[113] top.test.hostrecv.data[112] top.test.hostrecv.data[111] top.test.hostrecv.data[110] top.test.hostrecv.data[109] top.test.hostrecv.data[108] top.test.hostrecv.data[107] top.test.hostrecv.data[106] top.test.hostrecv.data[105] top.test.hostrecv.data[104] top.test.hostrecv.data[103] top.test.hostrecv.data[102] top.test.hostrecv.data[101] top.test.hostrecv.data[100] top.test.hostrecv.data[99] top.test.hostrecv.data[98] top.test.hostrecv.data[97] top.test.hostrecv.data[96] top.test.hostrecv.data[95] top.test.hostrecv.data[94] top.test.hostrecv.data[93] top.test.hostrecv.data[92] top.test.hostrecv.data[91] top.test.hostrecv.data[90] top.test.hostrecv.data[89] top.test.hostrecv.data[88] top.test.hostrecv.data[87] top.test.hostrecv.data[86] top.test.hostrecv.data[85] top.test.hostrecv.data[84] top.test.hostrecv.data[83] top.test.hostrecv.data[82] top.test.hostrecv.data[81] top.test.hostrecv.data[80] top.test.hostrecv.data[79] top.test.hostrecv.data[78] top.test.hostrecv.data[77] top.test.hostrecv.data[76] top.test.hostrecv.data[75] top.test.hostrecv.data[74] top.test.hostrecv.data[73] top.test.hostrecv.data[72] top.test.hostrecv.data[71] top.test.hostrecv.data[70] top.test.hostrecv.data[69] top.test.hostrecv.data[68] top.test.hostrecv.data[67] top.test.hostrecv.data[66] top.test.hostrecv.data[65] top.test.hostrecv.data[64] top.test.hostrecv.data[63] top.test.hostrecv.data[62] top.test.hostrecv.data[61] top.test.hostrecv.data[60] top.test.hostrecv.data[59] top.test.hostrecv.data[58] top.test.hostrecv.data[57] top.test.hostrecv.data[56] top.test.hostrecv.data[55] top.test.hostrecv.data[54] top.test.hostrecv.data[53] top.test.hostrecv.data[52] top.test.hostrecv.data[51] top.test.hostrecv.data[50] top.test.hostrecv.data[49] top.test.hostrecv.data[48] top.test.hostrecv.data[47] top.test.hostrecv.data[46] top.test.hostrecv.data[45] top.test.hostrecv.data[44] top.test.hostrecv.data[43] top.test.hostrecv.data[42] top.test.hostrecv.data[41] top.test.hostrecv.data[40] top.test.hostrecv.data[39] top.test.hostrecv.data[38] top.test.hostrecv.data[37] top.test.hostrecv.data[36] top.test.hostrecv.data[35] top.test.hostrecv.data[34] top.test.hostrecv.data[33] top.test.hostrecv.data[32] top.test.hostrecv.data[31] top.test.hostrecv.data[30] top.test.hostrecv.data[29] top.test.hostrecv.data[28] top.test.hostrecv.data[27] top.test.hostrecv.data[26] top.test.hostrecv.data[25] top.test.hostrecv.data[24] top.test.hostrecv.data[23] top.test.hostrecv.data[22] top.test.hostrecv.data[21] top.test.hostrecv.data[20] top.test.hostrecv.data[19] top.test.hostrecv.data[18] top.test.hostrecv.data[17] top.test.hostrecv.data[16] top.test.hostrecv.data[15] top.test.hostrecv.data[14] top.test.hostrecv.data[13] top.test.hostrecv.data[12] top.test.hostrecv.data[11] top.test.hostrecv.data[10] top.test.hostrecv.data[9] top.test.hostrecv.data[8] top.test.hostrecv.data[7] top.test.hostrecv.data[6] top.test.hostrecv.data[5] top.test.hostrecv.data[4] top.test.hostrecv.data[3] top.test.hostrecv.data[2] top.test.hostrecv.data[1] top.test.hostrecv.data[0]
+@420
+top.test.nvmestate
+@22
+#{top.test.testdata0.data[31:0]} top.test.testdata0.data[31] top.test.testdata0.data[30] top.test.testdata0.data[29] top.test.testdata0.data[28] top.test.testdata0.data[27] top.test.testdata0.data[26] top.test.testdata0.data[25] top.test.testdata0.data[24] top.test.testdata0.data[23] top.test.testdata0.data[22] top.test.testdata0.data[21] top.test.testdata0.data[20] top.test.testdata0.data[19] top.test.testdata0.data[18] top.test.testdata0.data[17] top.test.testdata0.data[16] top.test.testdata0.data[15] top.test.testdata0.data[14] top.test.testdata0.data[13] top.test.testdata0.data[12] top.test.testdata0.data[11] top.test.testdata0.data[10] top.test.testdata0.data[9] top.test.testdata0.data[8] top.test.testdata0.data[7] top.test.testdata0.data[6] top.test.testdata0.data[5] top.test.testdata0.data[4] top.test.testdata0.data[3] top.test.testdata0.data[2] top.test.testdata0.data[1] top.test.testdata0.data[0]
+@1000200
+-Host
+@800200
+-Registers
+@22
+#{top.test.nvmestorageunit0.reg_control[31:0]} top.test.nvmestorageunit0.reg_control[31] top.test.nvmestorageunit0.reg_control[30] top.test.nvmestorageunit0.reg_control[29] top.test.nvmestorageunit0.reg_control[28] top.test.nvmestorageunit0.reg_control[27] top.test.nvmestorageunit0.reg_control[26] top.test.nvmestorageunit0.reg_control[25] top.test.nvmestorageunit0.reg_control[24] top.test.nvmestorageunit0.reg_control[23] top.test.nvmestorageunit0.reg_control[22] top.test.nvmestorageunit0.reg_control[21] top.test.nvmestorageunit0.reg_control[20] top.test.nvmestorageunit0.reg_control[19] top.test.nvmestorageunit0.reg_control[18] top.test.nvmestorageunit0.reg_control[17] top.test.nvmestorageunit0.reg_control[16] top.test.nvmestorageunit0.reg_control[15] top.test.nvmestorageunit0.reg_control[14] top.test.nvmestorageunit0.reg_control[13] top.test.nvmestorageunit0.reg_control[12] top.test.nvmestorageunit0.reg_control[11] top.test.nvmestorageunit0.reg_control[10] top.test.nvmestorageunit0.reg_control[9] top.test.nvmestorageunit0.reg_control[8] top.test.nvmestorageunit0.reg_control[7] top.test.nvmestorageunit0.reg_control[6] top.test.nvmestorageunit0.reg_control[5] top.test.nvmestorageunit0.reg_control[4] top.test.nvmestorageunit0.reg_control[3] top.test.nvmestorageunit0.reg_control[2] top.test.nvmestorageunit0.reg_control[1] top.test.nvmestorageunit0.reg_control[0]
+@28
+top.test.axil.toslave.arvalid
+top.test.axil.toslave.rready
+top.test.axil.tomaster.rvalid
+@22
+#{top.test.axil.tomaster.rdata[31:0]} top.test.axil.tomaster.rdata[31] top.test.axil.tomaster.rdata[30] top.test.axil.tomaster.rdata[29] top.test.axil.tomaster.rdata[28] top.test.axil.tomaster.rdata[27] top.test.axil.tomaster.rdata[26] top.test.axil.tomaster.rdata[25] top.test.axil.tomaster.rdata[24] top.test.axil.tomaster.rdata[23] top.test.axil.tomaster.rdata[22] top.test.axil.tomaster.rdata[21] top.test.axil.tomaster.rdata[20] top.test.axil.tomaster.rdata[19] top.test.axil.tomaster.rdata[18] top.test.axil.tomaster.rdata[17] top.test.axil.tomaster.rdata[16] top.test.axil.tomaster.rdata[15] top.test.axil.tomaster.rdata[14] top.test.axil.tomaster.rdata[13] top.test.axil.tomaster.rdata[12] top.test.axil.tomaster.rdata[11] top.test.axil.tomaster.rdata[10] top.test.axil.tomaster.rdata[9] top.test.axil.tomaster.rdata[8] top.test.axil.tomaster.rdata[7] top.test.axil.tomaster.rdata[6] top.test.axil.tomaster.rdata[5] top.test.axil.tomaster.rdata[4] top.test.axil.tomaster.rdata[3] top.test.axil.tomaster.rdata[2] top.test.axil.tomaster.rdata[1] top.test.axil.tomaster.rdata[0]
+@1000200
+-Registers
+@c00200
+-Switch
+@28
+top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].valid
+@22
+#{top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[127:0]} top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[127] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[126] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[125] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[124] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[123] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[122] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[121] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[120] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[119] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[118] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[117] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[116] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[115] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[114] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[113] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[112] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[111] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[110] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[109] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[108] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[107] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[106] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[105] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[104] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[103] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[102] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[101] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[100] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[99] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[98] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[97] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[96] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[95] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[94] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[93] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[92] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[91] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[90] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[89] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[88] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[87] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[86] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[85] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[84] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[83] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[82] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[81] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[80] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[79] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[78] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[77] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[76] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[75] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[74] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[73] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[72] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[71] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[70] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[69] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[68] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[67] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[66] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[65] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[64] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[63] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[62] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[61] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[60] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[59] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[58] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[57] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[56] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[55] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[54] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[53] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[52] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[51] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[50] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[49] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[48] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[47] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[46] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[45] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[44] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[43] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[42] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[41] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[40] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[39] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[38] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[37] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[36] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[35] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[34] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[33] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[32] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[31] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[30] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[29] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[28] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[27] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[26] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[25] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[24] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[23] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[22] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[21] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[20] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[19] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[18] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[17] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[16] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[15] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[14] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[13] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[12] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[11] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[10] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[9] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[8] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[7] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[6] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[5] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[4] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[3] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[2] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[1] top.test.nvmestorageunit0.gen03.streamswitch0.streamin[0].data[0]
+@28
+top.test.nvmestorageunit0.gen03.streamswitch0.streamout[0].ready
+top.test.nvmestorageunit0.gen03.streamswitch0.streamin[1].valid
+top.test.nvmestorageunit0.gen03.streamswitch0.streamout[1].ready
+top.test.nvmestorageunit0.gen03.streamswitch0.streamin[2].valid
+top.test.nvmestorageunit0.gen03.streamswitch0.streamout[2].ready
+@420
+top.test.nvmestorageunit0.gen03.streamswitch0.switchstate
+top.test.nvmestorageunit0.gen03.streamswitch0.switchin
+top.test.nvmestorageunit0.gen03.streamswitch0.switchout
+@1401200
+-Switch
+@800200
+-QueueRam
+@420
+top.test.nvmestorageunit0.gen03.nvmequeues0.state
+@28
+top.test.nvmestorageunit0.streamrecv[2].ready
+top.test.nvmestorageunit0.streamrecv[2].valid
+top.test.nvmestorageunit0.streamrecv[2].last
+@22
+#{top.test.nvmestorageunit0.streamrecv[2].data[127:0]} top.test.nvmestorageunit0.streamrecv[2].data[127] top.test.nvmestorageunit0.streamrecv[2].data[126] top.test.nvmestorageunit0.streamrecv[2].data[125] top.test.nvmestorageunit0.streamrecv[2].data[124] top.test.nvmestorageunit0.streamrecv[2].data[123] top.test.nvmestorageunit0.streamrecv[2].data[122] top.test.nvmestorageunit0.streamrecv[2].data[121] top.test.nvmestorageunit0.streamrecv[2].data[120] top.test.nvmestorageunit0.streamrecv[2].data[119] top.test.nvmestorageunit0.streamrecv[2].data[118] top.test.nvmestorageunit0.streamrecv[2].data[117] top.test.nvmestorageunit0.streamrecv[2].data[116] top.test.nvmestorageunit0.streamrecv[2].data[115] top.test.nvmestorageunit0.streamrecv[2].data[114] top.test.nvmestorageunit0.streamrecv[2].data[113] top.test.nvmestorageunit0.streamrecv[2].data[112] top.test.nvmestorageunit0.streamrecv[2].data[111] top.test.nvmestorageunit0.streamrecv[2].data[110] top.test.nvmestorageunit0.streamrecv[2].data[109] top.test.nvmestorageunit0.streamrecv[2].data[108] top.test.nvmestorageunit0.streamrecv[2].data[107] top.test.nvmestorageunit0.streamrecv[2].data[106] top.test.nvmestorageunit0.streamrecv[2].data[105] top.test.nvmestorageunit0.streamrecv[2].data[104] top.test.nvmestorageunit0.streamrecv[2].data[103] top.test.nvmestorageunit0.streamrecv[2].data[102] top.test.nvmestorageunit0.streamrecv[2].data[101] top.test.nvmestorageunit0.streamrecv[2].data[100] top.test.nvmestorageunit0.streamrecv[2].data[99] top.test.nvmestorageunit0.streamrecv[2].data[98] top.test.nvmestorageunit0.streamrecv[2].data[97] top.test.nvmestorageunit0.streamrecv[2].data[96] top.test.nvmestorageunit0.streamrecv[2].data[95] top.test.nvmestorageunit0.streamrecv[2].data[94] top.test.nvmestorageunit0.streamrecv[2].data[93] top.test.nvmestorageunit0.streamrecv[2].data[92] top.test.nvmestorageunit0.streamrecv[2].data[91] top.test.nvmestorageunit0.streamrecv[2].data[90] top.test.nvmestorageunit0.streamrecv[2].data[89] top.test.nvmestorageunit0.streamrecv[2].data[88] top.test.nvmestorageunit0.streamrecv[2].data[87] top.test.nvmestorageunit0.streamrecv[2].data[86] top.test.nvmestorageunit0.streamrecv[2].data[85] top.test.nvmestorageunit0.streamrecv[2].data[84] top.test.nvmestorageunit0.streamrecv[2].data[83] top.test.nvmestorageunit0.streamrecv[2].data[82] top.test.nvmestorageunit0.streamrecv[2].data[81] top.test.nvmestorageunit0.streamrecv[2].data[80] top.test.nvmestorageunit0.streamrecv[2].data[79] top.test.nvmestorageunit0.streamrecv[2].data[78] top.test.nvmestorageunit0.streamrecv[2].data[77] top.test.nvmestorageunit0.streamrecv[2].data[76] top.test.nvmestorageunit0.streamrecv[2].data[75] top.test.nvmestorageunit0.streamrecv[2].data[74] top.test.nvmestorageunit0.streamrecv[2].data[73] top.test.nvmestorageunit0.streamrecv[2].data[72] top.test.nvmestorageunit0.streamrecv[2].data[71] top.test.nvmestorageunit0.streamrecv[2].data[70] top.test.nvmestorageunit0.streamrecv[2].data[69] top.test.nvmestorageunit0.streamrecv[2].data[68] top.test.nvmestorageunit0.streamrecv[2].data[67] top.test.nvmestorageunit0.streamrecv[2].data[66] top.test.nvmestorageunit0.streamrecv[2].data[65] top.test.nvmestorageunit0.streamrecv[2].data[64] top.test.nvmestorageunit0.streamrecv[2].data[63] top.test.nvmestorageunit0.streamrecv[2].data[62] top.test.nvmestorageunit0.streamrecv[2].data[61] top.test.nvmestorageunit0.streamrecv[2].data[60] top.test.nvmestorageunit0.streamrecv[2].data[59] top.test.nvmestorageunit0.streamrecv[2].data[58] top.test.nvmestorageunit0.streamrecv[2].data[57] top.test.nvmestorageunit0.streamrecv[2].data[56] top.test.nvmestorageunit0.streamrecv[2].data[55] top.test.nvmestorageunit0.streamrecv[2].data[54] top.test.nvmestorageunit0.streamrecv[2].data[53] top.test.nvmestorageunit0.streamrecv[2].data[52] top.test.nvmestorageunit0.streamrecv[2].data[51] top.test.nvmestorageunit0.streamrecv[2].data[50] top.test.nvmestorageunit0.streamrecv[2].data[49] top.test.nvmestorageunit0.streamrecv[2].data[48] top.test.nvmestorageunit0.streamrecv[2].data[47] top.test.nvmestorageunit0.streamrecv[2].data[46] top.test.nvmestorageunit0.streamrecv[2].data[45] top.test.nvmestorageunit0.streamrecv[2].data[44] top.test.nvmestorageunit0.streamrecv[2].data[43] top.test.nvmestorageunit0.streamrecv[2].data[42] top.test.nvmestorageunit0.streamrecv[2].data[41] top.test.nvmestorageunit0.streamrecv[2].data[40] top.test.nvmestorageunit0.streamrecv[2].data[39] top.test.nvmestorageunit0.streamrecv[2].data[38] top.test.nvmestorageunit0.streamrecv[2].data[37] top.test.nvmestorageunit0.streamrecv[2].data[36] top.test.nvmestorageunit0.streamrecv[2].data[35] top.test.nvmestorageunit0.streamrecv[2].data[34] top.test.nvmestorageunit0.streamrecv[2].data[33] top.test.nvmestorageunit0.streamrecv[2].data[32] top.test.nvmestorageunit0.streamrecv[2].data[31] top.test.nvmestorageunit0.streamrecv[2].data[30] top.test.nvmestorageunit0.streamrecv[2].data[29] top.test.nvmestorageunit0.streamrecv[2].data[28] top.test.nvmestorageunit0.streamrecv[2].data[27] top.test.nvmestorageunit0.streamrecv[2].data[26] top.test.nvmestorageunit0.streamrecv[2].data[25] top.test.nvmestorageunit0.streamrecv[2].data[24] top.test.nvmestorageunit0.streamrecv[2].data[23] top.test.nvmestorageunit0.streamrecv[2].data[22] top.test.nvmestorageunit0.streamrecv[2].data[21] top.test.nvmestorageunit0.streamrecv[2].data[20] top.test.nvmestorageunit0.streamrecv[2].data[19] top.test.nvmestorageunit0.streamrecv[2].data[18] top.test.nvmestorageunit0.streamrecv[2].data[17] top.test.nvmestorageunit0.streamrecv[2].data[16] top.test.nvmestorageunit0.streamrecv[2].data[15] top.test.nvmestorageunit0.streamrecv[2].data[14] top.test.nvmestorageunit0.streamrecv[2].data[13] top.test.nvmestorageunit0.streamrecv[2].data[12] top.test.nvmestorageunit0.streamrecv[2].data[11] top.test.nvmestorageunit0.streamrecv[2].data[10] top.test.nvmestorageunit0.streamrecv[2].data[9] top.test.nvmestorageunit0.streamrecv[2].data[8] top.test.nvmestorageunit0.streamrecv[2].data[7] top.test.nvmestorageunit0.streamrecv[2].data[6] top.test.nvmestorageunit0.streamrecv[2].data[5] top.test.nvmestorageunit0.streamrecv[2].data[4] top.test.nvmestorageunit0.streamrecv[2].data[3] top.test.nvmestorageunit0.streamrecv[2].data[2] top.test.nvmestorageunit0.streamrecv[2].data[1] top.test.nvmestorageunit0.streamrecv[2].data[0]
+@28
+top.test.nvmestorageunit0.streamsend[2].ready
+top.test.nvmestorageunit0.streamsend[2].valid
+top.test.nvmestorageunit0.streamsend[2].last
+@22
+#{top.test.nvmestorageunit0.streamsend[2].data[127:0]} top.test.nvmestorageunit0.streamsend[2].data[127] top.test.nvmestorageunit0.streamsend[2].data[126] top.test.nvmestorageunit0.streamsend[2].data[125] top.test.nvmestorageunit0.streamsend[2].data[124] top.test.nvmestorageunit0.streamsend[2].data[123] top.test.nvmestorageunit0.streamsend[2].data[122] top.test.nvmestorageunit0.streamsend[2].data[121] top.test.nvmestorageunit0.streamsend[2].data[120] top.test.nvmestorageunit0.streamsend[2].data[119] top.test.nvmestorageunit0.streamsend[2].data[118] top.test.nvmestorageunit0.streamsend[2].data[117] top.test.nvmestorageunit0.streamsend[2].data[116] top.test.nvmestorageunit0.streamsend[2].data[115] top.test.nvmestorageunit0.streamsend[2].data[114] top.test.nvmestorageunit0.streamsend[2].data[113] top.test.nvmestorageunit0.streamsend[2].data[112] top.test.nvmestorageunit0.streamsend[2].data[111] top.test.nvmestorageunit0.streamsend[2].data[110] top.test.nvmestorageunit0.streamsend[2].data[109] top.test.nvmestorageunit0.streamsend[2].data[108] top.test.nvmestorageunit0.streamsend[2].data[107] top.test.nvmestorageunit0.streamsend[2].data[106] top.test.nvmestorageunit0.streamsend[2].data[105] top.test.nvmestorageunit0.streamsend[2].data[104] top.test.nvmestorageunit0.streamsend[2].data[103] top.test.nvmestorageunit0.streamsend[2].data[102] top.test.nvmestorageunit0.streamsend[2].data[101] top.test.nvmestorageunit0.streamsend[2].data[100] top.test.nvmestorageunit0.streamsend[2].data[99] top.test.nvmestorageunit0.streamsend[2].data[98] top.test.nvmestorageunit0.streamsend[2].data[97] top.test.nvmestorageunit0.streamsend[2].data[96] top.test.nvmestorageunit0.streamsend[2].data[95] top.test.nvmestorageunit0.streamsend[2].data[94] top.test.nvmestorageunit0.streamsend[2].data[93] top.test.nvmestorageunit0.streamsend[2].data[92] top.test.nvmestorageunit0.streamsend[2].data[91] top.test.nvmestorageunit0.streamsend[2].data[90] top.test.nvmestorageunit0.streamsend[2].data[89] top.test.nvmestorageunit0.streamsend[2].data[88] top.test.nvmestorageunit0.streamsend[2].data[87] top.test.nvmestorageunit0.streamsend[2].data[86] top.test.nvmestorageunit0.streamsend[2].data[85] top.test.nvmestorageunit0.streamsend[2].data[84] top.test.nvmestorageunit0.streamsend[2].data[83] top.test.nvmestorageunit0.streamsend[2].data[82] top.test.nvmestorageunit0.streamsend[2].data[81] top.test.nvmestorageunit0.streamsend[2].data[80] top.test.nvmestorageunit0.streamsend[2].data[79] top.test.nvmestorageunit0.streamsend[2].data[78] top.test.nvmestorageunit0.streamsend[2].data[77] top.test.nvmestorageunit0.streamsend[2].data[76] top.test.nvmestorageunit0.streamsend[2].data[75] top.test.nvmestorageunit0.streamsend[2].data[74] top.test.nvmestorageunit0.streamsend[2].data[73] top.test.nvmestorageunit0.streamsend[2].data[72] top.test.nvmestorageunit0.streamsend[2].data[71] top.test.nvmestorageunit0.streamsend[2].data[70] top.test.nvmestorageunit0.streamsend[2].data[69] top.test.nvmestorageunit0.streamsend[2].data[68] top.test.nvmestorageunit0.streamsend[2].data[67] top.test.nvmestorageunit0.streamsend[2].data[66] top.test.nvmestorageunit0.streamsend[2].data[65] top.test.nvmestorageunit0.streamsend[2].data[64] top.test.nvmestorageunit0.streamsend[2].data[63] top.test.nvmestorageunit0.streamsend[2].data[62] top.test.nvmestorageunit0.streamsend[2].data[61] top.test.nvmestorageunit0.streamsend[2].data[60] top.test.nvmestorageunit0.streamsend[2].data[59] top.test.nvmestorageunit0.streamsend[2].data[58] top.test.nvmestorageunit0.streamsend[2].data[57] top.test.nvmestorageunit0.streamsend[2].data[56] top.test.nvmestorageunit0.streamsend[2].data[55] top.test.nvmestorageunit0.streamsend[2].data[54] top.test.nvmestorageunit0.streamsend[2].data[53] top.test.nvmestorageunit0.streamsend[2].data[52] top.test.nvmestorageunit0.streamsend[2].data[51] top.test.nvmestorageunit0.streamsend[2].data[50] top.test.nvmestorageunit0.streamsend[2].data[49] top.test.nvmestorageunit0.streamsend[2].data[48] top.test.nvmestorageunit0.streamsend[2].data[47] top.test.nvmestorageunit0.streamsend[2].data[46] top.test.nvmestorageunit0.streamsend[2].data[45] top.test.nvmestorageunit0.streamsend[2].data[44] top.test.nvmestorageunit0.streamsend[2].data[43] top.test.nvmestorageunit0.streamsend[2].data[42] top.test.nvmestorageunit0.streamsend[2].data[41] top.test.nvmestorageunit0.streamsend[2].data[40] top.test.nvmestorageunit0.streamsend[2].data[39] top.test.nvmestorageunit0.streamsend[2].data[38] top.test.nvmestorageunit0.streamsend[2].data[37] top.test.nvmestorageunit0.streamsend[2].data[36] top.test.nvmestorageunit0.streamsend[2].data[35] top.test.nvmestorageunit0.streamsend[2].data[34] top.test.nvmestorageunit0.streamsend[2].data[33] top.test.nvmestorageunit0.streamsend[2].data[32] top.test.nvmestorageunit0.streamsend[2].data[31] top.test.nvmestorageunit0.streamsend[2].data[30] top.test.nvmestorageunit0.streamsend[2].data[29] top.test.nvmestorageunit0.streamsend[2].data[28] top.test.nvmestorageunit0.streamsend[2].data[27] top.test.nvmestorageunit0.streamsend[2].data[26] top.test.nvmestorageunit0.streamsend[2].data[25] top.test.nvmestorageunit0.streamsend[2].data[24] top.test.nvmestorageunit0.streamsend[2].data[23] top.test.nvmestorageunit0.streamsend[2].data[22] top.test.nvmestorageunit0.streamsend[2].data[21] top.test.nvmestorageunit0.streamsend[2].data[20] top.test.nvmestorageunit0.streamsend[2].data[19] top.test.nvmestorageunit0.streamsend[2].data[18] top.test.nvmestorageunit0.streamsend[2].data[17] top.test.nvmestorageunit0.streamsend[2].data[16] top.test.nvmestorageunit0.streamsend[2].data[15] top.test.nvmestorageunit0.streamsend[2].data[14] top.test.nvmestorageunit0.streamsend[2].data[13] top.test.nvmestorageunit0.streamsend[2].data[12] top.test.nvmestorageunit0.streamsend[2].data[11] top.test.nvmestorageunit0.streamsend[2].data[10] top.test.nvmestorageunit0.streamsend[2].data[9] top.test.nvmestorageunit0.streamsend[2].data[8] top.test.nvmestorageunit0.streamsend[2].data[7] top.test.nvmestorageunit0.streamsend[2].data[6] top.test.nvmestorageunit0.streamsend[2].data[5] top.test.nvmestorageunit0.streamsend[2].data[4] top.test.nvmestorageunit0.streamsend[2].data[3] top.test.nvmestorageunit0.streamsend[2].data[2] top.test.nvmestorageunit0.streamsend[2].data[1] top.test.nvmestorageunit0.streamsend[2].data[0]
+#{top.test.nvmestorageunit0.gen03.nvmequeues0.requesthead1.requesterid[15:0]} top.test.nvmestorageunit0.gen03.nvmequeues0.requesthead1.requesterid[15] top.test.nvmestorageunit0.gen03.nvmequeues0.requesthead1.requesterid[14] top.test.nvmestorageunit0.gen03.nvmequeues0.requesthead1.requesterid[13] top.test.nvmestorageunit0.gen03.nvmequeues0.requesthead1.requesterid[12] top.test.nvmestorageunit0.gen03.nvmequeues0.requesthead1.requesterid[11] top.test.nvmestorageunit0.gen03.nvmequeues0.requesthead1.requesterid[10] top.test.nvmestorageunit0.gen03.nvmequeues0.requesthead1.requesterid[9] top.test.nvmestorageunit0.gen03.nvmequeues0.requesthead1.requesterid[8] top.test.nvmestorageunit0.gen03.nvmequeues0.requesthead1.requesterid[7] top.test.nvmestorageunit0.gen03.nvmequeues0.requesthead1.requesterid[6] top.test.nvmestorageunit0.gen03.nvmequeues0.requesthead1.requesterid[5] top.test.nvmestorageunit0.gen03.nvmequeues0.requesthead1.requesterid[4] top.test.nvmestorageunit0.gen03.nvmequeues0.requesthead1.requesterid[3] top.test.nvmestorageunit0.gen03.nvmequeues0.requesthead1.requesterid[2] top.test.nvmestorageunit0.gen03.nvmequeues0.requesthead1.requesterid[1] top.test.nvmestorageunit0.gen03.nvmequeues0.requesthead1.requesterid[0]
+@421
+top.test.nvmestorageunit0.gen03.nvmequeues0.ramaddress
+@22
+#{top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][127:0]} top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][127] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][126] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][125] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][124] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][123] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][122] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][121] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][120] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][119] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][118] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][117] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][116] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][115] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][114] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][113] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][112] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][111] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][110] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][109] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][108] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][107] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][106] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][105] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][104] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][103] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][102] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][101] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][100] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][99] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][98] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][97] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][96] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][95] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][94] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][93] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][92] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][91] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][90] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][89] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][88] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][87] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][86] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][85] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][84] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][83] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][82] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][81] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][80] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][79] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][78] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][77] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][76] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][75] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][74] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][73] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][72] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][71] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][70] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][69] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][68] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][67] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][66] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][65] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][64] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][63] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][62] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][61] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][60] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][59] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][58] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][57] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][56] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][55] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][54] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][53] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][52] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][51] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][50] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][49] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][48] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][47] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][46] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][45] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][44] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][43] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][42] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][41] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][40] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][39] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][38] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][37] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][36] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][35] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][34] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][33] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][32] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][31] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][30] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][29] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][28] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][27] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][26] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][25] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][24] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][23] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][22] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][21] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][20] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][19] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][18] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][17] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][16] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][15] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][14] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][13] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][12] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][11] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][10] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][9] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][8] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][7] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][6] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][5] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][4] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][3] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][2] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][1] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[0][0]
+#{top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][127:0]} top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][127] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][126] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][125] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][124] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][123] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][122] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][121] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][120] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][119] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][118] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][117] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][116] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][115] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][114] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][113] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][112] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][111] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][110] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][109] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][108] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][107] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][106] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][105] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][104] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][103] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][102] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][101] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][100] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][99] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][98] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][97] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][96] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][95] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][94] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][93] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][92] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][91] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][90] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][89] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][88] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][87] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][86] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][85] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][84] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][83] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][82] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][81] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][80] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][79] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][78] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][77] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][76] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][75] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][74] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][73] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][72] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][71] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][70] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][69] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][68] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][67] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][66] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][65] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][64] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][63] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][62] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][61] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][60] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][59] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][58] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][57] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][56] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][55] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][54] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][53] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][52] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][51] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][50] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][49] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][48] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][47] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][46] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][45] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][44] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][43] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][42] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][41] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][40] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][39] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][38] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][37] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][36] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][35] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][34] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][33] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][32] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][31] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][30] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][29] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][28] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][27] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][26] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][25] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][24] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][23] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][22] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][21] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][20] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][19] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][18] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][17] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][16] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][15] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][14] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][13] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][12] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][11] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][10] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][9] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][8] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][7] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][6] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][5] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][4] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][3] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][2] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][1] top.test.nvmestorageunit0.gen03.nvmequeues0.ram[1][0]
+@1000200
+-QueueRam
+@800200
+-NvmeWrite
+@420
+top.test.nvmestorageunit0.gen03.nvmewrite0.state
+@28
+top.test.nvmestorageunit0.gen03.nvmewrite0.enable
+@420
+top.test.nvmestorageunit0.gen03.nvmewrite0.numblocks[0]
+@28
+top.test.nvmestorageunit0.gen03.nvmewrite0.fifo_full
+@22
+#{top.test.nvmestorageunit0.gen03.nvmewrite0.datafifo0.fifo_count[11:0]} top.test.nvmestorageunit0.gen03.nvmewrite0.datafifo0.fifo_count[8] top.test.nvmestorageunit0.gen03.nvmewrite0.datafifo0.fifo_count[7] top.test.nvmestorageunit0.gen03.nvmewrite0.datafifo0.fifo_count[6] top.test.nvmestorageunit0.gen03.nvmewrite0.datafifo0.fifo_count[5] top.test.nvmestorageunit0.gen03.nvmewrite0.datafifo0.fifo_count[4] top.test.nvmestorageunit0.gen03.nvmewrite0.datafifo0.fifo_count[3] top.test.nvmestorageunit0.gen03.nvmewrite0.datafifo0.fifo_count[2] top.test.nvmestorageunit0.gen03.nvmewrite0.datafifo0.fifo_count[1] top.test.nvmestorageunit0.gen03.nvmewrite0.datafifo0.fifo_count[0]
+@28
+top.test.nvmestorageunit0.gen03.nvmewrite0.datafifo0.datain.ready
+top.test.nvmestorageunit0.gen03.nvmewrite0.datafifo0.datain.valid
+@22
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+@28
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+@28
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+#{top.test.nvmestorageunit0.gen03.nvmewrite0.requestout.keep[15:0]} top.test.nvmestorageunit0.gen03.nvmewrite0.requestout.keep[15] top.test.nvmestorageunit0.gen03.nvmewrite0.requestout.keep[14] top.test.nvmestorageunit0.gen03.nvmewrite0.requestout.keep[13] top.test.nvmestorageunit0.gen03.nvmewrite0.requestout.keep[12] top.test.nvmestorageunit0.gen03.nvmewrite0.requestout.keep[11] top.test.nvmestorageunit0.gen03.nvmewrite0.requestout.keep[10] top.test.nvmestorageunit0.gen03.nvmewrite0.requestout.keep[9] top.test.nvmestorageunit0.gen03.nvmewrite0.requestout.keep[8] top.test.nvmestorageunit0.gen03.nvmewrite0.requestout.keep[7] top.test.nvmestorageunit0.gen03.nvmewrite0.requestout.keep[6] top.test.nvmestorageunit0.gen03.nvmewrite0.requestout.keep[5] top.test.nvmestorageunit0.gen03.nvmewrite0.requestout.keep[4] top.test.nvmestorageunit0.gen03.nvmewrite0.requestout.keep[3] top.test.nvmestorageunit0.gen03.nvmewrite0.requestout.keep[2] top.test.nvmestorageunit0.gen03.nvmewrite0.requestout.keep[1] top.test.nvmestorageunit0.gen03.nvmewrite0.requestout.keep[0]
+#{top.test.nvmestorageunit0.gen03.nvmewrite0.requestout.data[127:0]} top.test.nvmestorageunit0.gen03.nvmewrite0.requestout.data[127] top.test.nvmestorageunit0.gen03.nvmewrite0.requestout.data[126] top.test.nvmestorageunit0.gen03.nvmewrite0.requestout.data[125] top.test.nvmestorageunit0.gen03.nvmewrite0.requestout.data[124] top.test.nvmestorageunit0.gen03.nvmewrite0.requestout.data[123] top.test.nvmestorageunit0.gen03.nvmewrite0.requestout.data[122] top.test.nvmestorageunit0.gen03.nvmewrite0.requestout.data[121] top.test.nvmestorageunit0.gen03.nvmewrite0.requestout.data[120] top.test.nvmestorageunit0.gen03.nvmewrite0.requestout.data[119] top.test.nvmestorageunit0.gen03.nvmewrite0.requestout.data[118] top.test.nvmestorageunit0.gen03.nvmewrite0.requestout.data[117] top.test.nvmestorageunit0.gen03.nvmewrite0.requestout.data[116] top.test.nvmestorageunit0.gen03.nvmewrite0.requestout.data[115] top.test.nvmestorageunit0.gen03.nvmewrite0.requestout.data[114] top.test.nvmestorageunit0.gen03.nvmewrite0.requestout.data[113] top.test.nvmestorageunit0.gen03.nvmewrite0.requestout.data[112] top.test.nvmestorageunit0.gen03.nvmewrite0.requestout.data[111] top.test.nvmestorageunit0.gen03.nvmewrite0.requestout.data[110] top.test.nvmestorageunit0.gen03.nvmewrite0.requestout.data[109] top.test.nvmestorageunit0.gen03.nvmewrite0.requestout.data[108] top.test.nvmestorageunit0.gen03.nvmewrite0.requestout.data[107] top.test.nvmestorageunit0.gen03.nvmewrite0.requestout.data[106] top.test.nvmestorageunit0.gen03.nvmewrite0.requestout.data[105] top.test.nvmestorageunit0.gen03.nvmewrite0.requestout.data[104] top.test.nvmestorageunit0.gen03.nvmewrite0.requestout.data[103] top.test.nvmestorageunit0.gen03.nvmewrite0.requestout.data[102] top.test.nvmestorageunit0.gen03.nvmewrite0.requestout.data[101] top.test.nvmestorageunit0.gen03.nvmewrite0.requestout.data[100] top.test.nvmestorageunit0.gen03.nvmewrite0.requestout.data[99] top.test.nvmestorageunit0.gen03.nvmewrite0.requestout.data[98] top.test.nvmestorageunit0.gen03.nvmewrite0.requestout.data[97] top.test.nvmestorageunit0.gen03.nvmewrite0.requestout.data[96] top.test.nvmestorageunit0.gen03.nvmewrite0.requestout.data[95] top.test.nvmestorageunit0.gen03.nvmewrite0.requestout.data[94] top.test.nvmestorageunit0.gen03.nvmewrite0.requestout.data[93] top.test.nvmestorageunit0.gen03.nvmewrite0.requestout.data[92] top.test.nvmestorageunit0.gen03.nvmewrite0.requestout.data[91] top.test.nvmestorageunit0.gen03.nvmewrite0.requestout.data[90] top.test.nvmestorageunit0.gen03.nvmewrite0.requestout.data[89] top.test.nvmestorageunit0.gen03.nvmewrite0.requestout.data[88] top.test.nvmestorageunit0.gen03.nvmewrite0.requestout.data[87] top.test.nvmestorageunit0.gen03.nvmewrite0.requestout.data[86] top.test.nvmestorageunit0.gen03.nvmewrite0.requestout.data[85] top.test.nvmestorageunit0.gen03.nvmewrite0.requestout.data[84] top.test.nvmestorageunit0.gen03.nvmewrite0.requestout.data[83] top.test.nvmestorageunit0.gen03.nvmewrite0.requestout.data[82] top.test.nvmestorageunit0.gen03.nvmewrite0.requestout.data[81] top.test.nvmestorageunit0.gen03.nvmewrite0.requestout.data[80] top.test.nvmestorageunit0.gen03.nvmewrite0.requestout.data[79] top.test.nvmestorageunit0.gen03.nvmewrite0.requestout.data[78] top.test.nvmestorageunit0.gen03.nvmewrite0.requestout.data[77] top.test.nvmestorageunit0.gen03.nvmewrite0.requestout.data[76] top.test.nvmestorageunit0.gen03.nvmewrite0.requestout.data[75] top.test.nvmestorageunit0.gen03.nvmewrite0.requestout.data[74] top.test.nvmestorageunit0.gen03.nvmewrite0.requestout.data[73] top.test.nvmestorageunit0.gen03.nvmewrite0.requestout.data[72] top.test.nvmestorageunit0.gen03.nvmewrite0.requestout.data[71] top.test.nvmestorageunit0.gen03.nvmewrite0.requestout.data[70] top.test.nvmestorageunit0.gen03.nvmewrite0.requestout.data[69] top.test.nvmestorageunit0.gen03.nvmewrite0.requestout.data[68] top.test.nvmestorageunit0.gen03.nvmewrite0.requestout.data[67] top.test.nvmestorageunit0.gen03.nvmewrite0.requestout.data[66] top.test.nvmestorageunit0.gen03.nvmewrite0.requestout.data[65] top.test.nvmestorageunit0.gen03.nvmewrite0.requestout.data[64] top.test.nvmestorageunit0.gen03.nvmewrite0.requestout.data[63] top.test.nvmestorageunit0.gen03.nvmewrite0.requestout.data[62] top.test.nvmestorageunit0.gen03.nvmewrite0.requestout.data[61] top.test.nvmestorageunit0.gen03.nvmewrite0.requestout.data[60] top.test.nvmestorageunit0.gen03.nvmewrite0.requestout.data[59] top.test.nvmestorageunit0.gen03.nvmewrite0.requestout.data[58] top.test.nvmestorageunit0.gen03.nvmewrite0.requestout.data[57] top.test.nvmestorageunit0.gen03.nvmewrite0.requestout.data[56] top.test.nvmestorageunit0.gen03.nvmewrite0.requestout.data[55] top.test.nvmestorageunit0.gen03.nvmewrite0.requestout.data[54] top.test.nvmestorageunit0.gen03.nvmewrite0.requestout.data[53] top.test.nvmestorageunit0.gen03.nvmewrite0.requestout.data[52] top.test.nvmestorageunit0.gen03.nvmewrite0.requestout.data[51] top.test.nvmestorageunit0.gen03.nvmewrite0.requestout.data[50] top.test.nvmestorageunit0.gen03.nvmewrite0.requestout.data[49] top.test.nvmestorageunit0.gen03.nvmewrite0.requestout.data[48] top.test.nvmestorageunit0.gen03.nvmewrite0.requestout.data[47] top.test.nvmestorageunit0.gen03.nvmewrite0.requestout.data[46] top.test.nvmestorageunit0.gen03.nvmewrite0.requestout.data[45] top.test.nvmestorageunit0.gen03.nvmewrite0.requestout.data[44] top.test.nvmestorageunit0.gen03.nvmewrite0.requestout.data[43] top.test.nvmestorageunit0.gen03.nvmewrite0.requestout.data[42] top.test.nvmestorageunit0.gen03.nvmewrite0.requestout.data[41] top.test.nvmestorageunit0.gen03.nvmewrite0.requestout.data[40] top.test.nvmestorageunit0.gen03.nvmewrite0.requestout.data[39] top.test.nvmestorageunit0.gen03.nvmewrite0.requestout.data[38] top.test.nvmestorageunit0.gen03.nvmewrite0.requestout.data[37] top.test.nvmestorageunit0.gen03.nvmewrite0.requestout.data[36] top.test.nvmestorageunit0.gen03.nvmewrite0.requestout.data[35] top.test.nvmestorageunit0.gen03.nvmewrite0.requestout.data[34] top.test.nvmestorageunit0.gen03.nvmewrite0.requestout.data[33] top.test.nvmestorageunit0.gen03.nvmewrite0.requestout.data[32] top.test.nvmestorageunit0.gen03.nvmewrite0.requestout.data[31] top.test.nvmestorageunit0.gen03.nvmewrite0.requestout.data[30] top.test.nvmestorageunit0.gen03.nvmewrite0.requestout.data[29] top.test.nvmestorageunit0.gen03.nvmewrite0.requestout.data[28] top.test.nvmestorageunit0.gen03.nvmewrite0.requestout.data[27] top.test.nvmestorageunit0.gen03.nvmewrite0.requestout.data[26] top.test.nvmestorageunit0.gen03.nvmewrite0.requestout.data[25] top.test.nvmestorageunit0.gen03.nvmewrite0.requestout.data[24] top.test.nvmestorageunit0.gen03.nvmewrite0.requestout.data[23] top.test.nvmestorageunit0.gen03.nvmewrite0.requestout.data[22] top.test.nvmestorageunit0.gen03.nvmewrite0.requestout.data[21] top.test.nvmestorageunit0.gen03.nvmewrite0.requestout.data[20] top.test.nvmestorageunit0.gen03.nvmewrite0.requestout.data[19] top.test.nvmestorageunit0.gen03.nvmewrite0.requestout.data[18] top.test.nvmestorageunit0.gen03.nvmewrite0.requestout.data[17] top.test.nvmestorageunit0.gen03.nvmewrite0.requestout.data[16] top.test.nvmestorageunit0.gen03.nvmewrite0.requestout.data[15] top.test.nvmestorageunit0.gen03.nvmewrite0.requestout.data[14] top.test.nvmestorageunit0.gen03.nvmewrite0.requestout.data[13] top.test.nvmestorageunit0.gen03.nvmewrite0.requestout.data[12] top.test.nvmestorageunit0.gen03.nvmewrite0.requestout.data[11] top.test.nvmestorageunit0.gen03.nvmewrite0.requestout.data[10] top.test.nvmestorageunit0.gen03.nvmewrite0.requestout.data[9] top.test.nvmestorageunit0.gen03.nvmewrite0.requestout.data[8] top.test.nvmestorageunit0.gen03.nvmewrite0.requestout.data[7] top.test.nvmestorageunit0.gen03.nvmewrite0.requestout.data[6] top.test.nvmestorageunit0.gen03.nvmewrite0.requestout.data[5] top.test.nvmestorageunit0.gen03.nvmewrite0.requestout.data[4] top.test.nvmestorageunit0.gen03.nvmewrite0.requestout.data[3] top.test.nvmestorageunit0.gen03.nvmewrite0.requestout.data[2] top.test.nvmestorageunit0.gen03.nvmewrite0.requestout.data[1] top.test.nvmestorageunit0.gen03.nvmewrite0.requestout.data[0]
+@28
+top.test.nvmestorageunit0.gen03.nvmewrite0.replyin.ready
+top.test.nvmestorageunit0.gen03.nvmewrite0.replyin.valid
+top.test.nvmestorageunit0.gen03.nvmewrite0.replyin.last
+@22
+#{top.test.nvmestorageunit0.gen03.nvmewrite0.replyin.keep[15:0]} top.test.nvmestorageunit0.gen03.nvmewrite0.replyin.keep[15] top.test.nvmestorageunit0.gen03.nvmewrite0.replyin.keep[14] top.test.nvmestorageunit0.gen03.nvmewrite0.replyin.keep[13] top.test.nvmestorageunit0.gen03.nvmewrite0.replyin.keep[12] top.test.nvmestorageunit0.gen03.nvmewrite0.replyin.keep[11] top.test.nvmestorageunit0.gen03.nvmewrite0.replyin.keep[10] top.test.nvmestorageunit0.gen03.nvmewrite0.replyin.keep[9] top.test.nvmestorageunit0.gen03.nvmewrite0.replyin.keep[8] top.test.nvmestorageunit0.gen03.nvmewrite0.replyin.keep[7] top.test.nvmestorageunit0.gen03.nvmewrite0.replyin.keep[6] top.test.nvmestorageunit0.gen03.nvmewrite0.replyin.keep[5] top.test.nvmestorageunit0.gen03.nvmewrite0.replyin.keep[4] top.test.nvmestorageunit0.gen03.nvmewrite0.replyin.keep[3] top.test.nvmestorageunit0.gen03.nvmewrite0.replyin.keep[2] top.test.nvmestorageunit0.gen03.nvmewrite0.replyin.keep[1] top.test.nvmestorageunit0.gen03.nvmewrite0.replyin.keep[0]
+#{top.test.nvmestorageunit0.gen03.nvmewrite0.replyin.data[127:0]} top.test.nvmestorageunit0.gen03.nvmewrite0.replyin.data[127] top.test.nvmestorageunit0.gen03.nvmewrite0.replyin.data[126] top.test.nvmestorageunit0.gen03.nvmewrite0.replyin.data[125] top.test.nvmestorageunit0.gen03.nvmewrite0.replyin.data[124] top.test.nvmestorageunit0.gen03.nvmewrite0.replyin.data[123] top.test.nvmestorageunit0.gen03.nvmewrite0.replyin.data[122] top.test.nvmestorageunit0.gen03.nvmewrite0.replyin.data[121] top.test.nvmestorageunit0.gen03.nvmewrite0.replyin.data[120] top.test.nvmestorageunit0.gen03.nvmewrite0.replyin.data[119] top.test.nvmestorageunit0.gen03.nvmewrite0.replyin.data[118] top.test.nvmestorageunit0.gen03.nvmewrite0.replyin.data[117] top.test.nvmestorageunit0.gen03.nvmewrite0.replyin.data[116] top.test.nvmestorageunit0.gen03.nvmewrite0.replyin.data[115] top.test.nvmestorageunit0.gen03.nvmewrite0.replyin.data[114] top.test.nvmestorageunit0.gen03.nvmewrite0.replyin.data[113] top.test.nvmestorageunit0.gen03.nvmewrite0.replyin.data[112] top.test.nvmestorageunit0.gen03.nvmewrite0.replyin.data[111] top.test.nvmestorageunit0.gen03.nvmewrite0.replyin.data[110] top.test.nvmestorageunit0.gen03.nvmewrite0.replyin.data[109] top.test.nvmestorageunit0.gen03.nvmewrite0.replyin.data[108] top.test.nvmestorageunit0.gen03.nvmewrite0.replyin.data[107] top.test.nvmestorageunit0.gen03.nvmewrite0.replyin.data[106] top.test.nvmestorageunit0.gen03.nvmewrite0.replyin.data[105] top.test.nvmestorageunit0.gen03.nvmewrite0.replyin.data[104] top.test.nvmestorageunit0.gen03.nvmewrite0.replyin.data[103] top.test.nvmestorageunit0.gen03.nvmewrite0.replyin.data[102] top.test.nvmestorageunit0.gen03.nvmewrite0.replyin.data[101] top.test.nvmestorageunit0.gen03.nvmewrite0.replyin.data[100] top.test.nvmestorageunit0.gen03.nvmewrite0.replyin.data[99] top.test.nvmestorageunit0.gen03.nvmewrite0.replyin.data[98] top.test.nvmestorageunit0.gen03.nvmewrite0.replyin.data[97] top.test.nvmestorageunit0.gen03.nvmewrite0.replyin.data[96] top.test.nvmestorageunit0.gen03.nvmewrite0.replyin.data[95] top.test.nvmestorageunit0.gen03.nvmewrite0.replyin.data[94] top.test.nvmestorageunit0.gen03.nvmewrite0.replyin.data[93] top.test.nvmestorageunit0.gen03.nvmewrite0.replyin.data[92] top.test.nvmestorageunit0.gen03.nvmewrite0.replyin.data[91] top.test.nvmestorageunit0.gen03.nvmewrite0.replyin.data[90] top.test.nvmestorageunit0.gen03.nvmewrite0.replyin.data[89] top.test.nvmestorageunit0.gen03.nvmewrite0.replyin.data[88] top.test.nvmestorageunit0.gen03.nvmewrite0.replyin.data[87] top.test.nvmestorageunit0.gen03.nvmewrite0.replyin.data[86] top.test.nvmestorageunit0.gen03.nvmewrite0.replyin.data[85] top.test.nvmestorageunit0.gen03.nvmewrite0.replyin.data[84] top.test.nvmestorageunit0.gen03.nvmewrite0.replyin.data[83] top.test.nvmestorageunit0.gen03.nvmewrite0.replyin.data[82] top.test.nvmestorageunit0.gen03.nvmewrite0.replyin.data[81] top.test.nvmestorageunit0.gen03.nvmewrite0.replyin.data[80] top.test.nvmestorageunit0.gen03.nvmewrite0.replyin.data[79] top.test.nvmestorageunit0.gen03.nvmewrite0.replyin.data[78] top.test.nvmestorageunit0.gen03.nvmewrite0.replyin.data[77] top.test.nvmestorageunit0.gen03.nvmewrite0.replyin.data[76] top.test.nvmestorageunit0.gen03.nvmewrite0.replyin.data[75] top.test.nvmestorageunit0.gen03.nvmewrite0.replyin.data[74] top.test.nvmestorageunit0.gen03.nvmewrite0.replyin.data[73] top.test.nvmestorageunit0.gen03.nvmewrite0.replyin.data[72] top.test.nvmestorageunit0.gen03.nvmewrite0.replyin.data[71] top.test.nvmestorageunit0.gen03.nvmewrite0.replyin.data[70] top.test.nvmestorageunit0.gen03.nvmewrite0.replyin.data[69] top.test.nvmestorageunit0.gen03.nvmewrite0.replyin.data[68] top.test.nvmestorageunit0.gen03.nvmewrite0.replyin.data[67] top.test.nvmestorageunit0.gen03.nvmewrite0.replyin.data[66] top.test.nvmestorageunit0.gen03.nvmewrite0.replyin.data[65] top.test.nvmestorageunit0.gen03.nvmewrite0.replyin.data[64] top.test.nvmestorageunit0.gen03.nvmewrite0.replyin.data[63] top.test.nvmestorageunit0.gen03.nvmewrite0.replyin.data[62] top.test.nvmestorageunit0.gen03.nvmewrite0.replyin.data[61] top.test.nvmestorageunit0.gen03.nvmewrite0.replyin.data[60] top.test.nvmestorageunit0.gen03.nvmewrite0.replyin.data[59] top.test.nvmestorageunit0.gen03.nvmewrite0.replyin.data[58] top.test.nvmestorageunit0.gen03.nvmewrite0.replyin.data[57] top.test.nvmestorageunit0.gen03.nvmewrite0.replyin.data[56] top.test.nvmestorageunit0.gen03.nvmewrite0.replyin.data[55] top.test.nvmestorageunit0.gen03.nvmewrite0.replyin.data[54] top.test.nvmestorageunit0.gen03.nvmewrite0.replyin.data[53] top.test.nvmestorageunit0.gen03.nvmewrite0.replyin.data[52] top.test.nvmestorageunit0.gen03.nvmewrite0.replyin.data[51] top.test.nvmestorageunit0.gen03.nvmewrite0.replyin.data[50] top.test.nvmestorageunit0.gen03.nvmewrite0.replyin.data[49] top.test.nvmestorageunit0.gen03.nvmewrite0.replyin.data[48] top.test.nvmestorageunit0.gen03.nvmewrite0.replyin.data[47] top.test.nvmestorageunit0.gen03.nvmewrite0.replyin.data[46] top.test.nvmestorageunit0.gen03.nvmewrite0.replyin.data[45] top.test.nvmestorageunit0.gen03.nvmewrite0.replyin.data[44] top.test.nvmestorageunit0.gen03.nvmewrite0.replyin.data[43] top.test.nvmestorageunit0.gen03.nvmewrite0.replyin.data[42] top.test.nvmestorageunit0.gen03.nvmewrite0.replyin.data[41] top.test.nvmestorageunit0.gen03.nvmewrite0.replyin.data[40] top.test.nvmestorageunit0.gen03.nvmewrite0.replyin.data[39] top.test.nvmestorageunit0.gen03.nvmewrite0.replyin.data[38] top.test.nvmestorageunit0.gen03.nvmewrite0.replyin.data[37] top.test.nvmestorageunit0.gen03.nvmewrite0.replyin.data[36] top.test.nvmestorageunit0.gen03.nvmewrite0.replyin.data[35] top.test.nvmestorageunit0.gen03.nvmewrite0.replyin.data[34] top.test.nvmestorageunit0.gen03.nvmewrite0.replyin.data[33] top.test.nvmestorageunit0.gen03.nvmewrite0.replyin.data[32] top.test.nvmestorageunit0.gen03.nvmewrite0.replyin.data[31] top.test.nvmestorageunit0.gen03.nvmewrite0.replyin.data[30] top.test.nvmestorageunit0.gen03.nvmewrite0.replyin.data[29] top.test.nvmestorageunit0.gen03.nvmewrite0.replyin.data[28] top.test.nvmestorageunit0.gen03.nvmewrite0.replyin.data[27] top.test.nvmestorageunit0.gen03.nvmewrite0.replyin.data[26] top.test.nvmestorageunit0.gen03.nvmewrite0.replyin.data[25] top.test.nvmestorageunit0.gen03.nvmewrite0.replyin.data[24] top.test.nvmestorageunit0.gen03.nvmewrite0.replyin.data[23] top.test.nvmestorageunit0.gen03.nvmewrite0.replyin.data[22] top.test.nvmestorageunit0.gen03.nvmewrite0.replyin.data[21] top.test.nvmestorageunit0.gen03.nvmewrite0.replyin.data[20] top.test.nvmestorageunit0.gen03.nvmewrite0.replyin.data[19] top.test.nvmestorageunit0.gen03.nvmewrite0.replyin.data[18] top.test.nvmestorageunit0.gen03.nvmewrite0.replyin.data[17] top.test.nvmestorageunit0.gen03.nvmewrite0.replyin.data[16] top.test.nvmestorageunit0.gen03.nvmewrite0.replyin.data[15] top.test.nvmestorageunit0.gen03.nvmewrite0.replyin.data[14] top.test.nvmestorageunit0.gen03.nvmewrite0.replyin.data[13] top.test.nvmestorageunit0.gen03.nvmewrite0.replyin.data[12] top.test.nvmestorageunit0.gen03.nvmewrite0.replyin.data[11] top.test.nvmestorageunit0.gen03.nvmewrite0.replyin.data[10] top.test.nvmestorageunit0.gen03.nvmewrite0.replyin.data[9] top.test.nvmestorageunit0.gen03.nvmewrite0.replyin.data[8] top.test.nvmestorageunit0.gen03.nvmewrite0.replyin.data[7] top.test.nvmestorageunit0.gen03.nvmewrite0.replyin.data[6] top.test.nvmestorageunit0.gen03.nvmewrite0.replyin.data[5] top.test.nvmestorageunit0.gen03.nvmewrite0.replyin.data[4] top.test.nvmestorageunit0.gen03.nvmewrite0.replyin.data[3] top.test.nvmestorageunit0.gen03.nvmewrite0.replyin.data[2] top.test.nvmestorageunit0.gen03.nvmewrite0.replyin.data[1] top.test.nvmestorageunit0.gen03.nvmewrite0.replyin.data[0]
+@420
+top.test.nvmestorageunit0.gen03.nvmewrite0.memstate
+@22
+#{top.test.nvmestorageunit0.gen03.nvmewrite0.memcount[10:0]} top.test.nvmestorageunit0.gen03.nvmewrite0.memcount[10] top.test.nvmestorageunit0.gen03.nvmewrite0.memcount[9] top.test.nvmestorageunit0.gen03.nvmewrite0.memcount[8] top.test.nvmestorageunit0.gen03.nvmewrite0.memcount[7] top.test.nvmestorageunit0.gen03.nvmewrite0.memcount[6] top.test.nvmestorageunit0.gen03.nvmewrite0.memcount[5] top.test.nvmestorageunit0.gen03.nvmewrite0.memcount[4] top.test.nvmestorageunit0.gen03.nvmewrite0.memcount[3] top.test.nvmestorageunit0.gen03.nvmewrite0.memcount[2] top.test.nvmestorageunit0.gen03.nvmewrite0.memcount[1] top.test.nvmestorageunit0.gen03.nvmewrite0.memcount[0]
+#{top.test.nvmestorageunit0.gen03.nvmewrite0.memchunkcount[10:0]} top.test.nvmestorageunit0.gen03.nvmewrite0.memchunkcount[10] top.test.nvmestorageunit0.gen03.nvmewrite0.memchunkcount[9] top.test.nvmestorageunit0.gen03.nvmewrite0.memchunkcount[8] top.test.nvmestorageunit0.gen03.nvmewrite0.memchunkcount[7] top.test.nvmestorageunit0.gen03.nvmewrite0.memchunkcount[6] top.test.nvmestorageunit0.gen03.nvmewrite0.memchunkcount[5] top.test.nvmestorageunit0.gen03.nvmewrite0.memchunkcount[4] top.test.nvmestorageunit0.gen03.nvmewrite0.memchunkcount[3] top.test.nvmestorageunit0.gen03.nvmewrite0.memchunkcount[2] top.test.nvmestorageunit0.gen03.nvmewrite0.memchunkcount[1] top.test.nvmestorageunit0.gen03.nvmewrite0.memchunkcount[0]
+@28
+top.test.nvmestorageunit0.gen03.nvmewrite0.memreqin.ready
+top.test.nvmestorageunit0.gen03.nvmewrite0.memreqin.valid
+top.test.nvmestorageunit0.gen03.nvmewrite0.memreqin.last
+@22
+#{top.test.nvmestorageunit0.gen03.nvmewrite0.memreqin.data[127:0]} top.test.nvmestorageunit0.gen03.nvmewrite0.memreqin.data[127] top.test.nvmestorageunit0.gen03.nvmewrite0.memreqin.data[126] top.test.nvmestorageunit0.gen03.nvmewrite0.memreqin.data[125] top.test.nvmestorageunit0.gen03.nvmewrite0.memreqin.data[124] top.test.nvmestorageunit0.gen03.nvmewrite0.memreqin.data[123] top.test.nvmestorageunit0.gen03.nvmewrite0.memreqin.data[122] top.test.nvmestorageunit0.gen03.nvmewrite0.memreqin.data[121] top.test.nvmestorageunit0.gen03.nvmewrite0.memreqin.data[120] top.test.nvmestorageunit0.gen03.nvmewrite0.memreqin.data[119] top.test.nvmestorageunit0.gen03.nvmewrite0.memreqin.data[118] top.test.nvmestorageunit0.gen03.nvmewrite0.memreqin.data[117] top.test.nvmestorageunit0.gen03.nvmewrite0.memreqin.data[116] top.test.nvmestorageunit0.gen03.nvmewrite0.memreqin.data[115] top.test.nvmestorageunit0.gen03.nvmewrite0.memreqin.data[114] top.test.nvmestorageunit0.gen03.nvmewrite0.memreqin.data[113] top.test.nvmestorageunit0.gen03.nvmewrite0.memreqin.data[112] top.test.nvmestorageunit0.gen03.nvmewrite0.memreqin.data[111] top.test.nvmestorageunit0.gen03.nvmewrite0.memreqin.data[110] top.test.nvmestorageunit0.gen03.nvmewrite0.memreqin.data[109] top.test.nvmestorageunit0.gen03.nvmewrite0.memreqin.data[108] top.test.nvmestorageunit0.gen03.nvmewrite0.memreqin.data[107] top.test.nvmestorageunit0.gen03.nvmewrite0.memreqin.data[106] top.test.nvmestorageunit0.gen03.nvmewrite0.memreqin.data[105] top.test.nvmestorageunit0.gen03.nvmewrite0.memreqin.data[104] top.test.nvmestorageunit0.gen03.nvmewrite0.memreqin.data[103] top.test.nvmestorageunit0.gen03.nvmewrite0.memreqin.data[102] top.test.nvmestorageunit0.gen03.nvmewrite0.memreqin.data[101] top.test.nvmestorageunit0.gen03.nvmewrite0.memreqin.data[100] top.test.nvmestorageunit0.gen03.nvmewrite0.memreqin.data[99] top.test.nvmestorageunit0.gen03.nvmewrite0.memreqin.data[98] top.test.nvmestorageunit0.gen03.nvmewrite0.memreqin.data[97] top.test.nvmestorageunit0.gen03.nvmewrite0.memreqin.data[96] top.test.nvmestorageunit0.gen03.nvmewrite0.memreqin.data[95] top.test.nvmestorageunit0.gen03.nvmewrite0.memreqin.data[94] top.test.nvmestorageunit0.gen03.nvmewrite0.memreqin.data[93] top.test.nvmestorageunit0.gen03.nvmewrite0.memreqin.data[92] top.test.nvmestorageunit0.gen03.nvmewrite0.memreqin.data[91] top.test.nvmestorageunit0.gen03.nvmewrite0.memreqin.data[90] top.test.nvmestorageunit0.gen03.nvmewrite0.memreqin.data[89] top.test.nvmestorageunit0.gen03.nvmewrite0.memreqin.data[88] top.test.nvmestorageunit0.gen03.nvmewrite0.memreqin.data[87] top.test.nvmestorageunit0.gen03.nvmewrite0.memreqin.data[86] top.test.nvmestorageunit0.gen03.nvmewrite0.memreqin.data[85] top.test.nvmestorageunit0.gen03.nvmewrite0.memreqin.data[84] top.test.nvmestorageunit0.gen03.nvmewrite0.memreqin.data[83] top.test.nvmestorageunit0.gen03.nvmewrite0.memreqin.data[82] top.test.nvmestorageunit0.gen03.nvmewrite0.memreqin.data[81] top.test.nvmestorageunit0.gen03.nvmewrite0.memreqin.data[80] top.test.nvmestorageunit0.gen03.nvmewrite0.memreqin.data[79] top.test.nvmestorageunit0.gen03.nvmewrite0.memreqin.data[78] top.test.nvmestorageunit0.gen03.nvmewrite0.memreqin.data[77] top.test.nvmestorageunit0.gen03.nvmewrite0.memreqin.data[76] top.test.nvmestorageunit0.gen03.nvmewrite0.memreqin.data[75] top.test.nvmestorageunit0.gen03.nvmewrite0.memreqin.data[74] top.test.nvmestorageunit0.gen03.nvmewrite0.memreqin.data[73] top.test.nvmestorageunit0.gen03.nvmewrite0.memreqin.data[72] top.test.nvmestorageunit0.gen03.nvmewrite0.memreqin.data[71] top.test.nvmestorageunit0.gen03.nvmewrite0.memreqin.data[70] top.test.nvmestorageunit0.gen03.nvmewrite0.memreqin.data[69] top.test.nvmestorageunit0.gen03.nvmewrite0.memreqin.data[68] top.test.nvmestorageunit0.gen03.nvmewrite0.memreqin.data[67] top.test.nvmestorageunit0.gen03.nvmewrite0.memreqin.data[66] top.test.nvmestorageunit0.gen03.nvmewrite0.memreqin.data[65] top.test.nvmestorageunit0.gen03.nvmewrite0.memreqin.data[64] top.test.nvmestorageunit0.gen03.nvmewrite0.memreqin.data[63] top.test.nvmestorageunit0.gen03.nvmewrite0.memreqin.data[62] top.test.nvmestorageunit0.gen03.nvmewrite0.memreqin.data[61] top.test.nvmestorageunit0.gen03.nvmewrite0.memreqin.data[60] top.test.nvmestorageunit0.gen03.nvmewrite0.memreqin.data[59] top.test.nvmestorageunit0.gen03.nvmewrite0.memreqin.data[58] top.test.nvmestorageunit0.gen03.nvmewrite0.memreqin.data[57] top.test.nvmestorageunit0.gen03.nvmewrite0.memreqin.data[56] top.test.nvmestorageunit0.gen03.nvmewrite0.memreqin.data[55] top.test.nvmestorageunit0.gen03.nvmewrite0.memreqin.data[54] top.test.nvmestorageunit0.gen03.nvmewrite0.memreqin.data[53] top.test.nvmestorageunit0.gen03.nvmewrite0.memreqin.data[52] top.test.nvmestorageunit0.gen03.nvmewrite0.memreqin.data[51] top.test.nvmestorageunit0.gen03.nvmewrite0.memreqin.data[50] top.test.nvmestorageunit0.gen03.nvmewrite0.memreqin.data[49] top.test.nvmestorageunit0.gen03.nvmewrite0.memreqin.data[48] top.test.nvmestorageunit0.gen03.nvmewrite0.memreqin.data[47] top.test.nvmestorageunit0.gen03.nvmewrite0.memreqin.data[46] top.test.nvmestorageunit0.gen03.nvmewrite0.memreqin.data[45] top.test.nvmestorageunit0.gen03.nvmewrite0.memreqin.data[44] top.test.nvmestorageunit0.gen03.nvmewrite0.memreqin.data[43] top.test.nvmestorageunit0.gen03.nvmewrite0.memreqin.data[42] top.test.nvmestorageunit0.gen03.nvmewrite0.memreqin.data[41] top.test.nvmestorageunit0.gen03.nvmewrite0.memreqin.data[40] top.test.nvmestorageunit0.gen03.nvmewrite0.memreqin.data[39] top.test.nvmestorageunit0.gen03.nvmewrite0.memreqin.data[38] top.test.nvmestorageunit0.gen03.nvmewrite0.memreqin.data[37] top.test.nvmestorageunit0.gen03.nvmewrite0.memreqin.data[36] top.test.nvmestorageunit0.gen03.nvmewrite0.memreqin.data[35] top.test.nvmestorageunit0.gen03.nvmewrite0.memreqin.data[34] top.test.nvmestorageunit0.gen03.nvmewrite0.memreqin.data[33] top.test.nvmestorageunit0.gen03.nvmewrite0.memreqin.data[32] top.test.nvmestorageunit0.gen03.nvmewrite0.memreqin.data[31] top.test.nvmestorageunit0.gen03.nvmewrite0.memreqin.data[30] top.test.nvmestorageunit0.gen03.nvmewrite0.memreqin.data[29] top.test.nvmestorageunit0.gen03.nvmewrite0.memreqin.data[28] top.test.nvmestorageunit0.gen03.nvmewrite0.memreqin.data[27] top.test.nvmestorageunit0.gen03.nvmewrite0.memreqin.data[26] top.test.nvmestorageunit0.gen03.nvmewrite0.memreqin.data[25] top.test.nvmestorageunit0.gen03.nvmewrite0.memreqin.data[24] top.test.nvmestorageunit0.gen03.nvmewrite0.memreqin.data[23] top.test.nvmestorageunit0.gen03.nvmewrite0.memreqin.data[22] top.test.nvmestorageunit0.gen03.nvmewrite0.memreqin.data[21] top.test.nvmestorageunit0.gen03.nvmewrite0.memreqin.data[20] top.test.nvmestorageunit0.gen03.nvmewrite0.memreqin.data[19] top.test.nvmestorageunit0.gen03.nvmewrite0.memreqin.data[18] top.test.nvmestorageunit0.gen03.nvmewrite0.memreqin.data[17] top.test.nvmestorageunit0.gen03.nvmewrite0.memreqin.data[16] top.test.nvmestorageunit0.gen03.nvmewrite0.memreqin.data[15] top.test.nvmestorageunit0.gen03.nvmewrite0.memreqin.data[14] top.test.nvmestorageunit0.gen03.nvmewrite0.memreqin.data[13] top.test.nvmestorageunit0.gen03.nvmewrite0.memreqin.data[12] top.test.nvmestorageunit0.gen03.nvmewrite0.memreqin.data[11] top.test.nvmestorageunit0.gen03.nvmewrite0.memreqin.data[10] top.test.nvmestorageunit0.gen03.nvmewrite0.memreqin.data[9] top.test.nvmestorageunit0.gen03.nvmewrite0.memreqin.data[8] top.test.nvmestorageunit0.gen03.nvmewrite0.memreqin.data[7] top.test.nvmestorageunit0.gen03.nvmewrite0.memreqin.data[6] top.test.nvmestorageunit0.gen03.nvmewrite0.memreqin.data[5] top.test.nvmestorageunit0.gen03.nvmewrite0.memreqin.data[4] top.test.nvmestorageunit0.gen03.nvmewrite0.memreqin.data[3] top.test.nvmestorageunit0.gen03.nvmewrite0.memreqin.data[2] top.test.nvmestorageunit0.gen03.nvmewrite0.memreqin.data[1] top.test.nvmestorageunit0.gen03.nvmewrite0.memreqin.data[0]
+@28
+top.test.nvmestorageunit0.gen03.nvmewrite0.memreplyout.ready
+top.test.nvmestorageunit0.gen03.nvmewrite0.memreplyout.valid
+top.test.nvmestorageunit0.gen03.nvmewrite0.memreplyout.last
+@22
+#{top.test.nvmestorageunit0.gen03.nvmewrite0.memreplyout.keep[15:0]} top.test.nvmestorageunit0.gen03.nvmewrite0.memreplyout.keep[15] top.test.nvmestorageunit0.gen03.nvmewrite0.memreplyout.keep[14] top.test.nvmestorageunit0.gen03.nvmewrite0.memreplyout.keep[13] top.test.nvmestorageunit0.gen03.nvmewrite0.memreplyout.keep[12] top.test.nvmestorageunit0.gen03.nvmewrite0.memreplyout.keep[11] top.test.nvmestorageunit0.gen03.nvmewrite0.memreplyout.keep[10] top.test.nvmestorageunit0.gen03.nvmewrite0.memreplyout.keep[9] top.test.nvmestorageunit0.gen03.nvmewrite0.memreplyout.keep[8] top.test.nvmestorageunit0.gen03.nvmewrite0.memreplyout.keep[7] top.test.nvmestorageunit0.gen03.nvmewrite0.memreplyout.keep[6] top.test.nvmestorageunit0.gen03.nvmewrite0.memreplyout.keep[5] top.test.nvmestorageunit0.gen03.nvmewrite0.memreplyout.keep[4] top.test.nvmestorageunit0.gen03.nvmewrite0.memreplyout.keep[3] top.test.nvmestorageunit0.gen03.nvmewrite0.memreplyout.keep[2] top.test.nvmestorageunit0.gen03.nvmewrite0.memreplyout.keep[1] top.test.nvmestorageunit0.gen03.nvmewrite0.memreplyout.keep[0]
+#{top.test.nvmestorageunit0.gen03.nvmewrite0.memreplyout.data[127:0]} top.test.nvmestorageunit0.gen03.nvmewrite0.memreplyout.data[127] top.test.nvmestorageunit0.gen03.nvmewrite0.memreplyout.data[126] top.test.nvmestorageunit0.gen03.nvmewrite0.memreplyout.data[125] top.test.nvmestorageunit0.gen03.nvmewrite0.memreplyout.data[124] top.test.nvmestorageunit0.gen03.nvmewrite0.memreplyout.data[123] top.test.nvmestorageunit0.gen03.nvmewrite0.memreplyout.data[122] top.test.nvmestorageunit0.gen03.nvmewrite0.memreplyout.data[121] top.test.nvmestorageunit0.gen03.nvmewrite0.memreplyout.data[120] top.test.nvmestorageunit0.gen03.nvmewrite0.memreplyout.data[119] top.test.nvmestorageunit0.gen03.nvmewrite0.memreplyout.data[118] top.test.nvmestorageunit0.gen03.nvmewrite0.memreplyout.data[117] top.test.nvmestorageunit0.gen03.nvmewrite0.memreplyout.data[116] top.test.nvmestorageunit0.gen03.nvmewrite0.memreplyout.data[115] top.test.nvmestorageunit0.gen03.nvmewrite0.memreplyout.data[114] top.test.nvmestorageunit0.gen03.nvmewrite0.memreplyout.data[113] top.test.nvmestorageunit0.gen03.nvmewrite0.memreplyout.data[112] top.test.nvmestorageunit0.gen03.nvmewrite0.memreplyout.data[111] top.test.nvmestorageunit0.gen03.nvmewrite0.memreplyout.data[110] top.test.nvmestorageunit0.gen03.nvmewrite0.memreplyout.data[109] top.test.nvmestorageunit0.gen03.nvmewrite0.memreplyout.data[108] top.test.nvmestorageunit0.gen03.nvmewrite0.memreplyout.data[107] top.test.nvmestorageunit0.gen03.nvmewrite0.memreplyout.data[106] top.test.nvmestorageunit0.gen03.nvmewrite0.memreplyout.data[105] top.test.nvmestorageunit0.gen03.nvmewrite0.memreplyout.data[104] top.test.nvmestorageunit0.gen03.nvmewrite0.memreplyout.data[103] top.test.nvmestorageunit0.gen03.nvmewrite0.memreplyout.data[102] top.test.nvmestorageunit0.gen03.nvmewrite0.memreplyout.data[101] top.test.nvmestorageunit0.gen03.nvmewrite0.memreplyout.data[100] top.test.nvmestorageunit0.gen03.nvmewrite0.memreplyout.data[99] top.test.nvmestorageunit0.gen03.nvmewrite0.memreplyout.data[98] top.test.nvmestorageunit0.gen03.nvmewrite0.memreplyout.data[97] top.test.nvmestorageunit0.gen03.nvmewrite0.memreplyout.data[96] top.test.nvmestorageunit0.gen03.nvmewrite0.memreplyout.data[95] top.test.nvmestorageunit0.gen03.nvmewrite0.memreplyout.data[94] top.test.nvmestorageunit0.gen03.nvmewrite0.memreplyout.data[93] top.test.nvmestorageunit0.gen03.nvmewrite0.memreplyout.data[92] top.test.nvmestorageunit0.gen03.nvmewrite0.memreplyout.data[91] top.test.nvmestorageunit0.gen03.nvmewrite0.memreplyout.data[90] top.test.nvmestorageunit0.gen03.nvmewrite0.memreplyout.data[89] top.test.nvmestorageunit0.gen03.nvmewrite0.memreplyout.data[88] top.test.nvmestorageunit0.gen03.nvmewrite0.memreplyout.data[87] top.test.nvmestorageunit0.gen03.nvmewrite0.memreplyout.data[86] top.test.nvmestorageunit0.gen03.nvmewrite0.memreplyout.data[85] top.test.nvmestorageunit0.gen03.nvmewrite0.memreplyout.data[84] top.test.nvmestorageunit0.gen03.nvmewrite0.memreplyout.data[83] top.test.nvmestorageunit0.gen03.nvmewrite0.memreplyout.data[82] top.test.nvmestorageunit0.gen03.nvmewrite0.memreplyout.data[81] top.test.nvmestorageunit0.gen03.nvmewrite0.memreplyout.data[80] top.test.nvmestorageunit0.gen03.nvmewrite0.memreplyout.data[79] top.test.nvmestorageunit0.gen03.nvmewrite0.memreplyout.data[78] top.test.nvmestorageunit0.gen03.nvmewrite0.memreplyout.data[77] top.test.nvmestorageunit0.gen03.nvmewrite0.memreplyout.data[76] top.test.nvmestorageunit0.gen03.nvmewrite0.memreplyout.data[75] top.test.nvmestorageunit0.gen03.nvmewrite0.memreplyout.data[74] top.test.nvmestorageunit0.gen03.nvmewrite0.memreplyout.data[73] top.test.nvmestorageunit0.gen03.nvmewrite0.memreplyout.data[72] top.test.nvmestorageunit0.gen03.nvmewrite0.memreplyout.data[71] top.test.nvmestorageunit0.gen03.nvmewrite0.memreplyout.data[70] top.test.nvmestorageunit0.gen03.nvmewrite0.memreplyout.data[69] top.test.nvmestorageunit0.gen03.nvmewrite0.memreplyout.data[68] top.test.nvmestorageunit0.gen03.nvmewrite0.memreplyout.data[67] top.test.nvmestorageunit0.gen03.nvmewrite0.memreplyout.data[66] top.test.nvmestorageunit0.gen03.nvmewrite0.memreplyout.data[65] top.test.nvmestorageunit0.gen03.nvmewrite0.memreplyout.data[64] top.test.nvmestorageunit0.gen03.nvmewrite0.memreplyout.data[63] top.test.nvmestorageunit0.gen03.nvmewrite0.memreplyout.data[62] top.test.nvmestorageunit0.gen03.nvmewrite0.memreplyout.data[61] top.test.nvmestorageunit0.gen03.nvmewrite0.memreplyout.data[60] top.test.nvmestorageunit0.gen03.nvmewrite0.memreplyout.data[59] top.test.nvmestorageunit0.gen03.nvmewrite0.memreplyout.data[58] top.test.nvmestorageunit0.gen03.nvmewrite0.memreplyout.data[57] top.test.nvmestorageunit0.gen03.nvmewrite0.memreplyout.data[56] top.test.nvmestorageunit0.gen03.nvmewrite0.memreplyout.data[55] top.test.nvmestorageunit0.gen03.nvmewrite0.memreplyout.data[54] top.test.nvmestorageunit0.gen03.nvmewrite0.memreplyout.data[53] top.test.nvmestorageunit0.gen03.nvmewrite0.memreplyout.data[52] top.test.nvmestorageunit0.gen03.nvmewrite0.memreplyout.data[51] top.test.nvmestorageunit0.gen03.nvmewrite0.memreplyout.data[50] top.test.nvmestorageunit0.gen03.nvmewrite0.memreplyout.data[49] top.test.nvmestorageunit0.gen03.nvmewrite0.memreplyout.data[48] top.test.nvmestorageunit0.gen03.nvmewrite0.memreplyout.data[47] top.test.nvmestorageunit0.gen03.nvmewrite0.memreplyout.data[46] top.test.nvmestorageunit0.gen03.nvmewrite0.memreplyout.data[45] top.test.nvmestorageunit0.gen03.nvmewrite0.memreplyout.data[44] top.test.nvmestorageunit0.gen03.nvmewrite0.memreplyout.data[43] top.test.nvmestorageunit0.gen03.nvmewrite0.memreplyout.data[42] top.test.nvmestorageunit0.gen03.nvmewrite0.memreplyout.data[41] top.test.nvmestorageunit0.gen03.nvmewrite0.memreplyout.data[40] top.test.nvmestorageunit0.gen03.nvmewrite0.memreplyout.data[39] top.test.nvmestorageunit0.gen03.nvmewrite0.memreplyout.data[38] top.test.nvmestorageunit0.gen03.nvmewrite0.memreplyout.data[37] top.test.nvmestorageunit0.gen03.nvmewrite0.memreplyout.data[36] top.test.nvmestorageunit0.gen03.nvmewrite0.memreplyout.data[35] top.test.nvmestorageunit0.gen03.nvmewrite0.memreplyout.data[34] top.test.nvmestorageunit0.gen03.nvmewrite0.memreplyout.data[33] top.test.nvmestorageunit0.gen03.nvmewrite0.memreplyout.data[32] top.test.nvmestorageunit0.gen03.nvmewrite0.memreplyout.data[31] top.test.nvmestorageunit0.gen03.nvmewrite0.memreplyout.data[30] top.test.nvmestorageunit0.gen03.nvmewrite0.memreplyout.data[29] top.test.nvmestorageunit0.gen03.nvmewrite0.memreplyout.data[28] top.test.nvmestorageunit0.gen03.nvmewrite0.memreplyout.data[27] top.test.nvmestorageunit0.gen03.nvmewrite0.memreplyout.data[26] top.test.nvmestorageunit0.gen03.nvmewrite0.memreplyout.data[25] top.test.nvmestorageunit0.gen03.nvmewrite0.memreplyout.data[24] top.test.nvmestorageunit0.gen03.nvmewrite0.memreplyout.data[23] top.test.nvmestorageunit0.gen03.nvmewrite0.memreplyout.data[22] top.test.nvmestorageunit0.gen03.nvmewrite0.memreplyout.data[21] top.test.nvmestorageunit0.gen03.nvmewrite0.memreplyout.data[20] top.test.nvmestorageunit0.gen03.nvmewrite0.memreplyout.data[19] top.test.nvmestorageunit0.gen03.nvmewrite0.memreplyout.data[18] top.test.nvmestorageunit0.gen03.nvmewrite0.memreplyout.data[17] top.test.nvmestorageunit0.gen03.nvmewrite0.memreplyout.data[16] top.test.nvmestorageunit0.gen03.nvmewrite0.memreplyout.data[15] top.test.nvmestorageunit0.gen03.nvmewrite0.memreplyout.data[14] top.test.nvmestorageunit0.gen03.nvmewrite0.memreplyout.data[13] top.test.nvmestorageunit0.gen03.nvmewrite0.memreplyout.data[12] top.test.nvmestorageunit0.gen03.nvmewrite0.memreplyout.data[11] top.test.nvmestorageunit0.gen03.nvmewrite0.memreplyout.data[10] top.test.nvmestorageunit0.gen03.nvmewrite0.memreplyout.data[9] top.test.nvmestorageunit0.gen03.nvmewrite0.memreplyout.data[8] top.test.nvmestorageunit0.gen03.nvmewrite0.memreplyout.data[7] top.test.nvmestorageunit0.gen03.nvmewrite0.memreplyout.data[6] top.test.nvmestorageunit0.gen03.nvmewrite0.memreplyout.data[5] top.test.nvmestorageunit0.gen03.nvmewrite0.memreplyout.data[4] top.test.nvmestorageunit0.gen03.nvmewrite0.memreplyout.data[3] top.test.nvmestorageunit0.gen03.nvmewrite0.memreplyout.data[2] top.test.nvmestorageunit0.gen03.nvmewrite0.memreplyout.data[1] top.test.nvmestorageunit0.gen03.nvmewrite0.memreplyout.data[0]
+@1000200
+-NvmeWrite
+@800200
+-NvmeSim
+@420
+top.test.nvmestorageunit0.sim.nvmesim0.state
+@22
+#{top.test.nvmestorageunit0.sim.nvmesim0.count[10:0]} top.test.nvmestorageunit0.sim.nvmesim0.count[10] top.test.nvmestorageunit0.sim.nvmesim0.count[9] top.test.nvmestorageunit0.sim.nvmesim0.count[8] top.test.nvmestorageunit0.sim.nvmesim0.count[7] top.test.nvmestorageunit0.sim.nvmesim0.count[6] top.test.nvmestorageunit0.sim.nvmesim0.count[5] top.test.nvmestorageunit0.sim.nvmesim0.count[4] top.test.nvmestorageunit0.sim.nvmesim0.count[3] top.test.nvmestorageunit0.sim.nvmesim0.count[2] top.test.nvmestorageunit0.sim.nvmesim0.count[1] top.test.nvmestorageunit0.sim.nvmesim0.count[0]
+@28
+top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.ready
+top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.valid
+top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.last
+@22
+#{top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[127:0]} top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[127] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[126] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[125] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[124] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[123] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[122] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[121] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[120] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[119] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[118] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[117] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[116] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[115] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[114] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[113] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[112] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[111] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[110] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[109] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[108] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[107] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[106] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[105] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[104] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[103] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[102] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[101] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[100] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[99] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[98] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[97] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[96] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[95] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[94] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[93] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[92] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[91] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[90] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[89] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[88] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[87] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[86] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[85] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[84] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[83] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[82] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[81] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[80] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[79] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[78] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[77] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[76] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[75] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[74] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[73] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[72] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[71] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[70] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[69] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[68] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[67] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[66] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[65] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[64] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[63] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[62] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[61] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[60] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[59] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[58] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[57] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[56] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[55] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[54] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[53] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[52] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[51] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[50] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[49] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[48] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[47] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[46] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[45] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[44] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[43] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[42] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[41] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[40] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[39] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[38] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[37] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[36] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[35] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[34] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[33] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[32] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[31] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[30] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[29] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[28] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[27] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[26] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[25] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[24] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[23] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[22] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[21] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[20] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[19] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[18] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[17] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[16] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[15] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[14] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[13] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[12] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[11] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[10] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[9] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[8] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[7] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[6] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[5] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[4] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[3] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[2] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[1] top.test.nvmestorageunit0.sim.nvmesim0.nvmereq.data[0]
+#{top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[0][127:0]} top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[0][31] top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[0][30] top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[0][29] top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[0][28] top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[0][27] top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[0][26] top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[0][25] top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[0][24] top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[0][23] top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[0][22] top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[0][21] top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[0][20] top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[0][19] top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[0][18] top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[0][17] top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[0][16] top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[0][15] top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[0][14] top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[0][13] top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[0][12] top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[0][11] top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[0][10] top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[0][9] top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[0][8] top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[0][7] top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[0][6] top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[0][5] top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[0][4] top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[0][3] top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[0][2] top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[0][1] top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[0][0]
+#{top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[1][127:0]} top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[1][31] top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[1][30] top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[1][29] top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[1][28] top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[1][27] top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[1][26] top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[1][25] top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[1][24] top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[1][23] top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[1][22] top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[1][21] top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[1][20] top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[1][19] top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[1][18] top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[1][17] top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[1][16] top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[1][15] top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[1][14] top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[1][13] top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[1][12] top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[1][11] top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[1][10] top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[1][9] top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[1][8] top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[1][7] top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[1][6] top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[1][5] top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[1][4] top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[1][3] top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[1][2] top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[1][1] top.test.nvmestorageunit0.sim.nvmesim0.queuerequest[1][0]
+@28
+top.test.nvmestorageunit0.sim.nvmesim0.nvmereply.ready
+top.test.nvmestorageunit0.sim.nvmesim0.nvmereply.valid
+top.test.nvmestorageunit0.sim.nvmesim0.nvmereply.last
+@22
+#{top.test.nvmestorageunit0.sim.nvmesim0.nvmereply.data[127:0]} top.test.nvmestorageunit0.sim.nvmesim0.nvmereply.data[127] top.test.nvmestorageunit0.sim.nvmesim0.nvmereply.data[126] top.test.nvmestorageunit0.sim.nvmesim0.nvmereply.data[125] top.test.nvmestorageunit0.sim.nvmesim0.nvmereply.data[124] top.test.nvmestorageunit0.sim.nvmesim0.nvmereply.data[123] top.test.nvmestorageunit0.sim.nvmesim0.nvmereply.data[122] top.test.nvmestorageunit0.sim.nvmesim0.nvmereply.data[121] top.test.nvmestorageunit0.sim.nvmesim0.nvmereply.data[120] top.test.nvmestorageunit0.sim.nvmesim0.nvmereply.data[119] top.test.nvmestorageunit0.sim.nvmesim0.nvmereply.data[118] top.test.nvmestorageunit0.sim.nvmesim0.nvmereply.data[117] top.test.nvmestorageunit0.sim.nvmesim0.nvmereply.data[116] top.test.nvmestorageunit0.sim.nvmesim0.nvmereply.data[115] top.test.nvmestorageunit0.sim.nvmesim0.nvmereply.data[114] top.test.nvmestorageunit0.sim.nvmesim0.nvmereply.data[113] top.test.nvmestorageunit0.sim.nvmesim0.nvmereply.data[112] top.test.nvmestorageunit0.sim.nvmesim0.nvmereply.data[111] top.test.nvmestorageunit0.sim.nvmesim0.nvmereply.data[110] top.test.nvmestorageunit0.sim.nvmesim0.nvmereply.data[109] top.test.nvmestorageunit0.sim.nvmesim0.nvmereply.data[108] top.test.nvmestorageunit0.sim.nvmesim0.nvmereply.data[107] top.test.nvmestorageunit0.sim.nvmesim0.nvmereply.data[106] top.test.nvmestorageunit0.sim.nvmesim0.nvmereply.data[105] top.test.nvmestorageunit0.sim.nvmesim0.nvmereply.data[104] top.test.nvmestorageunit0.sim.nvmesim0.nvmereply.data[103] top.test.nvmestorageunit0.sim.nvmesim0.nvmereply.data[102] top.test.nvmestorageunit0.sim.nvmesim0.nvmereply.data[101] top.test.nvmestorageunit0.sim.nvmesim0.nvmereply.data[100] top.test.nvmestorageunit0.sim.nvmesim0.nvmereply.data[99] top.test.nvmestorageunit0.sim.nvmesim0.nvmereply.data[98] top.test.nvmestorageunit0.sim.nvmesim0.nvmereply.data[97] top.test.nvmestorageunit0.sim.nvmesim0.nvmereply.data[96] top.test.nvmestorageunit0.sim.nvmesim0.nvmereply.data[95] top.test.nvmestorageunit0.sim.nvmesim0.nvmereply.data[94] top.test.nvmestorageunit0.sim.nvmesim0.nvmereply.data[93] top.test.nvmestorageunit0.sim.nvmesim0.nvmereply.data[92] top.test.nvmestorageunit0.sim.nvmesim0.nvmereply.data[91] top.test.nvmestorageunit0.sim.nvmesim0.nvmereply.data[90] top.test.nvmestorageunit0.sim.nvmesim0.nvmereply.data[89] top.test.nvmestorageunit0.sim.nvmesim0.nvmereply.data[88] top.test.nvmestorageunit0.sim.nvmesim0.nvmereply.data[87] top.test.nvmestorageunit0.sim.nvmesim0.nvmereply.data[86] top.test.nvmestorageunit0.sim.nvmesim0.nvmereply.data[85] top.test.nvmestorageunit0.sim.nvmesim0.nvmereply.data[84] top.test.nvmestorageunit0.sim.nvmesim0.nvmereply.data[83] top.test.nvmestorageunit0.sim.nvmesim0.nvmereply.data[82] top.test.nvmestorageunit0.sim.nvmesim0.nvmereply.data[81] top.test.nvmestorageunit0.sim.nvmesim0.nvmereply.data[80] top.test.nvmestorageunit0.sim.nvmesim0.nvmereply.data[79] top.test.nvmestorageunit0.sim.nvmesim0.nvmereply.data[78] top.test.nvmestorageunit0.sim.nvmesim0.nvmereply.data[77] top.test.nvmestorageunit0.sim.nvmesim0.nvmereply.data[76] top.test.nvmestorageunit0.sim.nvmesim0.nvmereply.data[75] top.test.nvmestorageunit0.sim.nvmesim0.nvmereply.data[74] top.test.nvmestorageunit0.sim.nvmesim0.nvmereply.data[73] top.test.nvmestorageunit0.sim.nvmesim0.nvmereply.data[72] top.test.nvmestorageunit0.sim.nvmesim0.nvmereply.data[71] top.test.nvmestorageunit0.sim.nvmesim0.nvmereply.data[70] top.test.nvmestorageunit0.sim.nvmesim0.nvmereply.data[69] top.test.nvmestorageunit0.sim.nvmesim0.nvmereply.data[68] top.test.nvmestorageunit0.sim.nvmesim0.nvmereply.data[67] top.test.nvmestorageunit0.sim.nvmesim0.nvmereply.data[66] top.test.nvmestorageunit0.sim.nvmesim0.nvmereply.data[65] top.test.nvmestorageunit0.sim.nvmesim0.nvmereply.data[64] top.test.nvmestorageunit0.sim.nvmesim0.nvmereply.data[63] top.test.nvmestorageunit0.sim.nvmesim0.nvmereply.data[62] top.test.nvmestorageunit0.sim.nvmesim0.nvmereply.data[61] top.test.nvmestorageunit0.sim.nvmesim0.nvmereply.data[60] top.test.nvmestorageunit0.sim.nvmesim0.nvmereply.data[59] top.test.nvmestorageunit0.sim.nvmesim0.nvmereply.data[58] top.test.nvmestorageunit0.sim.nvmesim0.nvmereply.data[57] top.test.nvmestorageunit0.sim.nvmesim0.nvmereply.data[56] top.test.nvmestorageunit0.sim.nvmesim0.nvmereply.data[55] top.test.nvmestorageunit0.sim.nvmesim0.nvmereply.data[54] top.test.nvmestorageunit0.sim.nvmesim0.nvmereply.data[53] top.test.nvmestorageunit0.sim.nvmesim0.nvmereply.data[52] top.test.nvmestorageunit0.sim.nvmesim0.nvmereply.data[51] top.test.nvmestorageunit0.sim.nvmesim0.nvmereply.data[50] top.test.nvmestorageunit0.sim.nvmesim0.nvmereply.data[49] top.test.nvmestorageunit0.sim.nvmesim0.nvmereply.data[48] top.test.nvmestorageunit0.sim.nvmesim0.nvmereply.data[47] top.test.nvmestorageunit0.sim.nvmesim0.nvmereply.data[46] top.test.nvmestorageunit0.sim.nvmesim0.nvmereply.data[45] top.test.nvmestorageunit0.sim.nvmesim0.nvmereply.data[44] top.test.nvmestorageunit0.sim.nvmesim0.nvmereply.data[43] top.test.nvmestorageunit0.sim.nvmesim0.nvmereply.data[42] top.test.nvmestorageunit0.sim.nvmesim0.nvmereply.data[41] top.test.nvmestorageunit0.sim.nvmesim0.nvmereply.data[40] top.test.nvmestorageunit0.sim.nvmesim0.nvmereply.data[39] top.test.nvmestorageunit0.sim.nvmesim0.nvmereply.data[38] top.test.nvmestorageunit0.sim.nvmesim0.nvmereply.data[37] top.test.nvmestorageunit0.sim.nvmesim0.nvmereply.data[36] top.test.nvmestorageunit0.sim.nvmesim0.nvmereply.data[35] top.test.nvmestorageunit0.sim.nvmesim0.nvmereply.data[34] top.test.nvmestorageunit0.sim.nvmesim0.nvmereply.data[33] top.test.nvmestorageunit0.sim.nvmesim0.nvmereply.data[32] top.test.nvmestorageunit0.sim.nvmesim0.nvmereply.data[31] top.test.nvmestorageunit0.sim.nvmesim0.nvmereply.data[30] top.test.nvmestorageunit0.sim.nvmesim0.nvmereply.data[29] top.test.nvmestorageunit0.sim.nvmesim0.nvmereply.data[28] top.test.nvmestorageunit0.sim.nvmesim0.nvmereply.data[27] top.test.nvmestorageunit0.sim.nvmesim0.nvmereply.data[26] top.test.nvmestorageunit0.sim.nvmesim0.nvmereply.data[25] top.test.nvmestorageunit0.sim.nvmesim0.nvmereply.data[24] top.test.nvmestorageunit0.sim.nvmesim0.nvmereply.data[23] top.test.nvmestorageunit0.sim.nvmesim0.nvmereply.data[22] top.test.nvmestorageunit0.sim.nvmesim0.nvmereply.data[21] top.test.nvmestorageunit0.sim.nvmesim0.nvmereply.data[20] top.test.nvmestorageunit0.sim.nvmesim0.nvmereply.data[19] top.test.nvmestorageunit0.sim.nvmesim0.nvmereply.data[18] top.test.nvmestorageunit0.sim.nvmesim0.nvmereply.data[17] top.test.nvmestorageunit0.sim.nvmesim0.nvmereply.data[16] top.test.nvmestorageunit0.sim.nvmesim0.nvmereply.data[15] top.test.nvmestorageunit0.sim.nvmesim0.nvmereply.data[14] top.test.nvmestorageunit0.sim.nvmesim0.nvmereply.data[13] top.test.nvmestorageunit0.sim.nvmesim0.nvmereply.data[12] top.test.nvmestorageunit0.sim.nvmesim0.nvmereply.data[11] top.test.nvmestorageunit0.sim.nvmesim0.nvmereply.data[10] top.test.nvmestorageunit0.sim.nvmesim0.nvmereply.data[9] top.test.nvmestorageunit0.sim.nvmesim0.nvmereply.data[8] top.test.nvmestorageunit0.sim.nvmesim0.nvmereply.data[7] top.test.nvmestorageunit0.sim.nvmesim0.nvmereply.data[6] top.test.nvmestorageunit0.sim.nvmesim0.nvmereply.data[5] top.test.nvmestorageunit0.sim.nvmesim0.nvmereply.data[4] top.test.nvmestorageunit0.sim.nvmesim0.nvmereply.data[3] top.test.nvmestorageunit0.sim.nvmesim0.nvmereply.data[2] top.test.nvmestorageunit0.sim.nvmesim0.nvmereply.data[1] top.test.nvmestorageunit0.sim.nvmesim0.nvmereply.data[0]
+@1000200
+-NvmeSim
+[pattern_trace] 1
+[pattern_trace] 0
diff --git a/source/DuneNvme/sim/testbench/test017-write.vhd b/source/DuneNvme/sim/testbench/test017-write.vhd
new file mode 100644 (file)
index 0000000..b2aaf09
--- /dev/null
@@ -0,0 +1,336 @@
+--------------------------------------------------------------------------------
+--     Test009-packets.vhd     Simple nvme interface tests
+--     T.Barnaby,      Beam Ltd.       2020-04-14
+--------------------------------------------------------------------------------
+--
+--
+--
+library ieee ;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.NvmeStoragePkg.all;
+use work.NvmeStorageIntPkg.all;
+use work.TestPkg.all;
+
+entity Test is
+end;
+
+architecture sim of Test is
+
+component NvmeStorageUnit is
+generic(
+       Simulate        : boolean       := True;                --! Generate simulation core
+       ClockPeriod     : time          := 10 ms                --! Clock period for timers (125 MHz)
+);
+port (
+       clk             : in std_logic;                         --! The interface clock line
+       reset           : in std_logic;                         --! The active high reset line
+
+       -- Control and status interface
+       axilIn          : in AxilToSlaveType;                   --! Axil bus input signals
+       axilOut         : out AxilToMasterType;                 --! Axil bus output signals
+
+       -- From host to NVMe request/reply streams
+       hostSend        : inout AxisStreamType := AxisInput;    --! Host request stream
+       hostRecv        : inout AxisStreamType := AxisOutput;   --! Host reply stream
+
+       -- AXIS data stream input
+       dataIn          : inout AxisStreamType  := AxisInput;   --! Raw data to save stream
+
+       -- NVMe interface
+       nvme_clk_p      : in std_logic;                         --! Nvme external clock +ve
+       nvme_clk_n      : in std_logic;                         --! Nvme external clock -ve
+       nvme_reset_n    : out std_logic;                        --! Nvme reset output to reset NVMe devices
+       nvme_exp_txp    : out std_logic_vector(3 downto 0);     --! Nvme PCIe TX plus lanes
+       nvme_exp_txn    : out std_logic_vector(3 downto 0);     --! Nvme PCIe TX minus lanes
+       nvme_exp_rxp    : in std_logic_vector(3 downto 0);      --! Nvme PCIe RX plus lanes
+       nvme_exp_rxn    : in std_logic_vector(3 downto 0);      --! Nvme PCIe RX minus lanes
+
+       -- Debug
+       leds            : out std_logic_vector(3 downto 0)
+);
+end component;
+
+component TestData is
+generic(
+       BlockSize       : integer := 4096                       --! The block size in Bytes.
+);
+port (
+       clk             : in std_logic;                         --! The interface clock line
+       reset           : in std_logic;                         --! The active high reset line
+
+       -- Control and status interface
+       enable          : in std_logic;                         --! Enable production of data
+
+       -- AXIS data output
+       dataStream      : inout AxisStreamType := AxisOutput    --! Output data stream
+);
+end component;
+
+component NvmeStreamMux is
+port (
+       clk             : in std_logic;                         --! The interface clock line
+       reset           : in std_logic;                         --! The active high reset line
+       
+       stream1In       : inout AxisStreamType := AxisInput;    --! Single multiplexed Input stream
+       stream1Out      : inout AxisStreamType := AxisOutput;   --! Single multiplexed Ouput stream
+
+       stream2In       : inout AxisStreamType := AxisInput;    --! Host Replies input stream
+       stream2Out      : inout AxisStreamType := AxisOutput;   --! Host Requests output stream
+
+       stream3In       : inout AxisStreamType := AxisInput;    --! Nvme Requests input stream
+       stream3Out      : inout AxisStreamType := AxisOutput    --! Nvme replies output stream
+);
+end component;
+
+constant TCQ           : time := 1 ns;
+constant CHUNK_SIZE    : integer := 32;                        -- The data write chunk size in DWords due to PCIe packet size limitations
+
+signal clk             : std_logic := '0';
+signal reset           : std_logic := '0';
+
+signal axil            : AxilBusType;
+signal hostSend                : AxisStreamType := AxisOutput;
+signal hostRecv                : AxisStreamType := AxisInput;
+
+signal leds            : std_logic_vector(3 downto 0);
+
+signal hostReply       : AxisStreamType := AxisInput;
+signal hostReq         : AxisStreamType := AxisOutput;
+signal nvmeReq         : AxisStreamType := AxisInput;
+signal nvmeReply       : AxisStreamType := AxisOutput;
+signal dataIn          : AxisStreamType;
+
+type NvmeStateType is (NVME_STATE_IDLE, NVME_STATE_WRITEDATA, NVME_STATE_READHEAD, NVME_STATE_READDATA);
+signal nvmeState       : NvmeStateType := NVME_STATE_IDLE;
+signal nvmeRequestHead : PcieRequestHeadType;
+signal nvmeRequestHead1        : PcieRequestHeadType;
+signal nvmeReplyHead   : PcieReplyHeadType;
+signal nvmeCount       : unsigned(10 downto 0);                        -- DWord data send count
+signal nvmeChunkCount  : unsigned(10 downto 0);                        -- DWord data send within a chunk count
+signal nvmeData                : std_logic_vector(127 downto 0);
+signal nvmeData1       : std_logic_vector(127 downto 0);
+
+signal sendData                : std_logic := '0';
+
+begin
+       hostReply.ready <= '1';
+       
+       NvmeStorageUnit0 : NvmeStorageUnit
+       port map (
+               clk             => clk,
+               reset           => reset,
+
+               axilIn          => axil.toSlave,
+               axilOut         => axil.toMaster,
+
+               hostSend        => hostSend,
+               hostRecv        => hostRecv,
+               
+               dataIn          => dataIn,
+
+               -- NVMe interface
+               nvme_clk_p      => '0',
+               nvme_clk_n      => '0',
+               --nvme_exp_txp  : out std_logic_vector(0 downto 0);
+               --nvme_exp_txn  : out std_logic_vector(0 downto 0);
+               nvme_exp_rxp    => "0000",
+               nvme_exp_rxn    => "0000",
+
+               leds            => leds
+       );
+
+       clock : process
+       begin
+               wait for 5 ns; clk  <= not clk;
+       end process clock;
+
+       init : process
+       begin
+               reset   <= '1';
+               wait for 20 ns;
+               reset   <= '0';
+               wait;
+       end process;
+       
+       run : process
+       begin
+               wait until reset = '0';
+
+               -- Test NvmeWrite
+               wait for 100 ns;
+               sendData <= '1';
+
+               -- Write to NvmeStorage control register to start NvmeWrite processing
+               wait for 100 ns;
+               busWrite(clk, axil.toSlave, axil.toMaster, 4, 16#00000004#);
+
+               -- Read status registers
+               wait for 100 ns;
+               busRead(clk, axil.toSlave, axil.toMaster, 32);
+               busRead(clk, axil.toSlave, axil.toMaster, 36);
+
+               wait;           
+               
+               --wait for 1000 ns;
+               
+               -- Perform local reset
+               --busWrite(clk, axil.toSlave, axil.toMaster, 4, 16#00000001#);
+               --wait for 1000 ns;
+
+               -- Set PCIe configuration command register to 0x06
+               --pcieRequestWrite(clk, hostReq, 1, 10, 4, 16#44#, 1, 16#00100006#);
+               
+               -- Read PCIe configuration command register
+               --pcieRequestRead(clk, hostReq, 1, 8, 4, 16#55#, 1);
+               
+               -- Test Mux with Write to Nvmeregister 0
+               --pcieRequestWrite(clk, hostReq, 1, 1, 16#0000#, 16#22#, 1, 16#40#);
+
+               -- Write to AdminQueue doorbell register
+               --pcieRequestWrite(clk, hostReq, 1, 1, 16#1000#, 16#22#, 1, 16#40#);
+
+               -- Write to AdminQueue
+               pcieRequestWrite(clk, hostReq, 1, 1, 16#02000000#, 16#22#, 16, 16#00000010#);
+
+               -- Write to DataQueue
+               pcieRequestWrite(clk, hostReq, 1, 1, 16#02010000#, 16#22#, 16, 16#00000010#);
+
+               -- Perform NVMe data write
+               -- Write to DataWriteQueue doorbell register
+               --pcieRequestWrite(clk, hostReq, 1, 1, 16#1008#, 16#23#, 1, 16#40#);
+               wait;
+       end process;
+       
+       -- The test data interface
+       testData0 : TestData
+       port map (
+               clk             => clk,
+               reset           => reset,
+
+               enable          => sendData,
+
+               dataStream      => dataIn
+       );      
+
+
+       -- Host to Nvme stream Mux/DeMux
+       nvmeStreamMux0 : NvmeStreamMux
+       port map (
+               clk             => clk,
+               reset           => reset,
+
+               stream1In       => hostRecv,
+               stream1Out      => hostSend,
+               
+               stream2In       => nvmeReply,
+               stream2Out      => nvmeReq,
+
+               stream3In       => hostReq,
+               stream3Out      => hostReply
+       );
+
+
+       nvmeRequestHead <= to_PcieRequestHeadType(nvmeReq.data);
+       nvmeReply.data <= nvmeData(31 downto 0) & to_stl(nvmeReplyHead) when(nvmeState = NVME_STATE_READHEAD)
+               else nvmeData(31 downto 0) & nvmeData1(127 downto 32);
+       
+       requests : process(clk)
+       begin
+               if(rising_edge(clk)) then
+                       if(reset = '1') then
+                               nvmeReq.ready   <= '0';
+                               nvmeReply.valid <= '0';
+                               nvmeReply.last  <= '0';
+                               nvmeReply.keep  <= (others => '1');
+                               nvmeData        <= (others => '0');
+                               nvmeState       <= NVME_STATE_IDLE;
+                       else
+                               case (nvmeState) is
+                               when NVME_STATE_IDLE =>
+                                       if(nvmeReq.ready = '1' and nvmeReq.valid = '1') then
+                                               nvmeRequestHead1        <= nvmeRequestHead;
+                                               nvmeCount               <= nvmeRequestHead.count;
+
+                                               if(nvmeRequestHead.request = 1) then
+                                                       nvmeState <= NVME_STATE_WRITEDATA;
+                                               elsif(nvmeRequestHead.request = 0) then
+                                                       nvmeState <= NVME_STATE_READHEAD;
+                                               end if;
+                                       else
+                                               nvmeReq.ready <= '1';
+                                       end if;
+
+                               when NVME_STATE_WRITEDATA =>
+                                       if((nvmeReq.ready = '1') and (nvmeReq.valid = '1') and (nvmeReq.last = '1')) then
+                                               nvmeState <= NVME_STATE_IDLE;
+                                       end if;
+                               
+                               
+                               when NVME_STATE_READHEAD =>
+                                       nvmeReq.ready                   <= '0';
+                                       nvmeReplyHead.byteCount         <= nvmeCount & "00";
+                                       nvmeReplyHead.address           <= nvmeRequestHead1.address(nvmeReplyHead.address'length - 1 downto 0);
+                                       nvmeReplyHead.error             <= (others => '0');
+                                       nvmeReplyHead.status            <= (others => '0');
+                                       nvmeReplyHead.tag               <= nvmeRequestHead1.tag;
+                                       nvmeReplyHead.requesterId       <= nvmeRequestHead1.requesterId;
+
+                                       if(nvmeCount > CHUNK_SIZE) then
+                                               nvmeReplyHead.count     <= to_unsigned(PcieMaxPayloadSize, nvmeReplyHead.count'length);
+                                               nvmeChunkCount          <= to_unsigned(PcieMaxPayloadSize, nvmeReplyHead.count'length);
+                                       else
+                                               nvmeReplyHead.count     <= nvmeCount;
+                                               nvmeChunkCount          <= nvmeCount;
+                                       end if;
+                                       
+                                       nvmeData1               <= nvmeData;
+                                       nvmeReply.keep          <= (others => '1');
+                                       nvmeReply.valid         <= '1';
+
+                                       if(nvmeReply.ready = '1' and nvmeReply.valid = '1') then
+                                               nvmeData        <= std_logic_vector(unsigned(nvmeData) + 1);
+                                               nvmeState       <= NVME_STATE_READDATA;
+                                       end if;
+
+                               when NVME_STATE_READDATA =>
+                                       if(nvmeReply.ready = '1' and nvmeReply.valid = '1') then
+                                               nvmeData1       <= nvmeData;
+                                               nvmeData        <= std_logic_vector(unsigned(nvmeData) + 1);
+
+                                               if(nvmeChunkCount = 4) then
+                                                       if(nvmeCount = 4) then
+                                                               nvmeReply.last  <= '0';
+                                                               nvmeReply.valid <= '0';
+                                                               nvmeState       <= NVME_STATE_IDLE;
+                                                       else
+                                                               nvmeReply.last  <= '0';
+                                                               nvmeReply.valid <= '0';
+                                                               nvmeState       <= NVME_STATE_READHEAD;
+                                                       end if;
+
+                                               elsif(nvmeChunkCount = 8) then
+                                                       nvmeReply.keep <= zeros(4) & ones(12);
+                                                       nvmeReply.last <= '1';
+
+                                               else
+                                                       nvmeReply.last <= '0';
+                                               end if;
+                                               
+                                               nvmeChunkCount                  <= nvmeChunkCount - 4;
+                                               nvmeCount                       <= nvmeCount - 4;
+                                               nvmeRequestHead1.address        <= nvmeRequestHead1.address + 4;
+                                       end if;
+                               end case;
+                       end if;
+               end if;
+       end process;
+
+       stop : process
+       begin
+               wait for 2000 ns;
+               assert false report "simulation ended ok" severity failure;
+       end process;
+end;
index 05d70adbb3e5c3f2f2ac989e6a464206d6cdde7f..4ff6eb908cad6548d3ca2c39e4c5e731164ab9ad 100644 (file)
@@ -9,9 +9,10 @@
 --! @version   0.0.1
 --!
 --! @brief
---! This module provides the data input fifo for the NvmeStorage module.
+--! This module provides a data input fifo for the NvmeWrite module.
 --!
 --! @details
+--! This FIFO will store a complete DataWiteChunk's worth of data, 32 kBytes.
 --! 
 --!
 --! @copyright GNU GPL License
@@ -40,64 +41,82 @@ use work.NvmeStorageIntPkg.all;
 
 entity DataFifo is
 generic(
-       DataWriteQueueNum       : integer := 4;                 --! The number of DataWrite queue entries
-       ChunkSize               : integer := 8192;              --! The chunk size in Bytes.
-       FifoSize                : integer := 4 * ChunkSize      --! The Fifo size in Bytes
+       FifoSize        : integer := 2048                       --! The Fifo size
 );
 port (
        clk             : in std_logic;                         --! The interface clock line
        reset           : in std_logic;                         --! The active high reset line
 
-       dataInEnable    : in std_logic;                         --! Allow data input to particular Fifo
-       dataInQueue     : in std_logic_vector(log2(DataWriteQueueNum)-1 downto 0);      --! The ingest Fifo number
+       full            : out std_logic;                        --! The fifo is full (Has Fifo size words)
+       empty           : out std_logic;                        --! The fifo is empty
+
        dataIn          : inout AxisStreamType := AxisInput;    --! Input data stream
-       
-       dataOutQueue    : in std_logic_vector(log2(DataWriteQueueNum)-1 downto 0);      --! The output Fifo number
        dataOut         : inout AxisStreamType := AxisOutput    --! Output data stream
 );
 end;
 
 architecture Behavioral of DataFifo is
 
-component fifo32k
-port(
-       s_aclk : in std_logic;
-       s_aresetn : in std_logic;
-       s_axis_tvalid : in std_logic;
-       s_axis_tready : out std_logic;
-       s_axis_tdata : in std_logic_vector(127 downto 0);
-       s_axis_tlast : in std_logic;
-       m_axis_tvalid : out std_logic;
-       m_axis_tready : in std_logic;
-       m_axis_tdata : out std_logic_vector(127 downto 0);
-       m_axis_tlast : out std_logic;
-       axis_prog_full : out std_logic
+component Fifo4k
+port (
+       clk : in std_logic;
+       srst : in std_logic;
+       din : in std_logic_vector(127 downto 0);
+       wr_en : in std_logic;
+       rd_en : in std_logic;
+       dout : out std_logic_vector(127 downto 0);
+       full : out std_logic;
+       empty : out std_logic;
+       valid : out std_logic;
+       wr_rst_busy : out std_logic;
+       rd_rst_busy : out std_logic;
+       data_count : out std_logic_vector(8 downto 0)
+);
+end component;
+
+component Fifo32k
+port (
+       clk : in std_logic;
+       srst : in std_logic;
+       din : in std_logic_vector(127 downto 0);
+       wr_en : in std_logic;
+       rd_en : in std_logic;
+       dout : out std_logic_vector(127 downto 0);
+       full : out std_logic;
+       empty : out std_logic;
+       valid : out std_logic;
+       wr_rst_busy : out std_logic;
+       rd_rst_busy : out std_logic;
+       data_count : out std_logic_vector(11 downto 0)
 );
 end component;
 
 constant TCQ           : time := 1 ns;
-signal hasBlock                : std_logic;
+signal fifo_full       : std_logic:= '0';
+signal fifo_empty      : std_logic:= '0';
+signal fifo_count      : std_logic_vector(11 downto 0) := (others => '0');
 
 begin
-       -- Output data stream
-       dataOut.valid <= dataIn.valid;
-       dataOut.last <= dataIn.last;
-       dataIn.ready <= dataOut.ready;
-       dataOut.data <= dataIn.data;
+       -- Stream signals
+       dataIn.ready <= not fifo_full when(reset = '0') else '0';
+       full <= '1' when((reset = '0') and (unsigned(fifo_count) >=  FifoSize)) else '0';
+       empty <= fifo_empty;
+       dataOut.valid <= not fifo_empty;
+       dataOut.last <= '0';
        
-       fifo32k0 : Fifo32k
+       fifo0: Fifo32k
        port map (
-               s_aclk          => clk,
-               s_aresetn       => not reset,
-               s_axis_tready   => dataIn.ready,
-               s_axis_tvalid   => dataIn.valid,
-               s_axis_tlast    => dataIn.last,
-               s_axis_tdata    => dataIn.data,
-               
-               m_axis_tready   => dataOut.ready,
-               m_axis_tvalid   => dataOut.valid,
-               m_axis_tlast    => dataOut.last,
-               m_axis_tdata    => dataOut.data,
-               axis_prog_full  => hasBlock
+               clk             => clk,
+               srst            => reset,
+               din             => dataIn.data,
+               wr_en           => dataIn.valid,
+               rd_en           => dataOut.ready,
+               dout            => dataOut.data,
+               full            => fifo_full,
+               empty           => fifo_empty,
+               --valid         => dataOut.valid,
+               --wr_rst_busy   =>
+               --rd_rst_busy   =>
+               data_count      => fifo_count
        );
 end;
index 6f5ad7f0dd5d6df61ba19be4622289936240d5b3..40de871591071d32f816acc517a620a7d2ff7270 100644 (file)
@@ -191,7 +191,7 @@ port (
        hostRecv        : inout AxisStreamType := AxisOutput;                        
        
        -- AXIS data stream input
-       --dataRx        : inout AxisStreamType  := AxisInput;
+       dataIn          : inout AxisStreamType  := AxisInput;
        
        -- NVMe interface
        nvme_clk_p      : in std_logic;
@@ -207,6 +207,22 @@ port (
 );
 end component;
 
+component TestData is
+generic(
+       BlockSize       : integer := 4096                       --! The block size in Bytes.
+);
+port (
+       clk             : in std_logic;                         --! The interface clock line
+       reset           : in std_logic;                         --! The active high reset line
+
+       -- Control and status interface
+       enable          : in std_logic;                         --! Enable production of data
+
+       -- AXIS data output
+       dataStream      : inout AxisStreamType := AxisOutput    --! Output data stream
+);
+end component;
+
 -- Clock and controls
 signal sys_clk                 : std_logic := 'U';
 signal sys_reset_buf_n         : std_logic := 'U';
@@ -233,6 +249,7 @@ signal hostSend                     : AxisStreamType;
 signal hostRecv                        : AxisStreamType;
 signal nvmeReq                 : AxisStreamType;
 signal nvmeReply               : AxisStreamType;
+signal dataIn                  : AxisStreamType;
 
 begin
        -- System clock just used for a boot reset
@@ -411,7 +428,7 @@ begin
                hostRecv        => hostRecv,
 
                -- AXIS data stream input
-               --dataRx        => dataRx,
+               dataIn  => dataIn,
 
                -- NVMe interface
                nvme_clk_p      => nvme_clk_p,
@@ -433,7 +450,19 @@ begin
        nvmeReply.data  <= nvmeReq.data;  
        nvmeReq.ready   <= nvmeReply.ready;
 
+       -- The test data interface
+       testData0 : TestData
+       port map (
+               clk             => axil_clk,
+               reset           => axil_reset,
+
+               enable          => '1',
+
+               dataStream      => dataIn
+       );
        end generate;
+       
+
 
        -- Led buffers
        obuf_leds: for i in 0 to 7 generate
index 0b3e6ab0d8f0816ff98b1f9fd677edf6a5003dfe..0401950c3316b3ccbbdd295a75f888c5b904326c 100644 (file)
@@ -65,7 +65,7 @@ architecture Behavioral of NvmeConfig is
 --! Set the fields in the PCIe TLP header
 function setHeader(request: integer; address: integer; count: integer; tag: integer) return std_logic_vector is
 begin
-       return to_stl(set_PcieRequestHeadType(2, request, address, count, tag));
+       return to_stl(set_PcieRequestHeadType(3, request, address, count, tag));
 end function;
 
 
@@ -87,15 +87,15 @@ constant rom        : RomType(0 to 27) := (
        setHeader(1, 16#0024#, 1, 0), to_stl(x"00070007", 128),
 
        -- Admin request queue base address
-       setHeader(1, 16#0028#, 1, 0), to_stl(x"05000000", 128),
+       setHeader(1, 16#0028#, 1, 0), to_stl(x"02000000", 128),
 
        -- Admin reply queue base address
-       setHeader(1, 16#0030#, 1, 0), to_stl(x"05100000", 128),
+       setHeader(1, 16#0030#, 1, 0), to_stl(x"02100000", 128),
 
        -- Create DataWrite reply queue (8 entries)  by sending 64byte request to Admin queue
-       setHeader(12, 16#05000000#, 16, 0),
+       setHeader(12, 16#02000000#, 16, 0),
                concat('0', 96) & x"02000005",                          -- Dwords 3, 2, 1, 0
-               concat('0', 32) & x"05110000" & concat('0', 64),        -- DWords 7, 6, 5, 4
+               concat('0', 32) & x"02110000" & concat('0', 64),        -- DWords 7, 6, 5, 4
                x"00000001" & x"00070001" & concat('0', 64),            -- DWords 11, 10, 9, 8
                concat('0', 128),                                       -- DWords 15, 14, 13, 12
 
@@ -105,9 +105,9 @@ constant rom        : RomType(0 to 27) := (
        -- Wait for reply in queue, how to do this ???
 
        -- Create DataWrite request queue by sending 64byte request to Admin queue
-       setHeader(12, 16#05000000#, 16, 0),
+       setHeader(12, 16#02000000#, 16, 0),
                concat('0', 96) & x"02000001",                          -- Dwords 3, 2, 1, 0
-               concat('0', 32) & x"05010000" & concat('0', 64),        -- DWords 7, 6, 5, 4
+               concat('0', 32) & x"02010000" & concat('0', 64),        -- DWords 7, 6, 5, 4
                x"00000001" & x"00070001" & concat('0', 64),            -- DWords 11, 10, 9, 8
                concat('0', 128),                                       -- DWords 15, 14, 13, 12
 
@@ -123,28 +123,6 @@ constant rom       : RomType(0 to 27) := (
        (others => '0')
        );
 
-constant rom1  : RomType(0 to 12) := (
-       -- Set PCIe configuration command word
-       setHeader(10, 16#0004#, 1, 0),  to_stl(16#00000006#, 128),
-       
-       -- Disable interrupts
-       setHeader(1, 16#000C#, 1, 0), to_stl(x"FFFFFFFF", 128),
-
-       -- Admin queue lengths to 8 entries each
-       setHeader(1, 16#0024#, 1, 0), to_stl(x"00070007", 128),
-
-       -- Admin request queue base address
-       setHeader(1, 16#0028#, 1, 0), to_stl(x"05000000", 128),
-
-       -- Admin reply queue base address
-       setHeader(1, 16#0030#, 1, 0), to_stl(x"05100000", 128),
-
-       -- Start controller
-       setHeader(1, 16#0014#, 1, 0), to_stl(x"00460001", 128),
-
-       --(others => '0'),
-       (others => '0')
-       );
 
 signal requestHead     : PcieRequestHeadType;                  --! The PCIe TLP request header fields
 signal tag             : unsigned(7 downto 0);
index d1150ca286768847232cd221240b4135e18f2496..8c427a8c630f6b1ad88c9bb9cd1578fa489adfbc 100644 (file)
@@ -208,7 +208,7 @@ begin
                                                        -- Perform bus master write request to doorbell register on Nvme (0x1000, 0x1008, 0x1010 ...)
                                                        doorbellReqHead.address <= to_unsigned(16#000010#, doorbellReqHead.address'length - 8) & to_unsigned(queueIn * 8, 8);
                                                        doorbellReqHead.tag     <= x"44";
-                                                       doorbellReqHead.requesterId     <= to_unsigned(5, doorbellReqHead.requesterId'length);
+                                                       doorbellReqHead.requesterId     <= to_unsigned(2, doorbellReqHead.requesterId'length);
                                                        doorbellReqHead.request <= "0001";
                                                        doorbellReqHead.count   <= to_unsigned(16#0001#, doorbellReqHead.count'length);
 
@@ -239,7 +239,7 @@ begin
                                        if((streamIn.ready = '1') and (streamIn.valid = '1')) then
                                                data1                                   <= streamIn.data;
                                                requestHead1.address(31 downto 24)      <= unsigned(streamIn.data(111 downto 104));
-                                               requestHead1.requesterId                <= to_unsigned(5, requestHead1.requesterId'length);
+                                               requestHead1.requesterId                <= to_unsigned(2, requestHead1.requesterId'length);
 
                                                streamIn.ready                          <= '0';
                                                streamOut.keep                          <= ones(16);
index 96c5c1dbc353cd6a724414f7ff672ea4e4168f5a..590ad94c530fb60dd7a3ae57442d02b12a9da551 100644 (file)
@@ -214,7 +214,7 @@ begin
 
                                when STATE_READ_QUEUE_START =>
                                        -- Perform bus master read request for queue data
-                                       nvmeRequestHead.address <= x"050" & to_unsigned(queue, 4) & x"0000";
+                                       nvmeRequestHead.address <= x"020" & to_unsigned(queue, 4) & x"0000";
                                        nvmeRequestHead.tag     <= x"44";
                                        nvmeRequestHead.requesterId     <= to_unsigned(0, nvmeRequestHead.requesterId'length);
                                        nvmeRequestHead.request <= "0000";
@@ -262,7 +262,7 @@ begin
                                                                -- Writes an entry into the Admin reply queue. Simply uses info in that last queued request. So only one request at a time.
                                                                -- Note data sent to queue is just the header reapeated so junk data ATM.
                                                                -- Perform bus master read request for data to write to NVMe
-                                                               nvmeRequestHead.address <= to_unsigned(16#05100000#, nvmeRequestHead.address'length);
+                                                               nvmeRequestHead.address <= to_unsigned(16#02100000#, nvmeRequestHead.address'length);
                                                                nvmeRequestHead.tag     <= x"44";
                                                                nvmeRequestHead.request <= "0001";
                                                                nvmeRequestHead.count   <= to_unsigned(16#0004#, nvmeRequestHead.count'length); -- 16 Byte queue entry
@@ -290,25 +290,28 @@ begin
 
                                when STATE_READ_DATA_START =>
                                        -- Perform bus master read request for data to write to NVMe
-                                       nvmeRequestHead.address <= to_unsigned(16#03000000#, nvmeRequestHead.address'length);
+                                       -- Hardcoded to address 0x04000000
+                                       nvmeRequestHead.address <= to_unsigned(16#04000000#, nvmeRequestHead.address'length);
                                        nvmeRequestHead.tag     <= x"44";
                                        nvmeRequestHead.request <= "0000";
-                                       nvmeRequestHead.count   <= to_unsigned(16#0020#, nvmeRequestHead.count'length); -- Test size of 32 DWords
+                                       nvmeRequestHead.count   <= to_unsigned(16#0040#, nvmeRequestHead.count'length); -- Test size of 64 DWords
                                        
                                        if(nvmeReq.valid = '1' and nvmeReq.ready = '1') then
-                                               count           <= nvmeRequestHead.count + 1;   -- Note ignoring 1 DWord in first 128 bits
+                                               count           <= nvmeRequestHead.count;       -- Note ignoring 1 DWord in first 128 bits
+                                               nvmeReq.last    <= '0';
                                                nvmeReq.valid   <= '0';
                                                nvmeReply.ready <= '1';
                                                state           <= STATE_READ_DATA_RECV_START;
                                        else
                                                nvmeReq.keep    <= ones(16);
+                                               nvmeReq.last    <= '1';
                                                nvmeReq.valid   <= '1';
                                        end if;
 
                                when STATE_READ_DATA_RECV_START =>
                                        -- Read in write data ignoring it
                                        if(nvmeReply.valid = '1' and nvmeReply.ready = '1') then
-                                               chunkCount      <= nvmeReplyHead.count + 1;
+                                               chunkCount      <= nvmeReplyHead.count;
                                                state           <= STATE_READ_DATA_RECV;
                                        end if;
 
@@ -319,6 +322,7 @@ begin
                                                        if(count = 4) then
                                                                nvmeReply.ready <= '0';
                                                                state           <= STATE_IDLE;
+                                                               --state         <= STATE_READ_DATA_START;
                                                        else
                                                                state           <= STATE_READ_DATA_RECV_START;
                                                        end if;
index c4a4c52092eca4fbf603f3b8ec64d6e6f243c39d..f6d52736db44ecb1ac66392812315e939ebb2956 100644 (file)
@@ -34,7 +34,11 @@ library work;
 use work.NvmeStoragePkg.all;
 
 package NvmeStorageIntPkg is
-       --! Generalaly useful functions
+       --! System constants
+       constant DataWriteQueueNum      : integer := 8;         --! The number of data write queue entries
+       constant PcieMaxPayloadSize     : integer := 32;        --! The maximum Pcie packet size in 32bit DWords
+       
+       --! Generaly useful functions
        function to_stl(v: integer; b: integer) return std_logic_vector;
        function to_stl(v: unsigned; b: integer) return std_logic_vector;
        function log2(v: integer) return integer;
index 3f8728b3bfcab796d53e29cfc230595f2121f7bb..afae929fa7d58410d69c5c8791c4aa86d2b93a40 100644 (file)
@@ -58,7 +58,7 @@ port (
        hostRecv        : inout AxisStreamType := AxisOutput;   --! Host reply stream
 
        -- AXIS data stream input
-       --dataRx        : inout AxisStreamType := AxisInput;    --! Raw data to save stream
+       dataIn          : inout AxisStreamType := AxisInput;    --! Raw data to save stream
 
        -- NVMe interface
        nvme_clk_p      : in std_logic;                         --! Nvme external clock +ve
@@ -293,6 +293,43 @@ port (
 );
 end component;
 
+component NvmeWrite is
+port (
+       clk             : in std_logic;                         --! The interface clock line
+       reset           : in std_logic;                         --! The active high reset line
+
+       enable          : in std_logic;                         --! Enable the data writing process
+       dataIn          : inout AxisStreamType := AxisInput;    --! Raw data to save stream
+
+       -- To Nvme Request/reply streams
+       requestOut      : inout AxisStreamType := AxisOutput;   --! To Nvme request stream (3)
+       replyIn         : inout AxisStreamType := AxisInput;    --! from Nvme reply stream
+
+       -- From Nvme Request/reply streams
+       memReqIn        : inout AxisStreamType := AxisInput;    --! From Nvme request stream (4)
+       memReplyOut     : inout AxisStreamType := AxisOutput;   --! To Nvme reply stream
+       
+       regAddress      : in unsigned(1 downto 0);              --! Status register to read
+       regData         : out std_logic_vector(31 downto 0)     --! Status register contents
+);
+end component;
+
+component TestData is
+generic(
+       BlockSize       : integer := 4096                       --! The block size in Bytes.
+);
+port (
+       clk             : in std_logic;                         --! The interface clock line
+       reset           : in std_logic;                         --! The active high reset line
+
+       -- Control and status interface
+       enable          : in std_logic;                         --! Enable production of data
+
+       -- AXIS data output
+       dataStream      : inout AxisStreamType := AxisOutput    --! Output data stream
+);
+end component;
+
 signal reset_local_run         : std_logic := '0';
 signal reset_local_done                : std_logic := '0';
 signal reset_local_active      : std_logic := '0';
@@ -309,11 +346,17 @@ alias nvmeSend                    is streamSend(0);
 alias nvmeRecv                 is streamRecv(0);
 alias hostSend1                        is streamSend(1);
 alias hostRecv1                        is streamRecv(1);
-alias configSend               is streamSend(2);
-alias configRecv               is streamRecv(2);
-alias queueSend                        is streamSend(5);
-alias queueRecv                        is streamRecv(5);
-
+alias queueSend                        is streamSend(2);
+alias queueRecv                        is streamRecv(2);
+alias configSend               is streamSend(3);
+alias configRecv               is streamRecv(3);
+alias writeSend                        is streamSend(4);
+alias writeRecv                        is streamRecv(4);
+alias writeMemSend             is streamSend(5);
+alias writeMemRecv             is streamRecv(5);
+
+signal dataIn1                 : AxisStreamType;
+signal dataIn2                 : AxisStreamType;
 signal streamNone              : AxisStreamType := AxisOutput;
 signal streamSink              : AxisStreamType := AxisSink;
 
@@ -346,12 +389,17 @@ signal address                    : std_logic_vector(3 downto 0) := (others => '0');
 signal reg_id                  : RegDataType := x"56010200";
 signal reg_control             : RegDataType := (others => '0');
 signal reg_status              : RegDataType := (others => '0');
+signal reg_nvmeWrite           : RegDataType := (others => '0');
 
 -- Nvme configuration signals
 signal configStart             : std_logic := 'U';
 signal configStartDone         : std_logic := 'U';
 signal configComplete          : std_logic := 'U';
 
+-- Nvme data write signals
+signal writeEnable             : std_logic := 'U';
+
+
 -- Pcie_nvme signals
 signal nvme_clk                        : std_logic := 'U';
 signal nvme_clk_gt             : std_logic := 'U';
@@ -415,16 +463,29 @@ begin
                streamTx        => hostRecv
        );
        
+       axisClockConverter2 :  AxisClockConverter
+       port map (
+               clkRx           => clk,
+               resetRx         => reset,
+               streamRx        => dataIn,
+
+               clkTx           => nvme_user_clk,
+               resetTx         => nvme_user_reset,
+               streamTx        => dataIn1
+       );
+
+       
        -- Register access
        axil1Out.rdata <=       reg_id when address = "0000" else
                                reg_control when address = "0001" else
                                reg_status when address = "0010" else
+                               reg_nvmeWrite when(address(3 downto 2) = "10") else
                                x"FFFFFFFF";
        
        -- Status register bits
        reg_status(0)           <= reset_local_run;
-       reg_status(1)           <= nvme_user_reset;
-       reg_status(2)           <= configComplete;
+       reg_status(1)           <= configComplete;
+       reg_status(2)           <= '0';
        reg_status(31 downto 3) <= (others => '0');
                
        -- Always return OK to read and write requests
@@ -724,10 +785,6 @@ begin
        
        -- Full switched communications
        gen03: if true generate
-       set0: for i in 3 to 4 generate
-               streamSend(i).valid     <= '0';
-               streamRecv(i).ready     <= '1';
-       end generate;
        set1: for i in 6 to 7 generate
                streamSend(i).valid     <= '0';
                streamRecv(i).ready     <= '1';
@@ -771,8 +828,8 @@ begin
                                configStart     <= '0';
                                configStartDone <= '0';
                        else
-                               --if((configStartDone = '0') and (configComplete = '0') and (reg_control(1) = '1')) then
-                               if(configStartDone = '0') then
+                               if((configStartDone = '0') and (configComplete = '0') and (reg_control(1) = '1')) then
+                               --if(configStartDone = '0') then
                                        configStart     <= '1' after TCQ;       -- Start the Nvme configuration
                                        configStartDone <= '1';
                                else
@@ -781,6 +838,39 @@ begin
                        end if;
                end if;
        end process;
+       
+       -- The Data write processing
+       writeEnable <= reg_control(2);
+       
+       nvmeWrite0: NvmeWrite
+       port map (
+               clk             => nvme_user_clk,
+               reset           => nvme_user_reset,
+
+               enable          => writeEnable,
+               dataIn          => dataIn2,
+
+               requestOut      => writeSend,
+               replyIn         => writeRecv,
+
+               memReqIn        => writeMemRecv,
+               memReplyOut     => writeMemSend,
+               
+               regAddress      => unsigned(address(1 downto 0)),
+               regData         => reg_nvmeWrite
+       );
+
+       -- The test data interface
+       testData0 : TestData
+       port map (
+               clk             => nvme_user_clk,
+               reset           => nvme_user_reset,
+
+               enable          => writeEnable,
+
+               dataStream      => dataIn2
+       );
+
        end generate;
        
 end;
index 12cc355ce34d329e4e4b319e42dcc4f5b4364290..e93eaa6e431b336a07dd800c5862def49ac58942 100644 (file)
@@ -43,12 +43,19 @@ port (
        clk             : in std_logic;                         --! The interface clock line
        reset           : in std_logic;                         --! The active high reset line
 
-       dataAvailable   : in std_logic;                         --! At least 1 x 8k chunk of data is available to write
-       dataRx          : inout AxisStreamType := AxisInput;    --! Raw data to save stream
+       enable          : in std_logic;                         --! Enable the data writing process
+       dataIn          : inout AxisStreamType := AxisInput;    --! Raw data to save stream
 
-       -- From host to NVMe request/reply streams
-       nvmeSend        : inout AxisStreamType := AxisOutput;   --! Nvme request stream
-       nvmeRecv        : inout AxisStreamType := AxisInput             --! Nvme reply stream
+       -- To Nvme Request/reply streams
+       requestOut      : inout AxisStreamType := AxisOutput;   --! To Nvme request stream (3)
+       replyIn         : inout AxisStreamType := AxisInput;    --! from Nvme reply stream
+
+       -- From Nvme Request/reply streams
+       memReqIn        : inout AxisStreamType := AxisInput;    --! From Nvme request stream (4)
+       memReplyOut     : inout AxisStreamType := AxisOutput;   --! To Nvme reply stream
+       
+       regAddress      : in unsigned(1 downto 0);              --! Status register to read
+       regData         : out std_logic_vector(31 downto 0)     --! Status register contents
 );
 end;
 
@@ -57,47 +64,245 @@ architecture Behavioral of NvmeWrite is
 --! Set the fields in the PCIe TLP header
 function setHeader(request: integer; address: integer; count: integer; tag: integer) return std_logic_vector is
 begin
-       return set_PcieRequestHeadType(request, address, count, tag);
+       return to_stl(set_PcieRequestHeadType(3, request, address, count, tag));
 end function;
 
 constant TCQ           : time := 1 ns;
 
-type StateType         is (STATE_IDLE, STATE_NEXT_ITEM, STATE_NEXT_DATA, STATE_ITEM_COMPLETE);
+component DataFifo is
+generic(
+       --FifoSize      : integer := 2048                       --! The Fifo size
+       FifoSize        : integer := 16                         --! The Fifo size
+       --FifoSize      : integer := 1024                       --! The Fifo size in 128bit words
+);
+port (
+       clk             : in std_logic;                         --! The interface clock line
+       reset           : in std_logic;                         --! The active high reset line
+
+       full            : out std_logic;                        --! The fifo is full (Has Fifo size words)
+       empty           : out std_logic;                        --! The fifo is empty
+
+       dataIn          : inout AxisStreamType := AxisInput;    --! Input data stream
+       dataOut         : inout AxisStreamType := AxisOutput    --! Output data stream
+);
+end component;
+
+type StateType         is (STATE_IDLE,
+                               STATE_QUEUE_HEAD, STATE_QUEUE_0, STATE_QUEUE_1, STATE_QUEUE_2, STATE_QUEUE_3,
+                               STATE_QUEUE_REPLY1, STATE_QUEUE_REPLY2,
+                               STATE_COMPLETE);
 signal state           : StateType := STATE_IDLE;
 
+signal fifo_full       : std_logic := '0';
+signal fifo_empty      : std_logic := '0';
+signal dataOut         : AxisStreamType;
+signal blockNumber     : unsigned(63 downto 0) := (others => '0');
+
+type MemStateType      is (MEMSTATE_IDLE, MEMSTATE_READHEAD, MEMSTATE_READDATA);
+signal memState                : MemStateType := MEMSTATE_IDLE;
+signal memRequestHead  : PcieRequestHeadType;
+signal memRequestHead1 : PcieRequestHeadType;
+signal memReplyHead    : PcieReplyHeadType;
+signal memCount                : unsigned(10 downto 0);                        -- DWord data send count
+signal memChunkCount   : unsigned(10 downto 0);                        -- DWord data send within a chunk count
+signal memData         : std_logic_vector(127 downto 0);
+
+-- Status information
+signal status          : unsigned(31 downto 0) := (others => '0');     -- The system status
+signal numBlocks       : unsigned(31 downto 0) := (others => '0');     -- The number of blocks written
+signal timeUs          : unsigned(31 downto 0) := (others => '0');     -- The time in us
+signal timeCounter     : integer range 0 to 125 := 0;
+
 begin
-       -- Process register access
+       -- Input data FIFO's, one per WriteQueue entry. Just the one for now.
+       dataFifo0 : DataFifo
+       port map (
+               clk             => clk,
+               reset           => reset,
+
+               full            => fifo_full,
+               empty           => fifo_empty,
+
+               dataIn          => dataIn,
+               dataOut         => dataOut
+       );
+       
+       -- Regsiter access
+       regData <= std_logic_vector(status) when(regAddress = 0)
+                       else std_logic_vector(numBlocks) when(regAddress = 1)
+                       else std_logic_vector(timeUs);
+       
+       -- Process data input
        process(clk)
        begin
                if(rising_edge(clk)) then
                        if(reset = '1') then
-                               nvmeSend.valid          <= '0';
-                               nvmeSend.last           <= '0';
-                               nvmeSend.keep           <= (others => '1');
+                               requestOut.valid        <= '0';
+                               requestOut.last         <= '0';
+                               requestOut.keep         <= (others => '1');
+                               replyIn.ready           <= '1';
+                               blockNumber             <= (others => '0');
+                               numBlocks               <= (others => '0');
+                               timeUs                  <= (others => '0');
+                               status                  <= (others => '0');
+                               timeCounter             <= 0;
                                state                   <= STATE_IDLE;
                        else
                                case(state) is
                                when STATE_IDLE =>
-                                       if(dataAvailable = '1') then
-                                               state   <= STATE_NEXT_ITEM;
+                                       if((enable = '1') and (fifo_full = '1') and (numBlocks < 4)) then
+                                               requestOut.data         <= setHeader(1, 16#02010000#, 16, 0);
+                                               requestOut.valid        <= '1';
+                                               state                   <= STATE_QUEUE_HEAD;
+                                       end if;
+
+                               when STATE_QUEUE_HEAD =>
+                                       if(requestOut.valid = '1' and requestOut.ready = '1') then
+                                               requestOut.data <= zeros(64) & x"00000001" & x"04000001";       -- Namespace 1, From stream4, opcode 1
+                                               state           <= STATE_QUEUE_0;
+                                       end if;
+
+                               when STATE_QUEUE_0 =>
+                                       if(requestOut.valid = '1' and requestOut.ready = '1') then
+                                               requestOut.data <= zeros(32) & x"05000000" & zeros(64); -- Data source address
+                                               --requestOut.data       <= zeros(32) & x"01800000" & zeros(64); -- Data source address
+                                               state           <= STATE_QUEUE_1;
+                                       end if;
+
+                               when STATE_QUEUE_1 =>
+                                       if(requestOut.valid = '1' and requestOut.ready = '1') then
+                                               requestOut.data <= std_logic_vector(blockNumber) & zeros(64);
+                                               state           <= STATE_QUEUE_2;
+                                       end if;
+
+                               when STATE_QUEUE_2 =>
+                                       if(requestOut.valid = '1' and requestOut.ready = '1') then
+                                               --requestOut.data       <= zeros(96) & x"00000000";     -- WriteMethod, NumBlocks (0 is 1 block)
+                                               requestOut.data <= zeros(96) & x"00000003";     -- WriteMethod, NumBlocks (0 is 1 block)
+                                               requestOut.last <= '1';
+                                               state           <= STATE_QUEUE_3;
+                                       end if;
+
+                               when STATE_QUEUE_3 =>
+                                       if(requestOut.valid = '1' and requestOut.ready = '1') then
+                                               requestOut.last         <= '0';
+                                               requestOut.valid        <= '0';
+                                               numBlocks               <= numBlocks + 1;
+                                               replyIn.ready           <= '1';
+                                               state                   <= STATE_QUEUE_REPLY1;
                                        end if;
 
-                               when STATE_NEXT_ITEM =>
-                                       state   <= STATE_NEXT_DATA;
-                                       
+                               when STATE_QUEUE_REPLY1 =>
+                                       if(replyIn.valid = '1' and replyIn.ready = '1') then
+                                               state   <= STATE_QUEUE_REPLY2;
+                                       end if;
 
-                               when STATE_NEXT_DATA =>
-                                       if(nvmeSend.valid = '1' and nvmeSend.ready = '1') then
-                                               nvmeSend.data   <= (others => '0');
-                                               state           <= STATE_ITEM_COMPLETE;
+                               when STATE_QUEUE_REPLY2 =>
+                                       if(replyIn.valid = '1' and replyIn.ready = '1') then
+                                               --replyIn.ready <= '0';
+                                               --state         <= STATE_IDLE;
                                        end if;
 
-                               when STATE_ITEM_COMPLETE =>
-                                       nvmeSend.valid  <= '0';
-                                       nvmeSend.last   <= '0';
+                               when STATE_COMPLETE =>
+                                       requestOut.valid <= '0';
+                                       requestOut.last         <= '0';
                                        state           <= STATE_IDLE;
 
                                end case;
+                               
+                               if(timeCounter = 125) then
+                                       timeUs          <= timeUs + 1;
+                                       timeCounter     <= 0;
+                               else
+                                       timeCounter     <= timeCounter + 1;
+                               end if;
+                       end if;
+               end if;
+       end process;
+       
+       -- Process Nvme read data requests
+       dataOut.ready <= memReplyOut.ready and not memReplyOut.last when((memState = MEMSTATE_READHEAD) or (memState = MEMSTATE_READDATA)) else '0';
+       memRequestHead  <= to_PcieRequestHeadType(memReqIn.data);
+       memReplyOut.data <= dataOut.data(31 downto 0) & to_stl(memReplyHead) when(memState = MEMSTATE_READHEAD)
+               else dataOut.data(31 downto 0) & memData(127 downto 32);
+
+       process(clk)
+       begin
+               if(rising_edge(clk)) then
+                       if(reset = '1') then
+                               memReqIn.ready  <= '0';
+                               memState        <= MEMSTATE_IDLE;
+                       else
+                               case(MEMSTATE) is
+                               when MEMSTATE_IDLE =>
+                                       if((memReqIn.ready = '1') and (memReqIn.valid = '1')) then
+                                               memRequestHead1 <= memRequestHead;
+                                               memCount        <= memRequestHead.count;
+
+                                               if(memRequestHead.request = 0) then
+                                                       memReqIn.ready  <= '0';
+                                                       memState        <= MEMSTATE_READHEAD;
+                                               end if;
+                                       else
+                                               memReqIn.ready <= '1';
+                                       end if;
+
+                               when MEMSTATE_READHEAD =>
+                                       if(dataOut.valid = '1') then
+                                               memReplyHead.byteCount          <= memCount & "00";
+                                               memReplyHead.address            <= memRequestHead1.address(memReplyHead.address'length - 1 downto 0);
+                                               memReplyHead.error              <= (others => '0');
+                                               memReplyHead.status             <= (others => '0');
+                                               memReplyHead.tag                <= memRequestHead1.tag;
+                                               memReplyHead.requesterId        <= memRequestHead1.requesterId;
+
+                                               if(memCount > PcieMaxPayloadSize) then
+                                                       memReplyHead.count      <= to_unsigned(PcieMaxPayloadSize, memReplyHead.count'length);
+                                                       memChunkCount           <= to_unsigned(PcieMaxPayloadSize, memReplyHead.count'length);
+                                               else
+                                                       memReplyHead.count      <= memCount;
+                                                       memChunkCount           <= memCount;
+                                               end if;
+
+                                               memData                 <= dataOut.data;
+                                               memReplyOut.keep        <= (others => '1');
+                                               memReplyOut.valid       <= '1';
+
+                                               if(memReplyOut.ready = '1' and memReplyOut.valid = '1') then
+                                                       memState        <= MEMSTATE_READDATA;
+                                               end if;
+                                       end if;
+                               
+                               when MEMSTATE_READDATA =>
+                                       if(memReplyOut.ready = '1' and memReplyOut.valid = '1') then
+                                               -- Should we also check dataOut.valid ?
+                                               memData         <= dataOut.data;
+
+                                               if(memChunkCount = 4) then
+                                                       if(memCount = 4) then
+                                                               memReplyOut.last        <= '0';
+                                                               memReplyOut.valid       <= '0';
+                                                               memState                <= MEMSTATE_IDLE;
+                                                       else
+                                                               memReplyOut.last        <= '0';
+                                                               memReplyOut.valid       <= '0';
+                                                               memState                <= MEMSTATE_READHEAD;
+                                                       end if;
+
+                                               elsif(memChunkCount = 8) then
+                                                       memReplyOut.keep <= zeros(4) & ones(12);
+                                                       memReplyOut.last <= '1';
+
+                                               else
+                                                       memReplyOut.last <= '0';
+                                               end if;
+
+                                               memChunkCount           <= memChunkCount - 4;
+                                               memCount                <= memCount - 4;
+                                               memRequestHead1.address <= memRequestHead1.address + 16;
+                                       end if;
+
+                               end case;
                        end if;
                end if;
        end process;
index ff4d1fbc4c624f75d467376c351eea49e93ce866..deb8dd068d6ab33d3269fa5a2e76ecee46fe9a4c 100644 (file)
@@ -1,18 +1,25 @@
 --------------------------------------------------------------------------------
---     StreamSwitch.vhd Multiplex/De-multiplex a stream into two using header
+--     StreamSwitch.vhd Send PCIe packets between separate streams.
 --     T.Barnaby, Beam Ltd. 2020-04-08
 -------------------------------------------------------------------------------
 --!
 --! @class     StreamSwitch
 --! @author    Terry Barnaby (terry.barnaby@beam.ltd.uk)
 --! @date      2020-04-08
---! @version   0.0.1
+--! @version   0.2
 --!
 --! @brief
---! This module Multiplex/De-multiplex a stream a 128bit Axis stream into two stream using the 128bit header
+--! This module implements a PCIe packet switch transfering packets between streams.
 --!
 --! @details
---! 
+--! This switch sends PCIe packets between streams. There are two AXI streams per logical stream
+--! one is for input packets and one for output packets. Streams are numbered 0 to NumStreams-1.
+--! It expects Xilinx PCIe Gen3 PCIe packet headers to be used.
+--! Packets are switched based on the address fields bits 27 downto 24 in the case of request packets
+--! and on the requesterId field in the case of replies.
+--! The switch uses a priority based on the input stream number, with 0 being the highest priority.
+--! When the switch sees a valid signal on one of the streams and its desitation stream is ready then
+--! the switch will send a complete packet, using the "last" signal to denote the end of packet.
 --!
 --! @copyright GNU GPL License
 --! Copyright (c) Beam Ltd, All rights reserved. <br>
@@ -61,9 +68,16 @@ signal switchState   : StateType := SWITCH_STATE_IDLE;
 signal switchIn                : integer range 0 to NumStreams-1 := 0;
 signal switchOut       : integer range 0 to NumStreams-1 := 0;
 
-function streamFromAddress(address: unsigned) return integer is
+function streamOutNum(header: std_logic_vector) return integer is
+variable num: integer;
 begin
-       return to_integer(address(27 downto 24));
+       if(to_PcieReplyHeadType(header).reply = '1') then
+               num := to_integer(to_PcieReplyHeadType(header).requesterId);
+       else
+               num := to_integer(to_PcieRequestHeadType(header).address(27 downto 24));
+       end if;
+
+       return num;
 end function;
 
 begin
@@ -75,7 +89,6 @@ begin
                streamOut(i).data       <= streamIn(switchIn).data when((switchState = SWITCH_STATE_TRANSFER) and (i = switchOut)) else (others => '0');
        end generate;
 
-
        -- Process stream
        process(clk)
        begin
@@ -85,16 +98,12 @@ begin
                        else
                                case(switchState) is
                                when SWITCH_STATE_IDLE =>
-                                       --! *** We should realy check ready status on output stream to reduce lockups ***
+                                       -- Decide on which swtream to send to based on valid and ready signals in stream number priority order (stream 0 highest)
                                        for i in 0 to NumStreams-1 loop
-                                               if(streamIn(i).valid = '1') then
-                                                       switchIn <= i;
-                                                       if(to_PcieReplyHeadType(streamIn(i).data).reply = '1') then
-                                                               switchOut <= to_integer(to_PcieReplyHeadType(streamIn(i).data).requesterId);
-                                                       else
-                                                               switchOut <= streamFromAddress(to_PcieRequestHeadType(streamIn(i).data).address);
-                                                       end if;
-                                                       switchState <= SWITCH_STATE_TRANSFER;
+                                               if((streamIn(i).valid = '1') and (streamOut(streamOutNum(streamIn(i).data)).ready = '1')) then
+                                                       switchIn        <= i;
+                                                       switchOut       <= streamOutNum(streamIn(i).data);
+                                                       switchState     <= SWITCH_STATE_TRANSFER;
                                                        exit;
                                                end if;
                                        end loop;
index d5fb0de0d4dee9f052b583539e9af2d45dad2ce0..47e5f83ce9f53d83bae33ccc2180e275b094f94a 100644 (file)
@@ -60,12 +60,12 @@ architecture Behavioral of TestData is
 constant TCQ           : time := 1 ns;
 constant BytesPerWord  : integer := 16;        -- Number of bytes per Axis data word
 
-signal data            : std_logic_vector(31 downto 0) := (others => '0');
-signal countBlock      : std_logic_vector(log2(BlockSize/BytesPerWord)-1 downto 0) := (others => '0');
+signal data            : unsigned(31 downto 0) := (others => '0');
+signal countBlock      : unsigned(log2(BlockSize/BytesPerWord)-1 downto 0) := (others => '0');
 
 begin
        -- Output incrementing data stream
-       dataStream.data <= (data + 3) & (data + 2) & (data + 1) & data;
+       dataStream.data <= std_logic_vector((data + 3) & (data + 2) & (data + 1) & data);
                
        -- Generate data stream
        process(clk)
diff --git a/source/DuneNvme/src/ip/Fifo32k.xci b/source/DuneNvme/src/ip/Fifo32k.xci
new file mode 100644 (file)
index 0000000..3be5f59
--- /dev/null
@@ -0,0 +1,590 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>Fifo32k</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="fifo_generator" spirit:version="13.2"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.ASSOCIATED_BUSIF"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.ASSOCIATED_RESET"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MASTER_ACLK.ASSOCIATED_RESET"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MASTER_ACLK.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MASTER_ACLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MASTER_ACLK.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MASTER_ACLK.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.ADDR_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.ARUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.AWUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.BUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.DATA_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BRESP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BURST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_CACHE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_LOCK">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_PROT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_QOS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_REGION">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_RRESP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_WSTRB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.ID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.MAX_BURST_LENGTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_READ_OUTSTANDING">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_READ_THREADS">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_WRITE_OUTSTANDING">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_WRITE_THREADS">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.PROTOCOL">AXI4LITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.RUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.SUPPORTS_NARROW_BURST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.WUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.WUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TKEEP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TLAST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TREADY">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TSTRB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.LAYERED_METADATA">undef</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.TDATA_NUM_BYTES">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.TDEST_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.TID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.TUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.READ_CLK.ASSOCIATED_BUSIF"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.READ_CLK.ASSOCIATED_RESET"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.READ_CLK.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.READ_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.READ_CLK.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.READ_CLK.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLAVE_ACLK.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLAVE_ACLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLAVE_ACLK.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLAVE_ACLK.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLAVE_ARESETN.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.ADDR_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.ARUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.AWUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.BUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.DATA_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BRESP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BURST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_CACHE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_LOCK">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_PROT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_QOS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_REGION">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_RRESP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_WSTRB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.ID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.MAX_BURST_LENGTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_READ_OUTSTANDING">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_READ_THREADS">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_OUTSTANDING">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_THREADS">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.PROTOCOL">AXI4LITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.RUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.SUPPORTS_NARROW_BURST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.WUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.WUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.CLK_DOMAIN"/>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SELECT_XPM">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SYNCHRONIZER_STAGE">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_UNDERFLOW_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_COMMON_OVERFLOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_COMMON_UNDERFLOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DEFAULT_SETTINGS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DOUT_RST">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_EMBEDDED_REG">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FIFO16_FLAGS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FWFT_DATA_COUNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_PIPELINE_REG">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_VALID_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WACH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WDCH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRCH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_ACK_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DATA_COUNT_WIDTH">12</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH">2048</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_AXIS">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_RACH">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_RDCH">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WACH">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WDCH">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WRCH">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_FREQ">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH">11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_AXIS">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_RACH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_RDCH">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WACH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WDCH">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WRCH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_RESPONSE_LATENCY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ADDRESS_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ARUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AWUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Add_NGC_Constraint_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Almost_Empty_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Almost_Full_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_SELECT_XPM">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Clock_Enable_Type">Slave_Interface_Clock_Enable</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Clock_Type_AXI">Common_Clock</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">Fifo32k</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DATA_WIDTH">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Data_Count">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Data_Count_Width">12</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Timing_Violations">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Timing_Violations_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Dout_Reset_Value">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_axis">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_rach">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_rdch">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wach">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wdch">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wrch">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Negate_Value">5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Common_Overflow">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Common_Underflow">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_Type">Hard_ECC</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Reset_Synchronization">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Safety_Circuit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_TLAST">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_TREADY">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_axis">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_rach">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_rdch">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wach">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wdch">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wrch">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_axis">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_rach">Common_Clock_Distributed_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_rdch">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wach">Common_Clock_Distributed_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wdch">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wrch">Common_Clock_Distributed_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Fifo_Implementation">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Flags_Reset_Value">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value">2047</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_axis">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_rach">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_rdch">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wach">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wdch">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wrch">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Negate_Value">2046</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_ACLKEN">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_TKEEP">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_TSTRB">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERFACE_TYPE">Native</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Data_Width">128</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth">2048</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_axis">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_rach">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_rdch">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wach">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wdch">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wrch">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Master_interface_Clock_enable_memory_mapped">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Data_Width">128</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Depth">2048</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Register_Type">Embedded_Reg</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Flag_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Sense_AXI">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROTOCOL">AXI4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Performance_Options">First_Word_Fall_Through</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_axis">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_rach">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_rdch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wach">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wdch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wrch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_axis">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_rach">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_rdch">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wach">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wdch">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wrch">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Clock_Frequency">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Data_Count">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Data_Count_Width">12</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_axis">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_rach">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_rdch">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wach">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wdch">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wrch">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Pin">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Type">Synchronous_Reset</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Slave_interface_Clock_enable_memory_mapped">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TDATA_NUM_BYTES">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TDEST_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TKEEP_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TSTRB_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TUSER_WIDTH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Flag_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Sense_AXI">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Dout_Reset">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Embedded_Registers">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Embedded_Registers_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Extra_Logic">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Valid_Flag">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Valid_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Acknowledge_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Acknowledge_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Clock_Frequency">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Data_Count">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Data_Count_Width">12</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.asymmetric_port_width">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axis_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.dynamic_power_saving">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ecc_pipeline_reg">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_low_latency">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_read_pointer_increment_by2">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.rach_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.rdch_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.synchronization_stages">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.synchronization_stages_axi">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_dout_register">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wach_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wdch_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wrch_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">kintexu</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART">xilinx.com:kcu105:part0:1.6</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xcku040</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffva1156</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VHDL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE">E</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2019.2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+      <spirit:vendorExtensions>
+        <xilinx:componentInstanceExtensions>
+          <xilinx:configElementInfos>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.ADDR_WIDTH" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.DATA_WIDTH" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BRESP" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BURST" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_CACHE" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_LOCK" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_PROT" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_QOS" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_REGION" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_RRESP" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_WSTRB" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.PROTOCOL" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TREADY" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.ADDR_WIDTH" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.DATA_WIDTH" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BRESP" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BURST" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_CACHE" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_LOCK" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_PROT" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_QOS" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_REGION" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_RRESP" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_WSTRB" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.PROTOCOL" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TREADY" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Data_Count" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Data_Count_Width" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_rach" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wach" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wrch" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Empty_Threshold_Negate_Value" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Enable_Safety_Circuit" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.FIFO_Implementation_axis" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.FIFO_Implementation_rach" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.FIFO_Implementation_rdch" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.FIFO_Implementation_wach" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.FIFO_Implementation_wdch" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.FIFO_Implementation_wrch" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Fifo_Implementation" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Full_Flags_Reset_Value" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_rach" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wach" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wrch" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Full_Threshold_Negate_Value" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.INTERFACE_TYPE" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Input_Data_Width" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Input_Depth" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Output_Data_Width" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Output_Depth" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Performance_Options" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Programmable_Full_Type" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Read_Data_Count_Width" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Reset_Type" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Use_Extra_Logic" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Valid_Flag" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Data_Count_Width" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.asymmetric_port_width" xilinx:valueSource="user"/>
+          </xilinx:configElementInfos>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/source/DuneNvme/src/ip/Fifo4k.xci b/source/DuneNvme/src/ip/Fifo4k.xci
new file mode 100644 (file)
index 0000000..0c95634
--- /dev/null
@@ -0,0 +1,573 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>Fifo4k</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="fifo_generator" spirit:version="13.2"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.ASSOCIATED_BUSIF"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.ASSOCIATED_RESET"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MASTER_ACLK.ASSOCIATED_RESET"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MASTER_ACLK.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MASTER_ACLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MASTER_ACLK.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MASTER_ACLK.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.ADDR_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.ARUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.AWUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.BUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.DATA_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BRESP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BURST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_CACHE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_LOCK">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_PROT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_QOS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_REGION">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_RRESP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_WSTRB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.ID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.MAX_BURST_LENGTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_READ_OUTSTANDING">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_READ_THREADS">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_WRITE_OUTSTANDING">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_WRITE_THREADS">1</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.PROTOCOL">AXI4LITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.RUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.SUPPORTS_NARROW_BURST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.WUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.WUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TKEEP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TLAST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TREADY">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TSTRB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.LAYERED_METADATA">undef</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.READ_CLK.ASSOCIATED_BUSIF"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.READ_CLK.ASSOCIATED_RESET"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.READ_CLK.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.READ_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.READ_CLK.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLAVE_ACLK.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLAVE_ACLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLAVE_ACLK.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLAVE_ACLK.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLAVE_ARESETN.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.ADDR_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.ARUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.AWUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.BUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.DATA_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BRESP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BURST">0</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_NEGATE_VAL">254</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RACH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RDCH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_DATA_COUNT_WIDTH">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_DEPTH">256</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_FREQ">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_PNTR_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SELECT_XPM">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SYNCHRONIZER_STAGE">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_UNDERFLOW_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_COMMON_OVERFLOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_COMMON_UNDERFLOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DEFAULT_SETTINGS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DOUT_RST">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_EMBEDDED_REG">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FIFO16_FLAGS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FWFT_DATA_COUNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_PIPELINE_REG">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_VALID_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WACH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WDCH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRCH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_ACK_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DATA_COUNT_WIDTH">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH">256</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_AXIS">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_RACH">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_RDCH">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WACH">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WDCH">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WRCH">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_FREQ">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_AXIS">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_RACH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_RDCH">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WACH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WDCH">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WRCH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_RESPONSE_LATENCY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ADDRESS_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ARUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AWUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Add_NGC_Constraint_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Almost_Empty_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Almost_Full_Flag">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_SELECT_XPM">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Clock_Enable_Type">Slave_Interface_Clock_Enable</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Clock_Type_AXI">Common_Clock</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">Fifo4k</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DATA_WIDTH">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Data_Count">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Data_Count_Width">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Timing_Violations">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Timing_Violations_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Dout_Reset_Value">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_axis">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_rach">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_rdch">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wach">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wdch">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wrch">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Negate_Value">5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Common_Overflow">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Common_Underflow">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_Type">Hard_ECC</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Reset_Synchronization">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Safety_Circuit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_TLAST">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_TREADY">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_axis">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_rach">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_rdch">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wach">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wdch">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wrch">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_axis">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_rach">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_rdch">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wach">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wdch">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wrch">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Fifo_Implementation">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Flags_Reset_Value">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value">255</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_axis">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_rach">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_rdch">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wach">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wdch">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wrch">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Negate_Value">254</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_ACLKEN">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_TKEEP">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_TSTRB">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERFACE_TYPE">Native</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Data_Width">128</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth">256</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_axis">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_rach">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_rdch">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wach">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wdch">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wrch">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Master_interface_Clock_enable_memory_mapped">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Data_Width">128</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Depth">256</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Register_Type">Embedded_Reg</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Flag_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Sense_AXI">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROTOCOL">AXI4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Performance_Options">First_Word_Fall_Through</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_axis">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_rach">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_rdch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wach">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wdch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wrch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_axis">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_rach">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_rdch">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wach">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wdch">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wrch">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Clock_Frequency">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Data_Count">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Data_Count_Width">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_axis">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_rach">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_rdch">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wach">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wdch">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wrch">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Pin">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Type">Synchronous_Reset</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Slave_interface_Clock_enable_memory_mapped">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TDATA_NUM_BYTES">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TDEST_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TKEEP_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TSTRB_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TUSER_WIDTH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Flag_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Sense_AXI">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Dout_Reset">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Embedded_Registers">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Embedded_Registers_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Extra_Logic">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Valid_Flag">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Valid_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Acknowledge_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Acknowledge_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Clock_Frequency">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Data_Count">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Data_Count_Width">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.asymmetric_port_width">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axis_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.dynamic_power_saving">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ecc_pipeline_reg">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_low_latency">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_read_pointer_increment_by2">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.rach_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.rdch_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.synchronization_stages">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.synchronization_stages_axi">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_dout_register">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wach_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wdch_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wrch_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">kintexu</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART">xilinx.com:kcu105:part0:1.6</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xcku040</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffva1156</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VHDL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE">E</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2019.2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+      <spirit:vendorExtensions>
+        <xilinx:componentInstanceExtensions>
+          <xilinx:configElementInfos>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.ADDR_WIDTH" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.DATA_WIDTH" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BRESP" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BURST" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_CACHE" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_LOCK" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_PROT" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_QOS" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_REGION" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_RRESP" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_WSTRB" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.PROTOCOL" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TREADY" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.ADDR_WIDTH" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.DATA_WIDTH" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BRESP" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BURST" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_CACHE" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_LOCK" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_PROT" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_QOS" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_REGION" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_RRESP" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_WSTRB" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.PROTOCOL" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TREADY" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Almost_Full_Flag" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Data_Count" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Data_Count_Width" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Empty_Threshold_Negate_Value" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Fifo_Implementation" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Full_Threshold_Negate_Value" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Input_Data_Width" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Input_Depth" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Output_Data_Width" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Output_Depth" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Performance_Options" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Read_Data_Count_Width" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Use_Extra_Logic" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Valid_Flag" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Data_Count_Width" xilinx:valueSource="user"/>
+          </xilinx:configElementInfos>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
index 07605ee1ad0dd211f315f0da291cad8cac95f08c..383a44ebe53b93724aa66e0814f423e2b06fe042 100644 (file)
@@ -199,21 +199,26 @@ void NvmeAccess::reset(){
        }
        te = getTime();
        printf("Reset time was: %f ms\n", (te - ts) * 1000);
-
-       printf("Last status was: %8.8x\n", data);
-       data = 0;
-       while((data & 4) == 0){
-               readNvmeStorageReg(8, data);
-               usleep(1000);
-       }
-       te = getTime();
-       printf("Full Reset time was: %f ms\n", (te - ts) * 1000);
-               
        usleep(100000);
+
        printf("Last status was: %8.8x\n", data);
+       
+       if(UseConfigEngine){
+               data = 0;
+               while((data & 4) == 0){
+                       readNvmeStorageReg(8, data);
+                       usleep(1000);
+               }
+               te = getTime();
+               printf("Full Reset time was: %f ms\n", (te - ts) * 1000);
 
-       data = 0x06;
-       pcieWrite(10, 4, 1, &data);                     ///< Set PCIe config command for memory accesses
+               usleep(100000);
+               printf("Last status was: %8.8x\n", data);
+       }
+       else {
+               data = 0x06;
+               pcieWrite(10, 4, 1, &data);                     ///< Set PCIe config command for memory accesses
+       }
 }
 #endif
 
@@ -240,8 +245,8 @@ int NvmeAccess::nvmeRequest(int queue, int opcode, BUInt32 address, BUInt32 arg1
        printf("nvmeRequest:\n"); bhd32(cmd, 16);
        if(UseQueueEngine){
                // Send message to queue engine
-               printf("Write to queue: %8.8x\n", 0x05000000 | (queue << 16));
-               if(e = pcieWrite(1, 0x05000000 | (queue << 16), 16, cmd))
+               printf("Write to queue: %8.8x\n", 0x02000000 | (queue << 16));
+               if(e = pcieWrite(1, 0x02000000 | (queue << 16), 16, cmd))
                        return e;
        }
        else {
@@ -301,24 +306,9 @@ int NvmeAccess::nvmeProcess(){
 
                dl3printf("NvmeAccess::nvmeProcess: awoken with: %d bytes\n", nt);
                //dl3hd32(obufRx, nt / 4);
+               printf("NvmeAccess::nvmeProcess: awoken with: %d bytes\n", nt);
+               bhd32(obufRx, nt / 4);
 
-#ifdef ZAP             
-               // Determine if packet is a reply or an Nvme request from the source number in the header
-               if(obufRx[0] == 1){
-                       memcpy(&opacketReply, obufRx, sizeof(opacketReply));
-                       dl3printf("NvmeAccess::nvmeProcess: Reply id: %x\n", opacketReply.requesterId);
-                       dl3hd32(&opacketReply, nt / 4);
-                       opacketReplySem.set();
-                       continue;
-               }
-               else if(obufRx[0] == 2){
-                       memcpy(&request, obufRx, sizeof(request));
-               }
-               else {
-                       printf("NvmeAccess::nvmeProcess: Error packet with unknown stream\n");
-                       continue;
-               }
-#else
                // Determine if packet is a reply or an Nvme request from the reply bit in the header
                if(obufRx[2] & 0x80000000){
                        memcpy(&opacketReply, obufRx, sizeof(opacketReply));
@@ -330,7 +320,6 @@ int NvmeAccess::nvmeProcess(){
                else {
                        memcpy(&request, obufRx, sizeof(request));
                }
-#endif
                
                dl3printf("NvmeAccess::nvmeProcess: recvNum: %d Req: %d nWords: %d address: 0x%8.8x\n", nt, request.request, request.numWords, request.address);
                dl3hd32(&request, nt / 4);
@@ -356,10 +345,11 @@ int NvmeAccess::nvmeProcess(){
                        nWordsRet = request.numWords;
                        while(nWordsRet){
                                nWords = nWordsRet;
-                               if(nWords > 32)
-                                       nWords = 32;
+                               if(nWords > PcieMaxPayloadSize)
+                                       nWords = PcieMaxPayloadSize;
 
                                reply.reply = 1;
+                               reply.address = request.address & 0x0FFF;
                                reply.numBytes = (nWordsRet * 4);
                                reply.numWords = nWords;
                                reply.tag = request.tag;
@@ -373,6 +363,7 @@ int NvmeAccess::nvmeProcess(){
                                }
                                        
                                nWordsRet -= nWords;
+                               request.address += (4 * nWords);
                        }
                }
                else if(request.request == 1){
@@ -416,8 +407,9 @@ int NvmeAccess::nvmeProcess(){
                                        return 1;
                                }
                        }
-                       else if((request.address & 0x00FF0000) == 0x00800000){
-                               dl3printf("NvmeAccess::nvmeProcess: IoBlockWrite: address: %8.8x nWords: %d\n", (request.address & 0x0FFFFFFF), nWords);
+                       else if((request.address & 0x00FF0000) == 0x000800000){
+                               dl3printf("NvmeAccess::nvmeProcess: IoBlockWrite: address: %8.8x nWords: %d\n", (request.address & 0x0FFFFFFF), request.numWords);
+                               printf("NvmeAccess::nvmeProcess: IoBlockWrite: address: %8.8x nWords: %d\n", (request.address & 0x0FFFFFFF), request.numWords);
 
                                memcpy(&odataBlockMem[(request.address & 0x0000FFFF) / 4], request.data, request.numWords * 4);
                        }
@@ -608,14 +600,15 @@ int NvmeAccess::packetSend(const NvmeReplyPacket& packet){
 
 
 void NvmeAccess::dumpRegs(){
-       printf("Id   : %8.8x\n", oregs[0]);
-       //printf("Address1: %8.8x\n", oregs[1]);
-       //printf("Address2: %8.8x\n", oregs[2]);
-       printf("Test0: %8.8x\n", oregs[3]);
-       printf("Test1: %8.8x\n", oregs[4]);
-       printf("Test2: %8.8x\n", oregs[5]);
-       printf("Test3: %8.8x\n", oregs[6]);
-       printf("Test4: %8.8x\n", oregs[7]);
+       int     r;
+       
+       printf("Id:       %8.8x\n", oregs[0]);
+       printf("Control:  %8.8x\n", oregs[1]);
+       printf("Status:   %8.8x\n", oregs[2]);
+       
+       for(r = 3; r < 16; r++){
+               printf("Reg%2.2d:    %8.8x\n", r, oregs[r]);
+       }
 }
 
 void  NvmeAccess::dumpDmaRegs(bool c2h, int chan){
index d2ac978c915d3b6562530d409dc065b43d68354c..313b99e00ca6e1b4405609cc6d6a46a6b7abd332 100644 (file)
@@ -58,6 +58,8 @@
 #include <bfpga_driver/bfpga.h>
 
 const Bool     UseQueueEngine = 1;             ///< Use the FPGA queue engine implementation
+const Bool     UseConfigEngine = 0;            ///< Use the FPGA configuration engine
+const BUInt    PcieMaxPayloadSize = 32;        ///< The Pcie maximim packet payload in 32bit DWords
 
 class NvmeRequestPacket {
 public:
@@ -78,7 +80,7 @@ public:
        BUInt32         completerId:16;         ///< The completers ID
        BUInt32         requesterIdEnable:1;    ///< Enable the manual use of the requestorId field.
        BUInt32         fill3:7;                ///< 
-       BUInt32         data[32];               ///< The data words (Max of 128 bytes but can be increased)
+       BUInt32         data[PcieMaxPayloadSize];       ///< The data words (Max of 1024 bytes but can be increased)
 };
 
 class NvmeReplyPacket {
@@ -102,7 +104,7 @@ public:
        BUInt32         tag:8;                  ///< The requests tag
        BUInt32         fill3:23;               ///< 
        BUInt32         reply:1;                ///< This bit indicates a reply (we have used an unused bit for this)
-       BUInt32         data[32];               ///< The data words (Max of 128 bytes but can be increased)
+       BUInt32         data[PcieMaxPayloadSize];       ///< The data words (Max of 1024 bytes but can be increased)
 };
 
 /// Nvme access class
diff --git a/source/DuneNvme/test/pciregs.txt b/source/DuneNvme/test/pciregs.txt
new file mode 100644 (file)
index 0000000..05203db
--- /dev/null
@@ -0,0 +1,207 @@
+WesternDigital
+02:00.0 Non-Volatile memory controller: Sandisk Corp Device 5006 (prog-if 02 [NVM Express])
+        Subsystem: Sandisk Corp Device 5006
+        Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+
+        Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
+        Latency: 0, Cache Line Size: 64 bytes
+        Interrupt: pin A routed to IRQ 16
+        NUMA node: 0
+        Region 0: Memory at a1200000 (64-bit, non-prefetchable) [size=16K]
+        Region 4: Memory at a1204000 (64-bit, non-prefetchable) [size=256]
+        Capabilities: [80] Power Management version 3
+                Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-)
+                Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME-
+        Capabilities: [90] MSI: Enable- Count=1/32 Maskable- 64bit+
+                Address: 0000000000000000  Data: 0000
+        Capabilities: [b0] MSI-X: Enable+ Count=65 Masked-
+                Vector table: BAR=0 offset=00002000
+                PBA: BAR=4 offset=00000000
+        Capabilities: [c0] Express (v2) Endpoint, MSI 00
+                DevCap: MaxPayload 512 bytes, PhantFunc 0, Latency L0s <1us, L1 unlimited
+                        ExtTag- AttnBtn- AttnInd- PwrInd- RBE+ FLReset+ SlotPowerLimit 0.000W
+                DevCtl: CorrErr+ NonFatalErr+ FatalErr+ UnsupReq+
+                        RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+ FLReset-
+                        MaxPayload 256 bytes, MaxReadReq 512 bytes
+                DevSta: CorrErr- NonFatalErr- FatalErr- UnsupReq- AuxPwr- TransPend-
+                LnkCap: Port #0, Speed 8GT/s, Width x4, ASPM L1, Exit Latency L1 <8us
+                        ClockPM+ Surprise- LLActRep- BwNot- ASPMOptComp+
+                LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- CommClk+
+                        ExtSynch- ClockPM+ AutWidDis- BWInt- AutBWInt-
+                LnkSta: Speed 8GT/s (ok), Width x4 (ok)
+                        TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt-
+                DevCap2: Completion Timeout: Range B, TimeoutDis+, NROPrPrP-, LTR+
+                         10BitTagComp-, 10BitTagReq-, OBFF Not Supported, ExtFmt+, EETLPPrefix-
+                         EmergencyPowerReduction Not Supported, EmergencyPowerReductionInit-
+                         FRS-, TPHComp-, ExtTPHComp-
+                         AtomicOpsCap: 32bit- 64bit- 128bitCAS-
+                DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR+, OBFF Disabled
+                         AtomicOpsCtl: ReqEn-
+                LnkCtl2: Target Link Speed: 8GT/s, EnterCompliance- SpeedDis-
+                         Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS-
+                         Compliance De-emphasis: -6dB
+                LnkSta2: Current De-emphasis Level: -6dB, EqualizationComplete+, EqualizationPhase1+
+                         EqualizationPhase2+, EqualizationPhase3+, LinkEqualizationRequest-
+        Capabilities: [100 v2] Advanced Error Reporting
+                UESta:  DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
+                UEMsk:  DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
+                UESvrt: DLP+ SDES+ TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol-
+                CESta:  RxErr- BadTLP- BadDLLP- Rollover- Timeout- AdvNonFatalErr-
+                CEMsk:  RxErr- BadTLP- BadDLLP- Rollover- Timeout- AdvNonFatalErr+
+                AERCap: First Error Pointer: 00, ECRCGenCap+ ECRCGenEn- ECRCChkCap+ ECRCChkEn-
+                        MultHdrRecCap- MultHdrRecEn- TLPPfxPres- HdrLogCap-
+                HeaderLog: 00000000 00000000 00000000 00000000
+        Capabilities: [150 v1] Device Serial Number 00-00-00-00-00-00-00-00
+        Capabilities: [1b8 v1] Latency Tolerance Reporting
+                Max snoop latency: 3145728ns
+                Max no snoop latency: 3145728ns
+        Capabilities: [300 v1] Secondary PCI Express
+                LnkCtl3: LnkEquIntrruptEn-, PerformEqu-
+                LaneErrStat: 0
+        Capabilities: [900 v1] L1 PM Substates
+                L1SubCap: PCI-PM_L1.2+ PCI-PM_L1.1- ASPM_L1.2+ ASPM_L1.1- L1_PM_Substates+
+                          PortCommonModeRestoreTime=32us PortTPowerOnTime=10us
+                L1SubCtl1: PCI-PM_L1.2- PCI-PM_L1.1- ASPM_L1.2- ASPM_L1.1-
+                           T_CommonMode=0us LTR1.2_Threshold=81920ns
+                L1SubCtl2: T_PwrOn=10us
+        Kernel driver in use: nvme
+        Kernel modules: nvme
+
+In Pc
+04:00.0 Non-Volatile memory controller: Sandisk Corp Device 5009 (rev 01) (prog-if 02 [NVM Express])
+        Subsystem: Sandisk Corp Device 5009
+        Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+
+        Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
+        Latency: 0, Cache Line Size: 64 bytes
+        Interrupt: pin A routed to IRQ 16
+        NUMA node: 0
+        Region 0: Memory at a1100000 (64-bit, non-prefetchable) [size=16K]
+        Region 4: Memory at a1104000 (64-bit, non-prefetchable) [size=256]
+        Capabilities: [80] Power Management version 3
+                Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-)
+                Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME-
+        Capabilities: [90] MSI: Enable- Count=1/32 Maskable- 64bit+
+                Address: 0000000000000000  Data: 0000
+        Capabilities: [b0] MSI-X: Enable+ Count=17 Masked-
+                Vector table: BAR=0 offset=00002000
+                PBA: BAR=4 offset=00000000
+        Capabilities: [c0] Express (v2) Endpoint, MSI 00
+                DevCap: MaxPayload 512 bytes, PhantFunc 0, Latency L0s <1us, L1 unlimited
+                        ExtTag- AttnBtn- AttnInd- PwrInd- RBE+ FLReset+ SlotPowerLimit 0.000W
+                DevCtl: CorrErr+ NonFatalErr+ FatalErr+ UnsupReq+
+                        RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+ FLReset-
+                        MaxPayload 256 bytes, MaxReadReq 512 bytes
+                DevSta: CorrErr- NonFatalErr- FatalErr- UnsupReq- AuxPwr- TransPend-
+                LnkCap: Port #0, Speed 8GT/s, Width x4, ASPM L1, Exit Latency L1 <8us
+                        ClockPM+ Surprise- LLActRep- BwNot- ASPMOptComp+
+                LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- CommClk+
+                        ExtSynch- ClockPM+ AutWidDis- BWInt- AutBWInt-
+                LnkSta: Speed 8GT/s (ok), Width x4 (ok)
+                        TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt-
+                DevCap2: Completion Timeout: Range B, TimeoutDis+, NROPrPrP-, LTR+
+                         10BitTagComp-, 10BitTagReq-, OBFF Not Supported, ExtFmt+, EETLPPrefix-
+                         EmergencyPowerReduction Not Supported, EmergencyPowerReductionInit-
+                         FRS-, TPHComp-, ExtTPHComp-
+                         AtomicOpsCap: 32bit- 64bit- 128bitCAS-
+                DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR+, OBFF Disabled
+                         AtomicOpsCtl: ReqEn-
+                LnkCtl2: Target Link Speed: 8GT/s, EnterCompliance- SpeedDis-
+                         Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS-
+                         Compliance De-emphasis: -6dB
+                LnkSta2: Current De-emphasis Level: -6dB, EqualizationComplete+, EqualizationPhase1+
+                         EqualizationPhase2+, EqualizationPhase3+, LinkEqualizationRequest-
+        Capabilities: [100 v2] Advanced Error Reporting
+                UESta:  DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
+                UEMsk:  DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
+                UESvrt: DLP+ SDES+ TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol-
+                CESta:  RxErr- BadTLP- BadDLLP- Rollover- Timeout- AdvNonFatalErr-
+                CEMsk:  RxErr- BadTLP- BadDLLP- Rollover- Timeout- AdvNonFatalErr+
+                AERCap: First Error Pointer: 00, ECRCGenCap+ ECRCGenEn- ECRCChkCap+ ECRCChkEn-
+                        MultHdrRecCap- MultHdrRecEn- TLPPfxPres- HdrLogCap-
+                HeaderLog: 00000000 00000000 00000000 00000000
+        Capabilities: [150 v1] Device Serial Number 00-00-00-00-00-00-00-00
+        Capabilities: [1b8 v1] Latency Tolerance Reporting
+                Max snoop latency: 3145728ns
+                Max no snoop latency: 3145728ns
+        Capabilities: [300 v1] Secondary PCI Express
+                LnkCtl3: LnkEquIntrruptEn-, PerformEqu-
+                LaneErrStat: 0
+        Capabilities: [900 v1] L1 PM Substates
+                L1SubCap: PCI-PM_L1.2+ PCI-PM_L1.1- ASPM_L1.2+ ASPM_L1.1- L1_PM_Substates+
+                          PortCommonModeRestoreTime=32us PortTPowerOnTime=10us
+                L1SubCtl1: PCI-PM_L1.2- PCI-PM_L1.1- ASPM_L1.2- ASPM_L1.1-
+                           T_CommonMode=0us LTR1.2_Threshold=81920ns
+                L1SubCtl2: T_PwrOn=10us
+        Kernel driver in use: nvme
+        Kernel modules: nvme
+
+Seagate
+02:00.0 Non-Volatile memory controller: Seagate Technology PLC Device 5016 (rev 01) (prog-if 02 [NVM Express])
+        Subsystem: Seagate Technology PLC Device 5016
+        Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+
+        Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
+        Latency: 0, Cache Line Size: 64 bytes
+        Interrupt: pin A routed to IRQ 16
+        NUMA node: 0
+        Region 0: Memory at a1200000 (64-bit, non-prefetchable) [size=16K]
+        Capabilities: [80] Express (v2) Endpoint, MSI 00
+                DevCap: MaxPayload 256 bytes, PhantFunc 0, Latency L0s unlimited, L1 unlimited
+                        ExtTag+ AttnBtn- AttnInd- PwrInd- RBE+ FLReset+ SlotPowerLimit 25.000W
+                DevCtl: CorrErr+ NonFatalErr+ FatalErr+ UnsupReq+
+                        RlxdOrd+ ExtTag+ PhantFunc- AuxPwr- NoSnoop+ FLReset-
+                        MaxPayload 256 bytes, MaxReadReq 512 bytes
+                DevSta: CorrErr- NonFatalErr- FatalErr- UnsupReq- AuxPwr- TransPend-
+                LnkCap: Port #1, Speed 16GT/s, Width x4, ASPM L1, Exit Latency L1 unlimited
+                        ClockPM- Surprise- LLActRep- BwNot- ASPMOptComp+
+                LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- CommClk+
+                        ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
+                LnkSta: Speed 8GT/s (downgraded), Width x4 (ok)
+                        TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt-
+                DevCap2: Completion Timeout: Range ABCD, TimeoutDis+, NROPrPrP-, LTR+
+                         10BitTagComp+, 10BitTagReq-, OBFF Not Supported, ExtFmt+, EETLPPrefix-
+                         EmergencyPowerReduction Not Supported, EmergencyPowerReductionInit-
+                         FRS-, TPHComp-, ExtTPHComp-
+                         AtomicOpsCap: 32bit- 64bit- 128bitCAS-
+                DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR+, OBFF Disabled
+                         AtomicOpsCtl: ReqEn-
+                LnkCtl2: Target Link Speed: 16GT/s, EnterCompliance- SpeedDis-
+                         Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS-
+                         Compliance De-emphasis: -6dB