Second part of improved register access with system to support Wishbone bus better.
authorTerry Barnaby <terry.barnaby@beam.beam.ltd.uk>
Fri, 7 Aug 2020 05:50:42 +0000 (06:50 +0100)
committerTerry Barnaby <terry.barnaby@beam.beam.ltd.uk>
Fri, 7 Aug 2020 05:50:42 +0000 (06:50 +0100)
commita2a4d88c26e61c7cf071ab902c4f2a1b13edd6f0
treee459a49f76f4872e93ec4d04715f623860efebd0
parent568084ce18c3f34afbfa70d188e3caf247687e48
Second part of improved register access with system to support Wishbone bus better.
sim/testbench/test020-write.vhd
src/NvmeStorage.vhd
src/RegAccessClockConvertor.vhd