Register access: Added delay on read to handle clock domain crossing latency.
authorTerry Barnaby <terry.barnaby@beam.beam.ltd.uk>
Tue, 19 May 2020 08:28:29 +0000 (09:28 +0100)
committerTerry Barnaby <terry.barnaby@beam.beam.ltd.uk>
Tue, 19 May 2020 08:28:29 +0000 (09:28 +0100)
commit40f5c4859dcd88d5034a9ac5d6e13a0dbdac1ab1
tree761102be1cb4fc22eb0a86049f523e84cce6f225
parentc31f056f8d0ec8417a46747899ab28fdc226bc92
Register access: Added delay on read to handle clock domain crossing latency.
Some tidy ups.
sim/Makefile
sim/testbench/test020-write.vhd
src/NvmeStorage.vhd
src/NvmeStorageUnit.vhd