/******************************************************************************* * This file is owned and controlled by Xilinx and must be used * * solely for design, simulation, implementation and creation of * * design files limited to Xilinx devices or technologies. Use * * with non-Xilinx devices or technologies is expressly prohibited * * and immediately terminates your license. * * * * XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" * * SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR * * XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION * * AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION * * OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS * * IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, * * AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE * * FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY * * WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * * IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * * REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * * INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS * * FOR A PARTICULAR PURPOSE. * * * * Xilinx products are not intended for use in life support * * appliances, devices, or systems. Use in such applications are * * expressly prohibited. * * * * (c) Copyright 1995-2005 Xilinx, Inc. * * All rights reserved. * *******************************************************************************/ // The synopsys directives "translate_off/translate_on" specified below are // supported by XST, FPGA Compiler II, Mentor Graphics and Synplicity synthesis // tools. Ensure they are correct for your synthesis tool(s). // You must compile the wrapper file spram8192x32.v when simulating // the core, spram8192x32. When compiling the wrapper file, be sure to // reference the XilinxCoreLib Verilog simulation library. For detailed // instructions, please refer to the "CORE Generator Help". `timescale 1ns/1ps module spram8192x32( addr, clk, din, dout, we); input [12 : 0] addr; input clk; input [31 : 0] din; output [31 : 0] dout; input we; // synopsys translate_off BLKMEMSP_V6_2 #( 13, // c_addr_width "0", // c_default_data 8192, // c_depth 0, // c_enable_rlocs 1, // c_has_default_data 1, // c_has_din 0, // c_has_en 0, // c_has_limit_data_pitch 0, // c_has_nd 0, // c_has_rdy 0, // c_has_rfd 0, // c_has_sinit 1, // c_has_we 18, // c_limit_data_pitch "mif_file_16_1", // c_mem_init_file 0, // c_pipe_stages 0, // c_reg_inputs "0", // c_sinit_value 32, // c_width 2, // c_write_mode "0", // c_ybottom_addr 1, // c_yclk_is_rising 1, // c_yen_is_high "hierarchy1", // c_yhierarchy 0, // c_ymake_bmm "16kx1", // c_yprimitive_type 1, // c_ysinit_is_high "1024", // c_ytop_addr 0, // c_yuse_single_primitive 1, // c_ywe_is_high 1) // c_yydisable_warnings inst ( .ADDR(addr), .CLK(clk), .DIN(din), .DOUT(dout), .WE(we), .EN(), .ND(), .RFD(), .RDY(), .SINIT()); // synopsys translate_on // FPGA Express black box declaration // synopsys attribute fpga_dont_touch "true" // synthesis attribute fpga_dont_touch of spram8192x32 is "true" // XST black box declaration // box_type "black_box" // synthesis attribute box_type of spram8192x32 is "black_box" endmodule