The following files were generated for 'phasetable' in directory 
C:\DESIGNS\FPGA\Custom_Libera:

phasetable.asy:
   Graphical symbol information file. Used by the ISE tools and some
   third party tools to create a symbol representing the core.

phasetable.edn:
   Electronic Data Netlist (EDN) file containing the information
   required to implement the module in a Xilinx (R) FPGA.

phasetable.sym:
   Please see the core data sheet.

phasetable.v:
   Verilog wrapper file provided to support functional simulation.
   This file contains simulation model customization data that is
   passed to a parameterized simulation model for the core.

phasetable.veo:
   VEO template file containing code that can be used as a model for
   instantiating a CORE Generator module in a Verilog design.

phasetable.vhd:
   VHDL wrapper file provided to support functional simulation. This
   file contains simulation model customization data that is passed to
   a parameterized simulation model for the core.

phasetable.vho:
   VHO template file containing code that can be used as a model for
   instantiating a CORE Generator module in a VHDL design.

phasetable.xco:
   CORE Generator input file containing the parameters used to
   regenerate a core.

phasetable_flist.txt:
   Text file listing all of the output files produced when a customized
   core was generated in the CORE Generator.

phasetable_readme.txt:
   Text file indicating the files generated and how they are used.


Please see the Xilinx CORE Generator online help for further details on
generated files and how to use them.