----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    12:41:34 10/09/2006 
-- Design Name: 
-- Module Name:    chipscope_analyser - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity chipscope_analyser is
    Port ( data_ch0 	: in  STD_LOGIC_VECTOR (95 downto 0);
           data_ch1 	: in  STD_LOGIC_VECTOR (47 downto 0);
           clk 		: in  STD_LOGIC;
			  reset 		: in std_logic;
			  clk_ext 	: in std_logic;
           trig_ch0 	: in  STD_LOGIC_VECTOR (3 downto 0);
           trig_ch1 	: in  STD_LOGIC_VECTOR (3 downto 0);
			  control_port_i 	: in  STD_LOGIC_VECTOR (31 downto 0);
			  async_port_i  	: in  STD_LOGIC_VECTOR (31 downto 0);
			  control_port_o 	: out  STD_LOGIC_VECTOR (7 downto 0);
           data_alt_ch0 	: in  STD_LOGIC_VECTOR (95 downto 0);
           data_alt_ch1 	: in  STD_LOGIC_VECTOR (47 downto 0));
end chipscope_analyser;

architecture Behavioral of chipscope_analyser is



  -------------------------------------------------------------------
  --
  --  ILA core signal declarations
  --
  -------------------------------------------------------------------
	signal 	control0       	: std_logic_vector(35 downto 0);
	signal 	control1       	: std_logic_vector(35 downto 0);
	signal 	control2       	: std_logic_vector(35 downto 0);
	signal 	control3       	: std_logic_vector(35 downto 0);
	signal 	data_2ch      		: std_logic_vector(47 downto 0);
	signal 	data_6ch 	  		: std_logic_vector(95 downto 0);
	signal 	timer,trig_timer	: std_logic_vector(23 downto 0);
	signal 	analyser_control,control_port		: std_logic_vector(31 downto 0); 
	signal 	clk2,clk2_sel,clk2_tmp,
				clk_en,
				ch_1_sel,
				ch_0_sel,
				ch0_trig_sel,
				trig_ch0_sel,
				trig_ch0_delayed,
				trig_timer_en		: std_logic;
	signal	trig_del1,trig_del2,trig_del3	: std_logic_vector(3 downto 0); 
	signal	stop_trig	: std_logic_vector(4 downto 0); 

	
 -------------------------------------------------------------------
  --
  --  ILA core component declaration
  --
  -------------------------------------------------------------------
  component ila_2CH
    port
    (
      control     : in    std_logic_vector(35 downto 0);
      clk         : in    std_logic;
      data       : in    std_logic_vector(47 downto 0);
      trig0       : in    std_logic_vector(3 downto 0)
    );
  end component;
  
    -------------------------------------------------------------------
  --
  --  ILA core component declaration
  --
  -------------------------------------------------------------------
 component ila_6CH
    port
    (
      control     : in    std_logic_vector(35 downto 0);
      clk         : in    std_logic;
      data        : in    std_logic_vector(95 downto 0);
      trig0       : in    std_logic_vector(3 downto 0)
    );
  end component;
  
   
   -------------------------------------------------------------------
  --
  --  ICON core component declaration
  --
  -------------------------------------------------------------------
  component icon
    port
    (
      control0    :   out std_logic_vector(35 downto 0);
      control1    :   out std_logic_vector(35 downto 0);
      control2    :   out std_logic_vector(35 downto 0);
      control3    :   out std_logic_vector(35 downto 0)
    );
  end component;
   
     -------------------------------------------------------------------
  --
  --  VIO core component declaration
  --
  -------------------------------------------------------------------
  component vio
    port
    (
      control     : in    std_logic_vector(35 downto 0);
      async_in    : in    std_logic_vector(31 downto 0);
      async_out   :   out std_logic_vector(31 downto 0)
    );
  end component;
  
  -------------------------------------------------------------------
  --
  --  VIO core component declaration
  --
  -------------------------------------------------------------------
  component vio_control
    port 
    (
      control     : in    std_logic_vector(35 downto 0);
      async_in    : in    std_logic_vector(31 downto 0);
      async_out   :   out std_logic_vector(31 downto 0)
    );
  end component;

begin
--**************************************************************************************************************    
--****************************   	   	CHIPSCOPE			      **********************************************    
--**************************************************************************************************************     


control_port_o <= control_port(31 downto 24);

-------------------------------------------------------------------
  --
  --  ICON core instance
  --
  -------------------------------------------------------------------
  i_icon : icon
    port map
    (
      control0    => control0,
      control1    => control1,
      control2    => control2,
      control3    => control3
    );	      
	
  -------------------------------------------------------------------
  --
  --  VIO core instance
  --
  -------------------------------------------------------------------
  i_vio_control : vio_control
    port map
    (
      control   => control0,
      async_in  => control_port_i,
      async_out => control_port
    );
	      

    
    
  -------------------------------------------------------------------
  --
  --  VIO core instance
  --
  -------------------------------------------------------------------
  i_vio : vio
    port map
    ( 
      control   => control1,
      async_in  => async_port_i,
      async_out => analyser_control
    );
	 
		ch_1_sel 		<= analyser_control(24);
		ch_0_sel 		<= analyser_control(25);
		clk2_sel 		<= analyser_control(26);
		ch0_trig_sel 	<= analyser_control(27);
	
  -------------------------------------------------------------------
  --
  --  ILA core instance
  --
  -------------------------------------------------------------------
	 
 i_ila_6CH : ila_6CH
    port map
    (
      control   => control2,
      clk       => clk,
      data      => data_6ch,
      trig0(3)     => trig_ch0_sel,
		trig0(2 downto 0) =>trig_ch0(2 downto 0)
    );
	 
	 data_6ch <= data_ch0 when ch_0_sel = '0' else data_alt_ch0;
	
	  -------------------------------------------------------------------
  --
  --  ILA core instance
  --
  -------------------------------------------------------------------
  i_ila_2CH : ila_2CH
    port map
    (
      control   => control3,
      clk       => clk2,   --clk2
      data      => data_2ch,
      trig0     => trig_del3
    );
	

 data_2ch <= data_ch1 when ch_1_sel = '0' else data_alt_ch1;

------------------------------------------------------------------------------------------------------	
	--trigger DELAY UNIT
------------------------------------------------------------------------------------------------------
	

process(clk,reset,trig_timer)
begin
	if clk'event and clk ='0' then
		if reset='1'  then
			trig_timer <=x"000002";
		elsif trig_ch0(3) = '1' then
		   trig_timer <=control_port(23 downto 0);
			trig_ch0_delayed<='0';
			trig_timer_en  <= '1';
		elsif trig_timer_en ='1' then
		   trig_timer <=trig_timer-'1';
		end if;
		
		if trig_timer = "000000" then  
			trig_ch0_delayed<='1';
		else 	
			trig_ch0_delayed<='0';
		end if;
		
		if trig_ch0_delayed = '1' then
			trig_timer_en  <= '0';
		end if;	
	end if;
end process;

	trig_ch0_sel <= trig_ch0(3) when ch0_trig_sel = '0' else trig_ch0_delayed;
	
	------------------------------------------------------------------------------------------------------	
	--trigger synchroniser
	------------------------------------------------------------------------------------------------------
	
process (clk)
 begin
 if rising_edge(clk) then
 --generation of delayed triggers
	trig_del1 <= trig_ch1;
	trig_del2 <= trig_del1;
	--detection of the rising edges
	if trig_del1(0) = '1' and trig_del2(0) = '0' then
		trig_del3(0) <= '1';
		stop_trig(0) <= '1';
	end if;
	--generation of trigger for 4 channels
	if trig_del1(1) = '1' and trig_del2(1) = '0' then
		trig_del3(1) <= '1';
		stop_trig(0) <= '1';
	end if;
	
	if trig_del1(2) = '1' and trig_del2(2) = '0' then
		trig_del3(2) <= '1';
		stop_trig(0) <= '1';
	end if;
	
	if trig_del1(3) = '1' and trig_del2(3) = '0' then
		trig_del3(3) <= '1';
		stop_trig(0) <= '1';
	end if;
	-- generation of long trig signal
	if clk2 = '1' then
		stop_trig(1) <= stop_trig(0);
		stop_trig(2) <= stop_trig(1);
		stop_trig(3) <= stop_trig(2);
		stop_trig(4) <= stop_trig(3);
	end if;
	
		if stop_trig(4) = '1' then
		trig_del3 <= "0000";
		stop_trig <= "00000"; 
	end if;
	
 end if;
 end process;
 	

	------------------------------------------------------------------------------------------------------	
	--CLK2 generator
	------------------------------------------------------------------------------------------------------
	process(clk,reset,timer)
begin
	if reset='1' then
		timer<=x"000100";
		
	elsif clk'event and clk ='0' then
		if clk_en = '1' then
		   timer <=analyser_control(23 downto 0);
		else
		   timer <=timer-'1';
		end if;
	end if;
	if timer = "000000" then  
		clk_en<='1';
	else
		clk_en<='0';
	end if;
	end process;
	
	--clk2 synchronisation
	process(clk)
begin
	if clk'event and clk ='0' then
		clk2<= clk2_tmp;
	end if;
	end process;
	
	clk2_tmp <= clk_en when clk2_sel = '0' else clk_ext;







end Behavioral;