---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 10:36:10 09/05/2006 -- Design Name: -- Module Name: Custom_libera_top - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; Library UNISIM; use UNISIM.vcomponents.all; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity Custom_libera_top is Port ( ADC_CLK_A_i : in STD_LOGIC; ADC_CLK_B_i : in STD_LOGIC; ADC_CLK_C_i : in STD_LOGIC; ADC_CLK_D_i : in STD_LOGIC; ADC_RESET_o : out STD_LOGIC; clk125_npad_i : in STD_LOGIC; clk125_ppad_i : in STD_LOGIC; adc_clk_ppad_i : in STD_LOGIC; adc_clk_npad_i : in STD_LOGIC; vcxo : out STD_LOGIC; -- vcx01_pad_o : out STD_LOGIC; -- vcx00_pad_o : out STD_LOGIC; -- osc_sel_pad_o : out STD_LOGIC; sys_clk106_en_pad_o : out STD_LOGIC; sys_clk125_en_pad_o : out STD_LOGIC; PostMortem_P_PAD : in STD_LOGIC; PostMortem_N_PAD : in STD_LOGIC; TRIGGER_N_PAD : in STD_LOGIC; TRIGGER_P_PAD : in STD_LOGIC; sbc_rst_pad_o : out STD_LOGIC; sbc_irq_pad_o : out STD_LOGIC; sbc_csn_pad_i : in STD_LOGIC; sbc_wrn_pad_i : in STD_LOGIC; sbc_adr_pad_i : in STD_LOGIC_VECTOR (17 downto 2); sbc_dat_pad_io : inout STD_LOGIC_VECTOR (31 downto 0); lemo_mclk_ppad_i : in STD_LOGIC; lemo_mclk_npad_i : in STD_LOGIC; lemo_sclk_npad_i : in STD_LOGIC; lemo_sclk_ppad_i : in STD_LOGIC; lemo_pm_ppad_i : in STD_LOGIC; lemo_pm_npad_i : in STD_LOGIC; lemo_trig_npad_i : in STD_LOGIC; lemo_trig_ppad_i : in STD_LOGIC; lemo_il_pad_o : out STD_LOGIC; fp_led_pad_o : out STD_LOGIC; bp_led0_pad_o : out STD_LOGIC; bp_led1_pad_o : out STD_LOGIC; bp_led2_pad_o : out STD_LOGIC; spi_func_pad_o : out STD_LOGIC; spi_clk_pad_o : out STD_LOGIC; spi_data_pad_o : out STD_LOGIC; spi_cs_ckm_pad_o : out STD_LOGIC; spi_cs_adc1_pad_o : out STD_LOGIC; spi_cs_adc2_pad_o : out STD_LOGIC; spi_cs_adc3_pad_o : out STD_LOGIC; spi_cs_adc4_pad_o : out STD_LOGIC; adc_a_dat_pad_i : in STD_LOGIC_VECTOR (13 downto 0); adc_b_dat_pad_i : in STD_LOGIC_VECTOR (13 downto 0); adc_c_dat_pad_i : in STD_LOGIC_VECTOR (13 downto 0); adc_d_dat_pad_i : in STD_LOGIC_VECTOR (13 downto 0); ddr2high_udqs_pad_io : inout STD_LOGIC; ddr2high_udqsn_pad_io : inout STD_LOGIC; ddr2high_ldqs_pad_io : inout STD_LOGIC; ddr2high_ldqsn_pad_io : inout STD_LOGIC; ddr2low_udqs_pad_io : inout STD_LOGIC; ddr2low_udqsn_pad_io : inout STD_LOGIC; ddr2low_ldqs_pad_io : inout STD_LOGIC; ddr2low_ldqsn_pad_io : inout STD_LOGIC; ddr2high_bank_pad_o : out STD_LOGIC_VECTOR (1 downto 0); ddr2low_bank_pad_o : out STD_LOGIC_VECTOR (1 downto 0); ddr2high_casn_pad_o : out STD_LOGIC; ddr2high_rasn_pad_o : out STD_LOGIC; ddr2high_cke_pad_o : out STD_LOGIC; ddr2high_clk_pad_o : out STD_LOGIC; ddr2high_clkn_pad_o : out STD_LOGIC; ddr2high_wen_pad_o : out STD_LOGIC; ddr2low_casn_pad_o : out STD_LOGIC; ddr2low_cke_pad_o : out STD_LOGIC; ddr2low_clk_pad_o : out STD_LOGIC; ddr2low_clkn_pad_o : out STD_LOGIC; ddr2low_rasn_pad_o : out STD_LOGIC; ddr2low_wen_pad_o : out STD_LOGIC; ddr2high_ldm_pad_o : out STD_LOGIC; ddr2high_udm_pad_o : out STD_LOGIC; ddr2high_odt_pad_o : out STD_LOGIC; ddr2high_csn_pad_o : out STD_LOGIC; ddr2low_ldm_pad_o : out STD_LOGIC; ddr2low_udm_pad_o : out STD_LOGIC; ddr2low_odt_pad_o : out STD_LOGIC; ddr2high_addr_pad_o : out STD_LOGIC_VECTOR (12 downto 0); ddr2low_addr_pad_o : out STD_LOGIC_VECTOR (12 downto 0); ddr2high_data_pad_io : inout STD_LOGIC_VECTOR (15 downto 0); ddr2low_data_pad_io : inout STD_LOGIC_VECTOR (15 downto 0); DIO : inout STD_LOGIC_VECTOR (24 downto 1); DIR : out STD_LOGIC_VECTOR (5 downto 0) ); end Custom_libera_top; architecture Behavioral of Custom_libera_top is ------------------------------------------------------------------- -- -- PLL core component declaration -- ------------------------------------------------------------------- component PLL3 port ( --global signals reset : in std_logic; clk : in std_logic; init : in std_logic; --PLL controls loop_gain : in std_logic_vector (3 downto 0); loop_ctrl : in std_logic; freq_init : in std_logic_vector (31 downto 0); dds_freq_min : in std_logic_vector (31 downto 0); dds_freq_max : in std_logic_vector (31 downto 0); dds_freq_limit_en : in std_logic; ph_init : in std_logic_vector (8 downto 0); --azimuth frev_gain : in std_logic_vector(13 downto 0); LO_delay : in std_logic_vector(7 downto 0); LO_sel : out std_logic; --ADCs input signals adc_a_i : in std_logic_vector (13 downto 0); adc_b_i : in std_logic_vector (13 downto 0); adc_c_i : in std_logic_vector (13 downto 0); -- PHASETABLE WRITE phase_addr_in : in std_logic_vector (12 downto 0); phase_data_in : in std_logic_vector (3 downto 0); write_enable : in std_logic; --others -- trigger : in std_logic; LO_out : out std_logic; --software timings ELFT_in : in std_logic; INJ_cnt_rst : in std_logic; --hardware timings F_rev_in : in std_logic; HC_timing_in : in std_logic; ST_timing_in : in std_logic; inject_trig : in std_logic; --READOUT OF POINTER TABLES C_table_addr : out std_logic; HC_table_addr : out std_logic; HC_TAB_RD_ADDR : in std_logic_vector (4 downto 0); HC_TAB_RD_DAT : out std_logic_vector (31 downto 0); C_TAB_RD_ADDR : in std_logic_vector (12 downto 0); C_TAB_RD_DAT : out std_logic_vector (31 downto 0); ST_TAB_RD_ADDR : in std_logic_vector (2 downto 0); ST_TAB_RD_DAT : out std_logic_vector (31 downto 0); INJ_TAB_RD_ADDR : in std_logic_vector (2 downto 0); INJ_TAB_RD_DAT : out std_logic_vector (31 downto 0); --readout of pointer registers ST_tab_ST_addr : out std_logic_vector (2 downto 0); HC_tab_ST_addr : out std_logic_vector (4 downto 0); C_tab_ST_addr : out std_logic_vector (12 downto 0); INJ_tab_ST_addr : out std_logic_vector (2 downto 0); SDRAM_ST_addr : out std_logic_vector (25 downto 0); --injection number INJ_cnt_o : out std_logic_vector (3 downto 0); --SDRAM SIGNALS SDRAM_ADDR_OUT : out std_logic_vector (25 downto 0); write_SDRAM : out std_logic; result_0 : out std_logic_vector (23 downto 0); result_1 : out std_logic_vector (23 downto 0); result_2 : out std_logic_vector (23 downto 0); -- ANALYSER SIGNALS ANA_record_len : in std_logic_vector(12 downto 0); ANA_addr_pointer : out std_logic_vector(12 downto 0); ANA_RD_addr : in std_logic_vector(13 downto 0); ANA_RD_DAT : out std_logic_vector(31 downto 0); ANA_slope : in std_logic; ANA_ARM : in std_logic; ANA_timer_en : in std_logic; ANA_DATA_ACQUIRED : out std_logic; ANA_trig_src : in std_logic_vector(2 downto 0); ANA_CH1_src : in std_logic_vector(2 downto 0); ANA_CH2_src : in std_logic_vector(2 downto 0); ANA_timer : in std_logic_vector(23 downto 0); ANA_delay : in std_logic_vector(31 downto 0) ); end component; --address decoder signals signal data_Reg_out : std_logic_vector (31 downto 0); --phase table signals signal phase_addr_in : std_logic_vector (12 downto 0); signal phase_data_in : std_logic_vector (3 downto 0); signal write_enable : std_logic; --edge detector signals signal edge_reg : std_logic_vector(3 downto 0); signal edge_h, edge_l, trig_i: std_logic; signal reset : std_logic; --register set signal reg0, reg1, reg2, reg3, reg4, reg5, reg6,reg7,reg8,reg9,regA,regB,regC,regD,regE,regF, data_out,data_mem_out : std_logic_vector(31 downto 0); signal clk,clk_en_500k, adc_clk, lemo_mclk, lemo_sclk, lemo_pm, lemo_trig,init : std_logic; signal timer : integer range 0 to 63 :=0; --timer 500kHz signal ADC_A_buf,ADC_B_buf,ADC_C_buf,ADC_D_buf : std_logic_vector(13 downto 0); signal F_rev_in : std_logic; signal HC_timing_in : std_logic; signal ST_timing_in : std_logic; signal inject_trig : std_logic; --READOUT OF POINTER TABLES signal C_table_addr : std_logic; signal HC_table_addr : std_logic; signal HC_TAB_RD_ADDR : std_logic_vector (4 downto 0); signal HC_TAB_RD_DAT : std_logic_vector (31 downto 0); signal C_TAB_RD_ADDR : std_logic_vector (12 downto 0); signal C_TAB_RD_DAT : std_logic_vector (31 downto 0); signal ST_TAB_RD_ADDR : std_logic_vector (2 downto 0); signal ST_TAB_RD_DAT : std_logic_vector (31 downto 0); signal INJ_TAB_RD_ADDR : std_logic_vector (2 downto 0); signal INJ_TAB_RD_DAT : std_logic_vector (31 downto 0); --readout of pointer registers signal ST_tab_ST_addr : std_logic_vector (2 downto 0); signal HC_tab_ST_addr : std_logic_vector (4 downto 0); signal C_tab_ST_addr : std_logic_vector (12 downto 0); signal INJ_tab_ST_addr : std_logic_vector (2 downto 0); signal SDRAM_ST_addr : std_logic_vector (25 downto 0); signal frev_gain : std_logic_vector(13 downto 0); signal LO_delay : std_logic_vector(7 downto 0); signal sel_lo_delay : std_logic; signal LO_sel : std_logic; signal ph_table_no : std_logic; signal int_sbc_addr : std_logic_vector(17 downto 0); --analyser signals signal ANA_record_len : std_logic_vector(12 downto 0); signal ANA_addr_pointer : std_logic_vector(12 downto 0); signal ANA_RD_addr : std_logic_vector(13 downto 0); signal ANA_RD_DAT : std_logic_vector(31 downto 0); signal ANA_slope : std_logic; signal ANA_ARM : std_logic; signal ANA_timer_en : std_logic; signal ANA_DATA_ACQUIRED : std_logic; signal ANA_trig_src : std_logic_vector(2 downto 0); signal ANA_CH1_src : std_logic_vector(2 downto 0); signal ANA_CH2_src : std_logic_vector(2 downto 0); signal ANA_timer : std_logic_vector(23 downto 0); signal ANA_delay : std_logic_vector(31 downto 0); begin ------------------------------------------------------------------- -- -- input signals buffering - differential do single ended convertion -- ------------------------------------------------------------------- --lemo_trig IBUFGDS_lemo_trig : IBUFDS generic map ( CAPACITANCE => "DONT_CARE", -- "LOW", "NORMAL", "DONT_CARE" (Virtex-4 only) DIFF_TERM => FALSE, -- Differential Termination (Virtex-4, Spartan-3E) IBUF_DELAY_VALUE => "0", -- Specify the amount of added input delay for buffer, "0"-"16" (Spartan-3E only) IFD_DELAY_VALUE => "AUTO", -- Specify the amount of added delay for input register, "AUTO", "0"-"8" (Spartan-3E only) IOSTANDARD => "DEFAULT") port map ( O => lemo_trig, -- Clock buffer output I => lemo_trig_ppad_i, -- Diff_p clock buffer input (connect directly to top-level port) IB => lemo_trig_npad_i -- Diff_n clock buffer input (connect directly to top-level port) ); --lemo pm IBUFGDS_lemo_pm : IBUFDS generic map ( CAPACITANCE => "DONT_CARE", -- "LOW", "NORMAL", "DONT_CARE" (Virtex-4 only) DIFF_TERM => FALSE, -- Differential Termination (Virtex-4, Spartan-3E) IBUF_DELAY_VALUE => "0", -- Specify the amount of added input delay for buffer, "0"-"16" (Spartan-3E only) IFD_DELAY_VALUE => "AUTO", -- Specify the amount of added delay for input register, "AUTO", "0"-"8" (Spartan-3E only) IOSTANDARD => "DEFAULT") port map ( O => lemo_pm, -- Clock buffer output I => lemo_pm_ppad_i, -- Diff_p clock buffer input (connect directly to top-level port) IB => lemo_pm_npad_i -- Diff_n clock buffer input (connect directly to top-level port) ); --lemo mclk IBUFGDS_lemo_mclk : IBUFGDS generic map ( DIFF_TERM => FALSE, -- Differential Termination (Virtex-4 only) IBUF_DELAY_VALUE => "0", -- Specify the amount of added input delay for buffer, "0"-"16" (Spartan-3E only) IOSTANDARD => "DEFAULT") port map ( O => lemo_mclk, -- Clock buffer output I => lemo_mclk_ppad_i, -- Diff_p clock buffer input (connect directly to top-level port) IB => lemo_mclk_npad_i -- Diff_n clock buffer input (connect directly to top-level port) ); --lemo sclk IBUFGDS_lemo_sclk : IBUFGDS generic map ( DIFF_TERM => FALSE, -- Differential Termination (Virtex-4 only) IBUF_DELAY_VALUE => "0", -- Specify the amount of added input delay for buffer, "0"-"16" (Spartan-3E only) IOSTANDARD => "DEFAULT") port map ( O => lemo_sclk, -- Clock buffer output I => lemo_sclk_ppad_i, -- Diff_p clock buffer input (connect directly to top-level port) IB => lemo_sclk_npad_i -- Diff_n clock buffer input (connect directly to top-level port) ); --clk IBUFGDS_clk : IBUFGDS generic map ( DIFF_TERM => FALSE, -- Differential Termination (Virtex-4 only) IBUF_DELAY_VALUE => "0", -- Specify the amount of added input delay for buffer, "0"-"16" (Spartan-3E only) IOSTANDARD => "DEFAULT") port map ( O => clk, -- Clock buffer output I => clk125_ppad_i, -- Diff_p clock buffer input (connect directly to top-level port) IB => clk125_npad_i -- Diff_n clock buffer input (connect directly to top-level port) ); --adc_clk IBUFGDS_adc : IBUFGDS generic map ( DIFF_TERM => FALSE, -- Differential Termination (Virtex-4 only) IBUF_DELAY_VALUE => "0", -- Specify the amount of added input delay for buffer, "0"-"16" (Spartan-3E only) IOSTANDARD => "DEFAULT") port map ( O => adc_clk, -- Clock buffer output I => adc_clk_ppad_i, -- Diff_p clock buffer input (connect directly to top-level port) IB => adc_clk_npad_i -- Diff_n clock buffer input (connect directly to top-level port) ); ------------------------------------------------------------------- -- -- register write process -- ------------------------------------------------------------------- int_sbc_addr <= sbc_adr_pad_i & "00"; process(sbc_csn_pad_i,sbc_wrn_pad_i) begin if rising_edge(sbc_csn_pad_i) then if sbc_wrn_pad_i = '0' then case int_sbc_addr(15 downto 0) is when x"0000" => reg0<=sbc_dat_pad_io; when x"0004" => reg1<=sbc_dat_pad_io; when x"0008" => reg2<=sbc_dat_pad_io; when x"000C" => reg3<=sbc_dat_pad_io; when x"0010" => reg4<=sbc_dat_pad_io; when x"0014" => reg5<=sbc_dat_pad_io; when x"0018" => reg6<=sbc_dat_pad_io; --when x"001C" => reg7<=sbc_dat_pad_io; --when x"0020" => reg8<=sbc_dat_pad_io; --when x"0024" => reg9<=sbc_dat_pad_io; when x"0028" => regA<=sbc_dat_pad_io; -- when x"002C" => regB<=sbc_dat_pad_io; when x"0030" => regC<=sbc_dat_pad_io; when x"0034" => regD<=sbc_dat_pad_io; -- when x"0038" => regE<=sbc_dat_pad_io; when x"003C" => regF<=sbc_dat_pad_io; when others => reg0<=x"00000000"; end case; end if; end if; end process; ------------------------------------------------------------------- -- -- register readout process -- ------------------------------------------------------------------- readout: WITH int_sbc_addr(15 downto 8) SELECT --SELECTS memory range to read data_mem_out <=data_Reg_out when x"00", --rgister set select INJ_TAB_RD_DAT when x"01", HC_TAB_RD_DAT when x"02", ST_TAB_RD_DAT when x"03", x"00000000" when others; WITH int_sbc_addr(17 downto 16) SELECT --SELECTS memory range to read data_out <= data_mem_out when "00", C_TAB_RD_DAT when "01", ANA_RD_DAT when "10", x"00000000" when others; ANA_RD_addr <=int_sbc_addr(15 downto 2); HC_TAB_RD_ADDR <=int_sbc_addr(6 downto 2); C_TAB_RD_ADDR <=int_sbc_addr(14 downto 2); ST_TAB_RD_ADDR <=int_sbc_addr(4 downto 2); INJ_TAB_RD_ADDR<=int_sbc_addr(4 downto 2); reg8 <= "00"& ST_tab_ST_addr & "00" & INJ_tab_ST_addr & "00" & C_tab_ST_addr & "00" & HC_tab_ST_addr; reg9 <= "000000" & SDRAM_ST_addr; WITH int_sbc_addr(7 downto 0) SELECT --SELECTS REGISTERS TO BE READ data_Reg_out<= reg0 when x"00", reg1 when x"04", reg2 when x"08", reg3 when x"0C", reg4 when x"10", reg5 when x"14", reg6 when x"18", reg7 when x"1C", reg8 when x"20", reg9 when x"24", regA when x"28", regB when x"2C", regC when x"30", regD when x"34", regE when x"38", regF when x"3C", x"00000000" when others; ANA_record_len <= regA(28 downto 16); ANA_timer_en <= regA(14); ANA_slope <= regA(13); ANA_ARM <= regA(12); ANA_CH1_src <= regA(10 downto 8); ANA_CH2_src <= regA(6 downto 4); ANA_trig_src <= regA(2 downto 0); ANA_timer <= regC(23 downto 0); ANA_delay <= regD(31 downto 0); regB <= x"0000" & "000" & ANA_addr_pointer; regE(0) <= ANA_DATA_ACQUIRED; --tristate buffer PROCESS (sbc_csn_pad_i,sbc_wrn_pad_i,data_out) BEGIN IF (sbc_csn_pad_i = '0' and sbc_wrn_pad_i = '1' ) THEN sbc_dat_pad_io <= data_out; ELSE sbc_dat_pad_io <= (others=>'Z'); END IF; END PROCESS; ------------------------------------------------------------------- -- -- ADC and CKM control pins assignment -- ------------------------------------------------------------------- vcxo <=reg1(0); sys_clk106_en_pad_o <= reg1(1); sys_clk125_en_pad_o <= reg1(2); spi_func_pad_o <= reg1(3); spi_clk_pad_o <= reg1(4); spi_data_pad_o <= reg1(5); spi_cs_adc1_pad_o <= reg1(6); spi_cs_adc2_pad_o <= reg1(7); spi_cs_adc3_pad_o <= reg1(8); spi_cs_adc4_pad_o <= reg1(9); spi_cs_ckm_pad_o <= reg1(10); ADC_RESET_o <= reg1(11); ------------------------------------------------------------------- -- -- ADC signals buffering -- ------------------------------------------------------------------- PROCESS(ADC_CLK) begin if rising_edge(adc_clk) then ADC_A_buf <= (not adc_a_dat_pad_i(13))& adc_a_dat_pad_i(12 downto 0); ADC_B_buf <= (not adc_b_dat_pad_i(13))& adc_b_dat_pad_i(12 downto 0); ADC_C_buf <= (not adc_c_dat_pad_i(13))& adc_c_dat_pad_i(12 downto 0); ADC_D_buf <= (not adc_d_dat_pad_i(13))& adc_d_dat_pad_i(12 downto 0); end if; end process; ------------------------------------------------------------------- -- -- PLL assignment -- ------------------------------------------------------------------- PLL: PLL3 port map ( --global signals reset => reset, --same as ADC RESET init => init, clk => adc_clk, --PLL controls ph_init => reg3(24 downto 16), -- azimuth loop_gain => reg3(7 downto 4), loop_ctrl => reg3(1), freq_init => reg2(31 downto 0), dds_freq_min => reg4(31 downto 0), dds_freq_max => reg5(31 downto 0), dds_freq_limit_en => reg3(2), frev_gain => reg6(13 downto 0), LO_delay => reg7(7 downto 0), --ADCs input signals adc_a_i => ADC_A_buf, adc_b_i => ADC_B_buf, adc_c_i => ADC_C_buf, -- PHASETABLE WRITE phase_addr_in => phase_addr_in, phase_data_in => phase_data_in, write_enable => write_enable, --software timings ELFT_in => '0', INJ_cnt_rst => '0', --hardware timings F_rev_in => DIO(18) , HC_timing_in => DIO(19) , ST_timing_in => DIO(20) , inject_trig => DIO(17) , --READOUT OF POINTER TABLES C_table_addr => C_table_addr, HC_table_addr => HC_table_addr, HC_TAB_RD_ADDR => HC_TAB_RD_ADDR, HC_TAB_RD_DAT => HC_TAB_RD_DAT, C_TAB_RD_ADDR => C_TAB_RD_ADDR, C_TAB_RD_DAT => C_TAB_RD_DAT, ST_TAB_RD_ADDR => ST_TAB_RD_ADDR, ST_TAB_RD_DAT => ST_TAB_RD_DAT, INJ_TAB_RD_ADDR => INJ_TAB_RD_ADDR, INJ_TAB_RD_DAT => INJ_TAB_RD_DAT, INJ_cnt_o => open, --readout of pointer registers ST_tab_ST_addr => ST_tab_ST_addr, HC_tab_ST_addr => HC_tab_ST_addr, C_tab_ST_addr => C_tab_ST_addr, INJ_tab_ST_addr => INJ_tab_ST_addr, SDRAM_ST_addr => SDRAM_ST_addr, --SDRAM SIGNALS SDRAM_ADDR_OUT => open, result_0 => open, result_1 => open, result_2 => open, write_SDRAM => open, --analser signals LO_out => DIO(7), ANA_record_len => ANA_record_len, ANA_addr_pointer => ANA_addr_pointer, ANA_RD_addr => ANA_RD_addr, ANA_RD_DAT => ANA_RD_DAT, ANA_slope => ANA_slope, ANA_ARM => ANA_ARM, ANA_timer_en => ANA_timer_en, ANA_DATA_ACQUIRED => ANA_DATA_ACQUIRED, ANA_trig_src => ANA_trig_src, ANA_CH1_src => ANA_CH1_src, ANA_CH2_src => ANA_CH2_src, ANA_timer => ANA_timer, ANA_delay => ANA_delay ); --init <=(reg1(11) or reg3(0)); init <=( trig_i or reg3(0)); --*************************************************************************************************** --*************************************** phase table ******************************* --*************************************************************************************************** -- phase_addr_in <= reg0(12 downto 0); phase_addr_in <= "0000" & reg0(8 downto 0); phase_data_in <= reg0(19 downto 16); write_enable <= reg0(23); --*************************************************************************************************** --*************************************** trigger edge detection ******************************* --*************************************************************************************************** process (adc_clk) begin if rising_edge(adc_clk) then edge_reg(0)<= (not DIO(17)); edge_reg(1)<=edge_reg(0); edge_reg(2)<=edge_reg(1); edge_reg(3)<=edge_reg(2); end if; end process; edge_l <= (not edge_reg(0)) and (not edge_reg(1)) and edge_reg(2)and edge_reg(3) ; edge_h <= (not edge_reg(3)) and (not edge_reg(2)) and edge_reg(1)and edge_reg(0) ; trig_i <= edge_h; --trig_i <= mainck; fp_led_pad_o <=reg1(16); bp_led0_pad_o <=reg1(17); bp_led1_pad_o <=reg1(18); bp_led2_pad_o <=reg1(19); -- fp_led_pad_o <= not lemo_sclk xor reg1(16); -- bp_led0_pad_o <= not lemo_mclk xor reg1(17); -- bp_led1_pad_o <= not lemo_pm xor reg1(18); -- bp_led2_pad_o <= not lemo_trig xor reg1(19); -- fp_led_pad_o <= not DIO(20) ; -- bp_led0_pad_o <= not DIO(19) ; -- bp_led1_pad_o <= not DIO(18) ; -- bp_led2_pad_o <= not DIO(17) ; -- DIR(0)<= reg1(16); -- DIR(1)<= reg1(17); -- DIR(2)<= reg1(18); -- DIR(3)<= reg1(19); -- DIR(4)<= reg1(19); -- DIR(5)<= reg1(19); --unknown DIO(16 downto 9) <= "ZZZZZZZZ"; DIO(24 downto 21) <= "ZZZZ"; --user DIO(1) <= clk; DIO(2) <= adc_clk; DIO(3) <= ADC_CLK_A_i ; DIO(4) <= ADC_CLK_B_i ; DIO(5) <= ADC_CLK_C_i ; DIO(6) <= ADC_CLK_D_i ; DIO(8) <= '0'; -- DIO(20 downto 17) <= "ZZZZ"; DIR(5 downto 0) <= "000011"; -- vcx01_pad_o <= reg0(5); -- vcx00_pad_o <= reg0(6); -- osc_sel_pad_o <= reg0(7); sbc_rst_pad_o <= '0'; sbc_irq_pad_o <= '0'; lemo_il_pad_o <= '0'; --DDR memory pins ddr2high_udqs_pad_io <= 'Z'; ddr2high_udqsn_pad_io <= 'Z'; ddr2high_ldqs_pad_io <= 'Z'; ddr2high_ldqsn_pad_io <= 'Z'; ddr2low_udqs_pad_io <= 'Z'; ddr2low_udqsn_pad_io <= 'Z'; ddr2low_ldqs_pad_io <= 'Z'; ddr2low_ldqsn_pad_io <= 'Z'; ddr2high_bank_pad_o <="00"; ddr2low_bank_pad_o <="00"; ddr2high_casn_pad_o <= '0'; ddr2high_rasn_pad_o <= '0'; ddr2high_cke_pad_o <= '0'; ddr2high_clk_pad_o <= '0'; ddr2high_clkn_pad_o <= '0'; ddr2high_wen_pad_o <= '0'; ddr2low_casn_pad_o <= '0'; ddr2low_cke_pad_o <= '0'; ddr2low_clk_pad_o <= '0'; ddr2low_clkn_pad_o <= '0'; ddr2low_rasn_pad_o <= '0'; ddr2low_wen_pad_o <= '0'; ddr2high_ldm_pad_o <= '0'; ddr2high_udm_pad_o <= '0'; ddr2high_odt_pad_o <= '0'; ddr2high_csn_pad_o <= '0'; ddr2low_ldm_pad_o <= '0'; ddr2low_udm_pad_o <= '0'; ddr2low_odt_pad_o <= '0'; ddr2high_addr_pad_o <=(others => '0'); ddr2low_addr_pad_o <=(others => '0'); ddr2high_data_pad_io <=(others => 'Z'); ddr2low_data_pad_io <=(others => 'Z'); end Behavioral;