xst -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -ifn Custom_libera_top.xst -ofn Custom_libera_top.syr xst -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -ifn Custom_libera_top.xst -ofn Custom_libera_top.syr xst -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -ifn Custom_libera_top.xst -ofn Custom_libera_top.syr xst -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -ifn Custom_libera_top.xst -ofn Custom_libera_top.syr ngdbuild -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -dd _ngo -nt timestamp -uc Custom_Libera.ucf -p xc2vp30-ff1152-6 Custom_libera_top.ngc Custom_libera_top.ngd ngdbuild -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -dd _ngo -nt timestamp -uc Custom_Libera.ucf -p xc2vp30-ff1152-6 Custom_libera_top.ngc Custom_libera_top.ngd ngdbuild -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -dd _ngo -nt timestamp -uc Custom_Libera.ucf -p xc2vp30-ff1152-6 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"C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -dd _ngo -nt timestamp -uc Custom_Libera.ucf -p xc2vp30-ff1152-6 Custom_libera_top.ngc Custom_libera_top.ngd map -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -p xc2vp30-ff1152-6 -cm area -pr b -k 4 -c 100 -tx off -o Custom_libera_top_map.ncd Custom_libera_top.ngd Custom_libera_top.pcf par -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -w -intstyle ise -ol std -t 1 Custom_libera_top_map.ncd Custom_libera_top.ncd Custom_libera_top.pcf trce -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -e 3 -l 3 -s 6 -xml Custom_libera_top Custom_libera_top.ncd -o Custom_libera_top.twr Custom_libera_top.pcf ngdbuild -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -dd _ngo -nt timestamp -uc Custom_Libera.ucf -p xc2vp30-ff1152-6 Custom_libera_top.ngc Custom_libera_top.ngd map -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -p xc2vp30-ff1152-6 -cm area -pr b -k 4 -c 100 -tx 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"C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -p xc2vp30-ff1152-6 -cm area -pr b -k 4 -c 100 -tx off -o Custom_libera_top_map.ncd Custom_libera_top.ngd Custom_libera_top.pcf par -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -w -intstyle ise -ol std -t 1 Custom_libera_top_map.ncd Custom_libera_top.ncd Custom_libera_top.pcf trce -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -e 3 -l 3 -s 6 -xml Custom_libera_top Custom_libera_top.ncd -o Custom_libera_top.twr Custom_libera_top.pcf ngdbuild -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -dd _ngo -nt timestamp -uc Custom_Libera.ucf -p xc2vp30-ff1152-6 Custom_libera_top.ngc Custom_libera_top.ngd map -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -p xc2vp30-ff1152-6 -cm area -pr b -k 4 -c 100 -tx off -o Custom_libera_top_map.ncd Custom_libera_top.ngd Custom_libera_top.pcf par -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -w -intstyle ise -ol std -t 1 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"C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -f Custom_libera_top.ut Custom_libera_top.ncd xst -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -ifn Custom_libera_top.xst -ofn Custom_libera_top.syr xst -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -ifn Custom_libera_top.xst -ofn Custom_libera_top.syr ngdbuild -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -dd _ngo -nt timestamp -uc Custom_Libera.ucf -p xc2vp30-ff1152-6 Custom_libera_top.ngc Custom_libera_top.ngd map -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -p xc2vp30-ff1152-6 -cm area -pr b -k 4 -c 100 -tx off -o Custom_libera_top_map.ncd Custom_libera_top.ngd Custom_libera_top.pcf par -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -w -intstyle ise -ol std -t 1 Custom_libera_top_map.ncd Custom_libera_top.ncd Custom_libera_top.pcf trce -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -e 3 -l 3 -s 6 -xml Custom_libera_top Custom_libera_top.ncd -o Custom_libera_top.twr Custom_libera_top.pcf bitgen -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -f Custom_libera_top.ut Custom_libera_top.ncd xst -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -ifn Custom_libera_top.xst -ofn Custom_libera_top.syr xst -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -ifn Custom_libera_top.xst -ofn Custom_libera_top.syr ngdbuild -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -dd _ngo -nt timestamp -uc Custom_Libera.ucf -p xc2vp30-ff1152-6 Custom_libera_top.ngc Custom_libera_top.ngd map -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -p xc2vp30-ff1152-6 -cm area -pr b -k 4 -c 100 -tx off -o Custom_libera_top_map.ncd Custom_libera_top.ngd Custom_libera_top.pcf par -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -w -intstyle ise -ol std -t 1 Custom_libera_top_map.ncd Custom_libera_top.ncd Custom_libera_top.pcf trce -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -e 3 -l 3 -s 6 -xml Custom_libera_top Custom_libera_top.ncd -o Custom_libera_top.twr Custom_libera_top.pcf bitgen -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -f Custom_libera_top.ut Custom_libera_top.ncd xst -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -ifn Custom_libera_top.xst -ofn Custom_libera_top.syr xst -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -ifn Custom_libera_top.xst -ofn Custom_libera_top.syr ngdbuild -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -dd _ngo -nt timestamp -uc Custom_Libera.ucf -p xc2vp30-ff1152-6 Custom_libera_top.ngc Custom_libera_top.ngd map -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -p xc2vp30-ff1152-6 -cm area -pr b -k 4 -c 100 -tx off -o Custom_libera_top_map.ncd Custom_libera_top.ngd Custom_libera_top.pcf par -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -w -intstyle ise -ol std -t 1 Custom_libera_top_map.ncd Custom_libera_top.ncd Custom_libera_top.pcf trce -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -e 3 -l 3 -s 6 -xml Custom_libera_top Custom_libera_top.ncd -o Custom_libera_top.twr Custom_libera_top.pcf bitgen -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -f Custom_libera_top.ut Custom_libera_top.ncd xst -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -ifn Custom_libera_top.xst -ofn Custom_libera_top.syr xst -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -ifn Custom_libera_top.xst -ofn Custom_libera_top.syr ngdbuild -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -dd _ngo -nt timestamp -uc Custom_Libera.ucf -p xc2vp30-ff1152-6 Custom_libera_top.ngc Custom_libera_top.ngd map -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -p xc2vp30-ff1152-6 -cm area -pr b -k 4 -c 100 -tx off -o Custom_libera_top_map.ncd Custom_libera_top.ngd Custom_libera_top.pcf par -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -w -intstyle ise -ol std -t 1 Custom_libera_top_map.ncd Custom_libera_top.ncd Custom_libera_top.pcf trce -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -e 3 -l 3 -s 6 -xml Custom_libera_top Custom_libera_top.ncd -o Custom_libera_top.twr Custom_libera_top.pcf bitgen -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -f Custom_libera_top.ut Custom_libera_top.ncd ngdbuild -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -dd _ngo -nt timestamp -uc Custom_Libera.ucf -p xc2vp30-ff1152-6 Custom_libera_top_cs.ngc Custom_libera_top.ngd xst -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -ifn Custom_libera_top.xst -ofn Custom_libera_top.syr xst -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -ifn Custom_libera_top.xst -ofn Custom_libera_top.syr xst -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -ifn Custom_libera_top.xst -ofn Custom_libera_top.syr ngdbuild -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -dd _ngo -nt timestamp -uc Custom_Libera.ucf -p xc2vp30-ff1152-6 Custom_libera_top.ngc Custom_libera_top.ngd map -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -p xc2vp30-ff1152-6 -cm area -pr b -k 4 -c 100 -tx off -o Custom_libera_top_map.ncd Custom_libera_top.ngd Custom_libera_top.pcf par -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -w -intstyle ise -ol std -t 1 Custom_libera_top_map.ncd Custom_libera_top.ncd Custom_libera_top.pcf trce -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -e 3 -l 3 -s 6 -xml Custom_libera_top Custom_libera_top.ncd -o Custom_libera_top.twr Custom_libera_top.pcf xst -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -ifn Custom_libera_top.xst -ofn Custom_libera_top.syr xst -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -ifn Custom_libera_top.xst -ofn Custom_libera_top.syr ngdbuild -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -dd _ngo -nt timestamp -uc Custom_Libera.ucf -p xc2vp30-ff1152-6 Custom_libera_top.ngc Custom_libera_top.ngd map -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -p xc2vp30-ff1152-6 -cm area -pr b -k 4 -c 100 -tx off -o Custom_libera_top_map.ncd Custom_libera_top.ngd Custom_libera_top.pcf par -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -w -intstyle ise -ol std -t 1 Custom_libera_top_map.ncd Custom_libera_top.ncd Custom_libera_top.pcf trce -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -e 3 -l 3 -s 6 -xml Custom_libera_top Custom_libera_top.ncd -o Custom_libera_top.twr Custom_libera_top.pcf bitgen -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -f Custom_libera_top.ut Custom_libera_top.ncd xst -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -ifn Custom_libera_top.xst -ofn Custom_libera_top.syr ngdbuild -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -dd _ngo -nt timestamp -uc Custom_Libera.ucf -p xc2vp30-ff1152-6 Custom_libera_top.ngc Custom_libera_top.ngd map -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -p xc2vp30-ff1152-6 -cm area -pr b -k 4 -c 100 -tx off -o Custom_libera_top_map.ncd Custom_libera_top.ngd Custom_libera_top.pcf par -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -w -intstyle ise -ol std -t 1 Custom_libera_top_map.ncd Custom_libera_top.ncd Custom_libera_top.pcf trce -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -e 3 -l 3 -s 6 -xml Custom_libera_top Custom_libera_top.ncd -o Custom_libera_top.twr Custom_libera_top.pcf bitgen -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -f Custom_libera_top.ut Custom_libera_top.ncd xst -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -ifn Custom_libera_top.xst -ofn Custom_libera_top.syr xst -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -ifn Custom_libera_top.xst -ofn Custom_libera_top.syr ngdbuild -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -dd _ngo -nt timestamp -uc Custom_Libera.ucf -p xc2vp30-ff1152-6 Custom_libera_top.ngc Custom_libera_top.ngd map -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -p xc2vp30-ff1152-6 -cm area -pr b -k 4 -c 100 -tx off -o Custom_libera_top_map.ncd Custom_libera_top.ngd Custom_libera_top.pcf par -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -w -intstyle ise -ol std -t 1 Custom_libera_top_map.ncd Custom_libera_top.ncd Custom_libera_top.pcf trce -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -e 3 -l 3 -s 6 -xml Custom_libera_top Custom_libera_top.ncd -o Custom_libera_top.twr Custom_libera_top.pcf bitgen -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -f Custom_libera_top.ut Custom_libera_top.ncd xst -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -ifn Custom_libera_top.xst -ofn Custom_libera_top.syr xst -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -ifn Custom_libera_top.xst -ofn Custom_libera_top.syr xst -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -ifn Custom_libera_top.xst -ofn Custom_libera_top.syr ngdbuild -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -dd _ngo -nt timestamp -uc Custom_Libera.ucf -p xc2vp30-ff1152-6 Custom_libera_top.ngc Custom_libera_top.ngd map -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -p xc2vp30-ff1152-6 -cm area -pr b -k 4 -c 100 -tx off -o Custom_libera_top_map.ncd Custom_libera_top.ngd Custom_libera_top.pcf par -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -w -intstyle ise -ol std -t 1 Custom_libera_top_map.ncd Custom_libera_top.ncd Custom_libera_top.pcf trce -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -e 3 -l 3 -s 6 -xml Custom_libera_top Custom_libera_top.ncd -o Custom_libera_top.twr Custom_libera_top.pcf bitgen -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -f Custom_libera_top.ut Custom_libera_top.ncd xst -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -ifn Custom_libera_top.xst -ofn Custom_libera_top.syr xst -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -ifn Custom_libera_top.xst -ofn Custom_libera_top.syr ngdbuild -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -dd _ngo -nt timestamp -uc Custom_Libera.ucf -p xc2vp30-ff1152-6 Custom_libera_top.ngc Custom_libera_top.ngd map -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -p xc2vp30-ff1152-6 -cm area -pr b -k 4 -c 100 -tx off -o Custom_libera_top_map.ncd Custom_libera_top.ngd Custom_libera_top.pcf par -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -w -intstyle ise -ol std -t 1 Custom_libera_top_map.ncd Custom_libera_top.ncd Custom_libera_top.pcf trce -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -e 3 -l 3 -s 6 -xml Custom_libera_top Custom_libera_top.ncd -o Custom_libera_top.twr Custom_libera_top.pcf bitgen -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -f Custom_libera_top.ut Custom_libera_top.ncd xst -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -ifn Custom_libera_top.xst -ofn Custom_libera_top.syr ngdbuild -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -dd _ngo -nt timestamp -uc Custom_Libera.ucf -p xc2vp30-ff1152-6 Custom_libera_top.ngc Custom_libera_top.ngd map -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -p xc2vp30-ff1152-6 -cm area -pr b -k 4 -c 100 -tx off -o Custom_libera_top_map.ncd Custom_libera_top.ngd Custom_libera_top.pcf par -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -w -intstyle ise -ol std -t 1 Custom_libera_top_map.ncd Custom_libera_top.ncd Custom_libera_top.pcf ngdbuild -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -dd _ngo -nt timestamp -uc Custom_Libera.ucf -p xc2vp30-ff1152-6 Custom_libera_top.ngc Custom_libera_top.ngd map -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -p xc2vp30-ff1152-6 -cm area -pr b -k 4 -c 100 -tx off -o Custom_libera_top_map.ncd Custom_libera_top.ngd Custom_libera_top.pcf par -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -w -intstyle ise -ol std -t 1 Custom_libera_top_map.ncd Custom_libera_top.ncd Custom_libera_top.pcf trce -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -e 3 -l 3 -s 6 -xml Custom_libera_top Custom_libera_top.ncd -o Custom_libera_top.twr Custom_libera_top.pcf bitgen -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -f Custom_libera_top.ut Custom_libera_top.ncd ngdbuild -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -dd _ngo -nt timestamp -uc Custom_Libera.ucf -p xc2vp30-ff1152-6 Custom_libera_top.ngc Custom_libera_top.ngd map -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -p xc2vp30-ff1152-6 -cm area -pr b -k 4 -c 100 -tx off -o Custom_libera_top_map.ncd Custom_libera_top.ngd Custom_libera_top.pcf par -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -w -intstyle ise -ol std -t 1 Custom_libera_top_map.ncd Custom_libera_top.ncd Custom_libera_top.pcf trce -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -e 3 -l 3 -s 6 -xml Custom_libera_top Custom_libera_top.ncd -o Custom_libera_top.twr Custom_libera_top.pcf bitgen -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -f Custom_libera_top.ut Custom_libera_top.ncd xst -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -ifn Custom_libera_top.xst -ofn Custom_libera_top.syr ngdbuild -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -dd _ngo -nt timestamp -uc Custom_Libera.ucf -p xc2vp30-ff1152-6 Custom_libera_top.ngc Custom_libera_top.ngd map -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -p xc2vp30-ff1152-6 -cm area -pr b -k 4 -c 100 -tx off -o Custom_libera_top_map.ncd Custom_libera_top.ngd Custom_libera_top.pcf par -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -w -intstyle ise -ol std -t 1 Custom_libera_top_map.ncd Custom_libera_top.ncd Custom_libera_top.pcf trce -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -e 3 -l 3 -s 6 -xml Custom_libera_top Custom_libera_top.ncd -o Custom_libera_top.twr Custom_libera_top.pcf bitgen -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -f Custom_libera_top.ut Custom_libera_top.ncd ngdbuild -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -dd _ngo -nt timestamp -uc Custom_Libera.ucf -p xc2vp30-ff1152-6 Custom_libera_top.ngc Custom_libera_top.ngd map -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -p xc2vp30-ff1152-6 -cm area -pr b -k 4 -c 100 -tx off -o Custom_libera_top_map.ncd Custom_libera_top.ngd Custom_libera_top.pcf xst -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -ifn Custom_libera_top.xst -ofn Custom_libera_top.syr xst -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -ifn Custom_libera_top.xst -ofn Custom_libera_top.syr ngdbuild -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -dd _ngo -nt timestamp -uc Custom_Libera.ucf -p xc2vp30-ff1152-6 Custom_libera_top.ngc Custom_libera_top.ngd map -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -p xc2vp30-ff1152-6 -cm area -pr b -k 4 -c 100 -tx off -o Custom_libera_top_map.ncd Custom_libera_top.ngd Custom_libera_top.pcf ngdbuild -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -dd _ngo -nt timestamp -uc Custom_Libera.ucf -p xc2vp30-ff1152-6 Custom_libera_top.ngc Custom_libera_top.ngd map -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -p xc2vp30-ff1152-6 -cm area -pr b -k 4 -c 100 -tx off -o Custom_libera_top_map.ncd Custom_libera_top.ngd Custom_libera_top.pcf par -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -w -intstyle ise -ol std -t 1 Custom_libera_top_map.ncd Custom_libera_top.ncd Custom_libera_top.pcf xst -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -ifn Custom_libera_top.xst -ofn Custom_libera_top.syr trce -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -e 3 -l 3 -s 6 -xml Custom_libera_top Custom_libera_top.ncd -o Custom_libera_top.twr Custom_libera_top.pcf ngdbuild -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -dd _ngo -nt timestamp -uc Custom_Libera.ucf -p xc2vp30-ff1152-6 Custom_libera_top.ngc Custom_libera_top.ngd map -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -p xc2vp30-ff1152-6 -cm area -pr b -k 4 -c 100 -tx off -o Custom_libera_top_map.ncd Custom_libera_top.ngd Custom_libera_top.pcf par -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -w -intstyle ise -ol std -t 1 Custom_libera_top_map.ncd Custom_libera_top.ncd Custom_libera_top.pcf trce -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -e 3 -l 3 -s 6 -xml Custom_libera_top Custom_libera_top.ncd -o Custom_libera_top.twr Custom_libera_top.pcf bitgen -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -f Custom_libera_top.ut Custom_libera_top.ncd xst -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -ifn Custom_libera_top.xst -ofn Custom_libera_top.syr ngdbuild -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -dd _ngo -nt timestamp -uc Custom_Libera.ucf -p xc2vp30-ff1152-6 Custom_libera_top.ngc Custom_libera_top.ngd map -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -p xc2vp30-ff1152-6 -cm area -pr b -k 4 -c 100 -tx off -o Custom_libera_top_map.ncd Custom_libera_top.ngd Custom_libera_top.pcf par -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -w -intstyle ise -ol std -t 1 Custom_libera_top_map.ncd Custom_libera_top.ncd Custom_libera_top.pcf trce -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -e 3 -l 3 -s 6 -xml Custom_libera_top Custom_libera_top.ncd -o Custom_libera_top.twr Custom_libera_top.pcf bitgen -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -f Custom_libera_top.ut Custom_libera_top.ncd xst -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -ifn Custom_libera_top.xst -ofn Custom_libera_top.syr ngdbuild -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -dd _ngo -nt timestamp -uc Custom_Libera.ucf -p xc2vp30-ff1152-6 Custom_libera_top.ngc Custom_libera_top.ngd map -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -p xc2vp30-ff1152-6 -cm area -pr b -k 4 -c 100 -tx off -o Custom_libera_top_map.ncd Custom_libera_top.ngd Custom_libera_top.pcf par -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -w -intstyle ise -ol std -t 1 Custom_libera_top_map.ncd Custom_libera_top.ncd Custom_libera_top.pcf trce -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -e 3 -l 3 -s 6 -xml Custom_libera_top Custom_libera_top.ncd -o Custom_libera_top.twr Custom_libera_top.pcf bitgen -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -f Custom_libera_top.ut Custom_libera_top.ncd ngdbuild -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -dd _ngo -nt timestamp -uc Custom_Libera.ucf -p xc2vp30-ff1152-6 Custom_libera_top.ngc Custom_libera_top.ngd ngdbuild -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -dd _ngo -nt timestamp -uc Custom_Libera.ucf -p xc2vp30-ff1152-6 Custom_libera_top.ngc Custom_libera_top.ngd map -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -p xc2vp30-ff1152-6 -cm area -pr b -k 4 -c 100 -tx off -o Custom_libera_top_map.ncd Custom_libera_top.ngd Custom_libera_top.pcf par -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -w -intstyle ise -ol std -t 1 Custom_libera_top_map.ncd Custom_libera_top.ncd Custom_libera_top.pcf trce -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -e 3 -l 3 -s 6 -xml Custom_libera_top Custom_libera_top.ncd -o Custom_libera_top.twr Custom_libera_top.pcf bitgen -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -f Custom_libera_top.ut Custom_libera_top.ncd xst -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -ifn Custom_libera_top.xst -ofn Custom_libera_top.syr ngdbuild -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -dd _ngo -nt timestamp -uc Custom_Libera.ucf -p xc2vp30-ff1152-6 Custom_libera_top.ngc Custom_libera_top.ngd map -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -p xc2vp30-ff1152-6 -cm area -pr b -k 4 -c 100 -tx off -o Custom_libera_top_map.ncd Custom_libera_top.ngd Custom_libera_top.pcf par -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -w -intstyle ise -ol std -t 1 Custom_libera_top_map.ncd Custom_libera_top.ncd Custom_libera_top.pcf trce -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -e 3 -l 3 -s 6 -xml Custom_libera_top Custom_libera_top.ncd -o Custom_libera_top.twr Custom_libera_top.pcf bitgen -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -f Custom_libera_top.ut Custom_libera_top.ncd xst -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -ifn Custom_libera_top.xst -ofn Custom_libera_top.syr xst -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -ifn Custom_libera_top.xst -ofn Custom_libera_top.syr xst -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -ifn Custom_libera_top.xst -ofn Custom_libera_top.syr ngdbuild -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -dd _ngo -nt timestamp -uc Custom_Libera.ucf -p xc2vp30-ff1152-6 Custom_libera_top.ngc Custom_libera_top.ngd ngdbuild -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -dd _ngo -nt timestamp -uc Custom_Libera.ucf -p xc2vp30-ff1152-6 Custom_libera_top.ngc Custom_libera_top.ngd map -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -p xc2vp30-ff1152-6 -cm area -pr b -k 4 -c 100 -tx off -o Custom_libera_top_map.ncd Custom_libera_top.ngd Custom_libera_top.pcf par -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -w -intstyle ise -ol std -t 1 Custom_libera_top_map.ncd Custom_libera_top.ncd Custom_libera_top.pcf trce -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -e 3 -l 3 -s 6 -xml Custom_libera_top Custom_libera_top.ncd -o Custom_libera_top.twr Custom_libera_top.pcf bitgen -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -f Custom_libera_top.ut Custom_libera_top.ncd xst -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -ifn Custom_libera_top.xst -ofn Custom_libera_top.syr ngdbuild -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -dd _ngo -nt timestamp -uc Custom_Libera.ucf -p xc2vp30-ff1152-6 Custom_libera_top.ngc Custom_libera_top.ngd map -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -p xc2vp30-ff1152-6 -cm area -pr b -k 4 -c 100 -tx off -o Custom_libera_top_map.ncd Custom_libera_top.ngd Custom_libera_top.pcf par -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -w -intstyle ise -ol std -t 1 Custom_libera_top_map.ncd Custom_libera_top.ncd Custom_libera_top.pcf trce -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -e 3 -l 3 -s 6 -xml Custom_libera_top Custom_libera_top.ncd -o Custom_libera_top.twr Custom_libera_top.pcf bitgen -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -f Custom_libera_top.ut Custom_libera_top.ncd xst -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -ifn Custom_libera_top.xst -ofn Custom_libera_top.syr ngdbuild -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -dd _ngo -nt timestamp -uc Custom_Libera.ucf -p xc2vp30-ff1152-6 Custom_libera_top.ngc Custom_libera_top.ngd map -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -p xc2vp30-ff1152-6 -cm area -pr b -k 4 -c 100 -tx off -o Custom_libera_top_map.ncd Custom_libera_top.ngd Custom_libera_top.pcf par -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -w -intstyle ise -ol std -t 1 Custom_libera_top_map.ncd Custom_libera_top.ncd Custom_libera_top.pcf trce -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -e 3 -l 3 -s 6 -xml Custom_libera_top Custom_libera_top.ncd -o Custom_libera_top.twr Custom_libera_top.pcf bitgen -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -f Custom_libera_top.ut Custom_libera_top.ncd xst -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -ifn Custom_libera_top.xst -ofn Custom_libera_top.syr xst -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -ifn Custom_libera_top.xst -ofn Custom_libera_top.syr xst -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -ifn Custom_libera_top.xst -ofn Custom_libera_top.syr ngdbuild -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -dd _ngo -nt timestamp -uc Custom_Libera.ucf -p xc2vp30-ff1152-6 Custom_libera_top.ngc Custom_libera_top.ngd ngdbuild -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -dd _ngo -nt timestamp -uc Custom_Libera.ucf -p xc2vp30-ff1152-6 Custom_libera_top.ngc Custom_libera_top.ngd xst -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -ifn Custom_libera_top.xst -ofn Custom_libera_top.syr ngdbuild -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -dd _ngo -nt timestamp -uc Custom_Libera.ucf -p xc2vp30-ff1152-6 Custom_libera_top.ngc Custom_libera_top.ngd ngdbuild -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -dd _ngo -nt timestamp -uc Custom_Libera.ucf -p xc2vp30-ff1152-6 Custom_libera_top.ngc Custom_libera_top.ngd ngdbuild -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -dd _ngo -nt timestamp -uc Custom_Libera.ucf -p xc2vp30-ff1152-6 Custom_libera_top.ngc Custom_libera_top.ngd ngdbuild -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -dd _ngo -nt timestamp -uc Custom_Libera.ucf -p xc2vp30-ff1152-6 Custom_libera_top.ngc Custom_libera_top.ngd map -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -p xc2vp30-ff1152-6 -cm area -pr b -k 4 -c 100 -tx off -o Custom_libera_top_map.ncd Custom_libera_top.ngd Custom_libera_top.pcf par -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -w -intstyle ise -ol std -t 1 Custom_libera_top_map.ncd Custom_libera_top.ncd Custom_libera_top.pcf trce -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -e 3 -l 3 -s 6 -xml Custom_libera_top Custom_libera_top.ncd -o Custom_libera_top.twr Custom_libera_top.pcf bitgen -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -f Custom_libera_top.ut Custom_libera_top.ncd xst -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -ifn Custom_libera_top.xst -ofn Custom_libera_top.syr xst -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -ifn Custom_libera_top.xst -ofn Custom_libera_top.syr xst -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -ifn Custom_libera_top.xst -ofn Custom_libera_top.syr ngdbuild -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -dd _ngo -nt timestamp -uc Custom_Libera.ucf -p xc2vp30-ff1152-6 Custom_libera_top.ngc Custom_libera_top.ngd map -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -p xc2vp30-ff1152-6 -cm area -pr b -k 4 -c 100 -tx off -o Custom_libera_top_map.ncd Custom_libera_top.ngd Custom_libera_top.pcf par -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -w -intstyle ise -ol std -t 1 Custom_libera_top_map.ncd Custom_libera_top.ncd Custom_libera_top.pcf trce -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -e 3 -l 3 -s 6 -xml Custom_libera_top Custom_libera_top.ncd -o Custom_libera_top.twr Custom_libera_top.pcf bitgen -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -f Custom_libera_top.ut Custom_libera_top.ncd xst -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -ifn Custom_libera_top.xst -ofn Custom_libera_top.syr xst -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -ifn Custom_libera_top.xst -ofn Custom_libera_top.syr ngdbuild -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -dd _ngo -nt timestamp -uc Custom_Libera.ucf -p xc2vp30-ff1152-6 Custom_libera_top.ngc Custom_libera_top.ngd map -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -p xc2vp30-ff1152-6 -cm area -pr b -k 4 -c 100 -tx off -o Custom_libera_top_map.ncd Custom_libera_top.ngd Custom_libera_top.pcf par -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -w -intstyle ise -ol std -t 1 Custom_libera_top_map.ncd Custom_libera_top.ncd Custom_libera_top.pcf trce -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -e 3 -l 3 -s 6 -xml Custom_libera_top Custom_libera_top.ncd -o Custom_libera_top.twr Custom_libera_top.pcf bitgen -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -f Custom_libera_top.ut Custom_libera_top.ncd xst -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -ifn Custom_libera_top.xst -ofn Custom_libera_top.syr xst -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -ifn Custom_libera_top.xst -ofn Custom_libera_top.syr ngdbuild -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -dd _ngo -nt timestamp -uc Custom_Libera.ucf -p xc2vp30-ff1152-6 Custom_libera_top.ngc Custom_libera_top.ngd map -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -p xc2vp30-ff1152-6 -cm area -pr b -k 4 -c 100 -tx off -o Custom_libera_top_map.ncd Custom_libera_top.ngd Custom_libera_top.pcf par -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -w -intstyle ise -ol std -t 1 Custom_libera_top_map.ncd Custom_libera_top.ncd Custom_libera_top.pcf trce -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -e 3 -l 3 -s 6 -xml Custom_libera_top Custom_libera_top.ncd -o Custom_libera_top.twr Custom_libera_top.pcf bitgen -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -f Custom_libera_top.ut Custom_libera_top.ncd xst -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -ifn Custom_libera_top.xst -ofn Custom_libera_top.syr ngdbuild -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -dd _ngo -nt timestamp -uc Custom_Libera.ucf -p xc2vp30-ff1152-6 Custom_libera_top.ngc Custom_libera_top.ngd ngdbuild -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -dd _ngo -nt timestamp -uc Custom_Libera.ucf -p xc2vp30-ff1152-6 Custom_libera_top.ngc Custom_libera_top.ngd map -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -p xc2vp30-ff1152-6 -cm area -pr b -k 4 -c 100 -tx off -o Custom_libera_top_map.ncd Custom_libera_top.ngd Custom_libera_top.pcf par -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -w -intstyle ise -ol std -t 1 Custom_libera_top_map.ncd Custom_libera_top.ncd Custom_libera_top.pcf trce -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -e 3 -l 3 -s 6 -xml Custom_libera_top Custom_libera_top.ncd -o Custom_libera_top.twr Custom_libera_top.pcf bitgen -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -f Custom_libera_top.ut Custom_libera_top.ncd xst -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -ifn Custom_libera_top.xst -ofn Custom_libera_top.syr ngdbuild -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -dd _ngo -nt timestamp -uc Custom_Libera.ucf -p xc2vp30-ff1152-6 Custom_libera_top.ngc Custom_libera_top.ngd map -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -p xc2vp30-ff1152-6 -cm area -pr b -k 4 -c 100 -tx off -o Custom_libera_top_map.ncd Custom_libera_top.ngd Custom_libera_top.pcf par -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -w -intstyle ise -ol std -t 1 Custom_libera_top_map.ncd Custom_libera_top.ncd Custom_libera_top.pcf trce -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -e 3 -l 3 -s 6 -xml Custom_libera_top Custom_libera_top.ncd -o Custom_libera_top.twr Custom_libera_top.pcf bitgen -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -f Custom_libera_top.ut Custom_libera_top.ncd xst -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -ifn Custom_libera_top.xst -ofn Custom_libera_top.syr ngdbuild -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -dd _ngo -nt timestamp -uc Custom_Libera.ucf -p xc2vp30-ff1152-6 Custom_libera_top.ngc Custom_libera_top.ngd map -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -p xc2vp30-ff1152-6 -cm area -pr b -k 4 -c 100 -tx off -o Custom_libera_top_map.ncd Custom_libera_top.ngd Custom_libera_top.pcf par -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -w -intstyle ise -ol std -t 1 Custom_libera_top_map.ncd Custom_libera_top.ncd Custom_libera_top.pcf trce -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -e 3 -l 3 -s 6 -xml Custom_libera_top Custom_libera_top.ncd -o Custom_libera_top.twr Custom_libera_top.pcf bitgen -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -f Custom_libera_top.ut Custom_libera_top.ncd xst -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -ifn Custom_libera_top.xst -ofn Custom_libera_top.syr ngdbuild -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -dd _ngo -nt timestamp -uc Custom_Libera.ucf -p xc2vp30-ff1152-6 Custom_libera_top.ngc Custom_libera_top.ngd map -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -p xc2vp30-ff1152-6 -cm area -pr b -k 4 -c 100 -tx off -o Custom_libera_top_map.ncd Custom_libera_top.ngd Custom_libera_top.pcf par -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -w -intstyle ise -ol std -t 1 Custom_libera_top_map.ncd Custom_libera_top.ncd Custom_libera_top.pcf trce -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -e 3 -l 3 -s 6 -xml Custom_libera_top Custom_libera_top.ncd -o Custom_libera_top.twr Custom_libera_top.pcf bitgen -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -f Custom_libera_top.ut Custom_libera_top.ncd xst -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -ifn Custom_libera_top.xst -ofn Custom_libera_top.syr ngdbuild -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -dd _ngo -nt timestamp -uc Custom_Libera.ucf -p xc2vp30-ff1152-6 Custom_libera_top.ngc Custom_libera_top.ngd map -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -p xc2vp30-ff1152-6 -cm area -pr b -k 4 -c 100 -tx off -o Custom_libera_top_map.ncd Custom_libera_top.ngd Custom_libera_top.pcf par -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -w -intstyle ise -ol std -t 1 Custom_libera_top_map.ncd Custom_libera_top.ncd Custom_libera_top.pcf trce -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -e 3 -l 3 -s 6 -xml Custom_libera_top Custom_libera_top.ncd -o Custom_libera_top.twr Custom_libera_top.pcf bitgen -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -f Custom_libera_top.ut Custom_libera_top.ncd xst -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -ifn Custom_libera_top.xst -ofn Custom_libera_top.syr ngdbuild -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -dd _ngo -nt timestamp -uc Custom_Libera.ucf -p xc2vp30-ff1152-6 Custom_libera_top.ngc Custom_libera_top.ngd map -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -p xc2vp30-ff1152-6 -cm area -pr b -k 4 -c 100 -tx off -o Custom_libera_top_map.ncd Custom_libera_top.ngd Custom_libera_top.pcf par -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -w -intstyle ise -ol std -t 1 Custom_libera_top_map.ncd Custom_libera_top.ncd Custom_libera_top.pcf trce -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -e 3 -l 3 -s 6 -xml Custom_libera_top Custom_libera_top.ncd -o Custom_libera_top.twr Custom_libera_top.pcf bitgen -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -f Custom_libera_top.ut Custom_libera_top.ncd xst -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -ifn Custom_libera_top.xst -ofn Custom_libera_top.syr xst -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -ifn Custom_libera_top.xst -ofn Custom_libera_top.syr xst -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -ifn Custom_libera_top.xst -ofn Custom_libera_top.syr xst -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -ifn Custom_libera_top.xst -ofn Custom_libera_top.syr xst -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -ifn Custom_libera_top.xst -ofn Custom_libera_top.syr xst -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -ifn Custom_libera_top.xst -ofn Custom_libera_top.syr ngdbuild -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -dd _ngo -nt timestamp -i -p xc2vp30-ff1152-6 Custom_libera_top.ngc Custom_libera_top.ngd ngdbuild -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -dd _ngo -nt timestamp -i -p xc2vp30-ff1152-6 Custom_libera_top.ngc Custom_libera_top.ngd ngdbuild -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -dd _ngo -nt timestamp -i -p xc2vp30-ff1152-6 Custom_libera_top.ngc Custom_libera_top.ngd ngdbuild -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -dd _ngo -nt timestamp -i -p xc2vp30-ff1152-6 Custom_libera_top.ngc Custom_libera_top.ngd ngdbuild -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -dd _ngo -nt timestamp -i -p xc2vp30-ff1152-6 Custom_libera_top.ngc Custom_libera_top.ngd ngdbuild -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -dd _ngo -nt timestamp -i -p xc2vp30-ff1152-6 Custom_libera_top.ngc Custom_libera_top.ngd xst -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -ifn Custom_libera_top.xst -ofn Custom_libera_top.syr ngdbuild -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -dd _ngo -nt timestamp -i -p xc2vp30-ff1152-6 Custom_libera_top.ngc Custom_libera_top.ngd ngdbuild -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -dd _ngo -nt timestamp -i -p xc2vp30-ff1152-6 Custom_libera_top.ngc Custom_libera_top.ngd map -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -p xc2vp30-ff1152-6 -cm area -pr b -k 4 -c 100 -tx off -o Custom_libera_top_map.ncd Custom_libera_top.ngd Custom_libera_top.pcf par -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -w -intstyle ise -ol std -t 1 Custom_libera_top_map.ncd Custom_libera_top.ncd Custom_libera_top.pcf trce -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -e 3 -l 3 -s 6 -xml Custom_libera_top Custom_libera_top.ncd -o Custom_libera_top.twr Custom_libera_top.pcf bitgen -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -f Custom_libera_top.ut Custom_libera_top.ncd xst -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -ifn Custom_libera_top.xst -ofn Custom_libera_top.syr xst -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -ifn Custom_libera_top.xst -ofn Custom_libera_top.syr ngdbuild -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -dd _ngo -nt timestamp -uc Custom_Libera.ucf -p xc2vp30-ff1152-6 Custom_libera_top.ngc Custom_libera_top.ngd ngdbuild -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -dd _ngo -nt timestamp -uc Custom_Libera.ucf -p xc2vp30-ff1152-6 Custom_libera_top.ngc Custom_libera_top.ngd ngdbuild -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -dd _ngo -nt timestamp -uc Custom_Libera.ucf -p xc2vp30-ff1152-6 Custom_libera_top.ngc Custom_libera_top.ngd map -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -p xc2vp30-ff1152-6 -cm area -pr b -k 4 -c 100 -tx off -o Custom_libera_top_map.ncd Custom_libera_top.ngd Custom_libera_top.pcf par -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -w -intstyle ise -ol std -t 1 Custom_libera_top_map.ncd Custom_libera_top.ncd Custom_libera_top.pcf trce -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -e 3 -l 3 -s 6 -xml Custom_libera_top Custom_libera_top.ncd -o Custom_libera_top.twr Custom_libera_top.pcf bitgen -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -f Custom_libera_top.ut Custom_libera_top.ncd xst -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -ifn Custom_libera_top.xst -ofn Custom_libera_top.syr ngdbuild -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -dd _ngo -nt timestamp -uc Custom_Libera.ucf -p xc2vp30-ff1152-6 Custom_libera_top.ngc Custom_libera_top.ngd ngdbuild -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -dd _ngo -nt timestamp -uc Custom_Libera.ucf -p xc2vp30-ff1152-6 Custom_libera_top.ngc Custom_libera_top.ngd map -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -p xc2vp30-ff1152-6 -cm area -pr b -k 4 -c 100 -tx off -o Custom_libera_top_map.ncd Custom_libera_top.ngd Custom_libera_top.pcf par -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -w -intstyle ise -ol std -t 1 Custom_libera_top_map.ncd Custom_libera_top.ncd Custom_libera_top.pcf trce -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -e 3 -l 3 -s 6 -xml Custom_libera_top Custom_libera_top.ncd -o Custom_libera_top.twr Custom_libera_top.pcf bitgen -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -f Custom_libera_top.ut Custom_libera_top.ncd xst -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -ifn Custom_libera_top.xst -ofn Custom_libera_top.syr ngdbuild -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -dd _ngo -nt timestamp -uc Custom_Libera.ucf -p xc2vp30-ff1152-6 Custom_libera_top.ngc Custom_libera_top.ngd map -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -p xc2vp30-ff1152-6 -cm area -pr b -k 4 -c 100 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Custom_libera_top_map.ncd Custom_libera_top.ncd Custom_libera_top.pcf trce -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -e 3 -l 3 -s 6 -xml Custom_libera_top Custom_libera_top.ncd -o Custom_libera_top.twr Custom_libera_top.pcf bitgen -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -f Custom_libera_top.ut Custom_libera_top.ncd xst -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -ifn Custom_libera_top.xst -ofn Custom_libera_top.syr xst -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -ifn Custom_libera_top.xst -ofn Custom_libera_top.syr xst -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -ifn Custom_libera_top.xst -ofn Custom_libera_top.syr ngdbuild -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -dd _ngo -nt timestamp -uc Custom_Libera.ucf -p xc2vp30-ff1152-6 Custom_libera_top.ngc Custom_libera_top.ngd map -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -p 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"C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -p xc2vp30-ff1152-6 -cm area -pr b -k 4 -c 100 -tx off -o Custom_libera_top_map.ncd Custom_libera_top.ngd Custom_libera_top.pcf par -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -w -intstyle ise -ol std -t 1 Custom_libera_top_map.ncd Custom_libera_top.ncd Custom_libera_top.pcf trce -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -e 3 -l 3 -s 6 -xml Custom_libera_top Custom_libera_top.ncd -o Custom_libera_top.twr Custom_libera_top.pcf xst -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -ifn Custom_libera_top.xst -ofn Custom_libera_top.syr ngdbuild -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -dd _ngo -nt timestamp -uc Custom_Libera.ucf -p xc2vp30-ff1152-6 Custom_libera_top.ngc Custom_libera_top.ngd map -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -p xc2vp30-ff1152-6 -cm area -pr b -k 4 -c 100 -tx off -o Custom_libera_top_map.ncd Custom_libera_top.ngd Custom_libera_top.pcf par -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -w -intstyle ise -ol std -t 1 Custom_libera_top_map.ncd Custom_libera_top.ncd Custom_libera_top.pcf trce -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -e 3 -l 3 -s 6 -xml Custom_libera_top Custom_libera_top.ncd -o Custom_libera_top.twr Custom_libera_top.pcf bitgen -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -f Custom_libera_top.ut Custom_libera_top.ncd xst -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -ifn Custom_libera_top.xst -ofn Custom_libera_top.syr ngdbuild -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -dd _ngo -nt timestamp -uc Custom_Libera.ucf -p xc2vp30-ff1152-6 Custom_libera_top.ngc Custom_libera_top.ngd map -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -p xc2vp30-ff1152-6 -cm area -pr b -k 4 -c 100 -tx off -o Custom_libera_top_map.ncd Custom_libera_top.ngd Custom_libera_top.pcf par -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -w -intstyle ise -ol std -t 1 Custom_libera_top_map.ncd Custom_libera_top.ncd Custom_libera_top.pcf trce -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -e 3 -l 3 -s 6 -xml Custom_libera_top Custom_libera_top.ncd -o Custom_libera_top.twr Custom_libera_top.pcf bitgen -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -f Custom_libera_top.ut Custom_libera_top.ncd xst -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -ifn Custom_libera_top.xst -ofn Custom_libera_top.syr ngdbuild -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -dd _ngo -nt timestamp -uc Custom_Libera.ucf -p xc2vp30-ff1152-6 Custom_libera_top.ngc Custom_libera_top.ngd map -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -p xc2vp30-ff1152-6 -cm area -pr b -k 4 -c 100 -tx off -o Custom_libera_top_map.ncd Custom_libera_top.ngd Custom_libera_top.pcf par -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" 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"C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -ifn Custom_libera_top.xst -ofn Custom_libera_top.syr xst -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -ifn Custom_libera_top.xst -ofn Custom_libera_top.syr ngdbuild -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -dd _ngo -nt timestamp -uc Custom_Libera.ucf -p xc2vp30-ff1152-6 Custom_libera_top.ngc Custom_libera_top.ngd xst -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -ifn Custom_libera_top.xst -ofn Custom_libera_top.syr ngdbuild -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -dd _ngo -nt timestamp -uc Custom_Libera.ucf -p xc2vp30-ff1152-6 Custom_libera_top.ngc Custom_libera_top.ngd map -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -p xc2vp30-ff1152-6 -cm area -pr b -k 4 -c 100 -tx off -o Custom_libera_top_map.ncd Custom_libera_top.ngd Custom_libera_top.pcf par -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -w -intstyle ise -ol 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Custom_libera_top.ncd Custom_libera_top.pcf trce -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -e 3 -l 3 -s 6 -xml Custom_libera_top Custom_libera_top.ncd -o Custom_libera_top.twr Custom_libera_top.pcf bitgen -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -f Custom_libera_top.ut Custom_libera_top.ncd bitgen -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -f Custom_libera_top.ut Custom_libera_top.ncd xst -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -ifn Custom_libera_top.xst -ofn Custom_libera_top.syr ngdbuild -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -dd _ngo -nt timestamp -uc Custom_Libera.ucf -p xc2vp30-ff1152-6 Custom_libera_top.ngc Custom_libera_top.ngd map -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -p xc2vp30-ff1152-6 -cm area -pr b -k 4 -c 100 -tx off -o Custom_libera_top_map.ncd Custom_libera_top.ngd Custom_libera_top.pcf par -ise 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"C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -ifn Custom_libera_top.xst -ofn Custom_libera_top.syr xst -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -ifn Custom_libera_top.xst -ofn Custom_libera_top.syr xst -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -ifn Custom_libera_top.xst -ofn Custom_libera_top.syr xst -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -ifn Custom_libera_top.xst -ofn Custom_libera_top.syr xst -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -ifn Custom_libera_top.xst -ofn Custom_libera_top.syr xst -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -ifn Custom_libera_top.xst -ofn Custom_libera_top.syr xst -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -ifn Custom_libera_top.xst -ofn Custom_libera_top.syr xst -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -ifn Custom_libera_top.xst -ofn Custom_libera_top.syr xst -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -ifn Custom_libera_top.xst -ofn Custom_libera_top.syr xst -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -ifn Custom_libera_top.xst -ofn Custom_libera_top.syr xst -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -ifn Custom_libera_top.xst -ofn Custom_libera_top.syr xst -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -ifn Custom_libera_top.xst -ofn Custom_libera_top.syr xst -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -ifn Custom_libera_top.xst -ofn Custom_libera_top.syr xst -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -ifn Custom_libera_top.xst -ofn Custom_libera_top.syr netgen -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -ar Structure -tm Custom_libera_top -w -dir netgen/synthesis -ofmt vhdl -sim Custom_libera_top.ngc Custom_libera_top_synthesis.vhd ngdbuild -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -dd _ngo -nt timestamp -uc Custom_Libera.ucf -p xc2vp30-ff1152-6 Custom_libera_top.ngc Custom_libera_top.ngd xst -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -ifn Custom_libera_top.xst -ofn Custom_libera_top.syr ngdbuild -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -dd _ngo -nt timestamp -uc Custom_Libera.ucf -p xc2vp30-ff1152-6 Custom_libera_top.ngc Custom_libera_top.ngd map -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -p xc2vp30-ff1152-6 -cm speed -gf C:/DESIGNS/FPGA/Custom_Libera/Custom_libera_top_map.ncd -gm leverage -pr b -k 4 -c 100 -tx off -o Custom_libera_top_map.ncd Custom_libera_top.ngd Custom_libera_top.pcf par -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -w -intstyle ise -ol std -t 1 -gf C:/DESIGNS/FPGA/Custom_Libera/Custom_libera_top_last_par.ncd -gm leverage Custom_libera_top_map.ncd Custom_libera_top.ncd Custom_libera_top.pcf trce -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -e 3 -l 3 -s 6 -xml Custom_libera_top Custom_libera_top.ncd -o Custom_libera_top.twr Custom_libera_top.pcf netgen -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -ar Structure -tm Custom_libera_top -w -dir netgen/synthesis -ofmt vhdl -sim Custom_libera_top.ngc Custom_libera_top_synthesis.vhd xst -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -ifn Custom_libera_top.xst -ofn Custom_libera_top.syr xst -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -ifn Custom_libera_top.xst -ofn Custom_libera_top.syr xst -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -ifn Custom_libera_top.xst -ofn Custom_libera_top.syr xst -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -ifn Custom_libera_top.xst -ofn Custom_libera_top.syr ngdbuild -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -dd _ngo -nt timestamp -uc Custom_Libera.ucf -p xc2vp30-ff1152-6 Custom_libera_top.ngc Custom_libera_top.ngd map -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -p xc2vp30-ff1152-6 -cm speed -gf C:/DESIGNS/FPGA/Custom_Libera/Custom_libera_top_map.ncd -gm leverage -pr b -k 4 -c 100 -tx off -o Custom_libera_top_map.ncd Custom_libera_top.ngd Custom_libera_top.pcf par -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -w -intstyle ise -ol std -t 1 -gf C:/DESIGNS/FPGA/Custom_Libera/Custom_libera_top_last_par.ncd -gm leverage Custom_libera_top_map.ncd Custom_libera_top.ncd Custom_libera_top.pcf trce -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -e 3 -l 3 -s 6 -xml Custom_libera_top Custom_libera_top.ncd -o Custom_libera_top.twr Custom_libera_top.pcf bitgen -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -f Custom_libera_top.ut Custom_libera_top.ncd xst -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -ifn Custom_libera_top.xst -ofn Custom_libera_top.syr xst -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -ifn Custom_libera_top.xst -ofn Custom_libera_top.syr ngdbuild -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -dd _ngo -nt timestamp -uc Custom_Libera.ucf -p xc2vp30-ff1152-6 Custom_libera_top.ngc Custom_libera_top.ngd map -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -p xc2vp30-ff1152-6 -cm speed -gf C:/DESIGNS/FPGA/Custom_Libera/Custom_libera_top_map.ncd -gm leverage -pr b -k 4 -c 100 -tx off -o Custom_libera_top_map.ncd Custom_libera_top.ngd Custom_libera_top.pcf par -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -w -intstyle ise -ol std -t 1 -gf C:/DESIGNS/FPGA/Custom_Libera/Custom_libera_top_last_par.ncd -gm leverage Custom_libera_top_map.ncd Custom_libera_top.ncd Custom_libera_top.pcf trce -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -e 3 -l 3 -s 6 -xml Custom_libera_top Custom_libera_top.ncd -o Custom_libera_top.twr Custom_libera_top.pcf bitgen -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -f Custom_libera_top.ut Custom_libera_top.ncd xst -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -ifn Custom_libera_top.xst -ofn Custom_libera_top.syr ngdbuild -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -dd _ngo -nt timestamp -uc Custom_Libera.ucf -p xc2vp30-ff1152-6 Custom_libera_top.ngc Custom_libera_top.ngd map -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -p xc2vp30-ff1152-6 -cm speed -gf C:/DESIGNS/FPGA/Custom_Libera/Custom_libera_top_map.ncd -gm leverage -pr b -k 4 -c 100 -tx off -o Custom_libera_top_map.ncd Custom_libera_top.ngd Custom_libera_top.pcf par -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -w -intstyle ise -ol std -t 1 -gf C:/DESIGNS/FPGA/Custom_Libera/Custom_libera_top_last_par.ncd -gm leverage Custom_libera_top_map.ncd Custom_libera_top.ncd Custom_libera_top.pcf trce -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -e 3 -l 3 -s 6 -xml Custom_libera_top Custom_libera_top.ncd -o Custom_libera_top.twr Custom_libera_top.pcf bitgen -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -f Custom_libera_top.ut Custom_libera_top.ncd xst -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -ifn Custom_libera_top.xst -ofn Custom_libera_top.syr ngdbuild -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -dd _ngo -nt timestamp -uc Custom_Libera.ucf -p xc2vp30-ff1152-6 Custom_libera_top.ngc Custom_libera_top.ngd map -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -p xc2vp30-ff1152-6 -cm speed -gf C:/DESIGNS/FPGA/Custom_Libera/Custom_libera_top_map.ncd -gm leverage -pr b -k 4 -c 100 -tx off -o Custom_libera_top_map.ncd Custom_libera_top.ngd Custom_libera_top.pcf par -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -w -intstyle ise -ol std -t 1 -gf C:/DESIGNS/FPGA/Custom_Libera/Custom_libera_top_last_par.ncd -gm leverage Custom_libera_top_map.ncd Custom_libera_top.ncd Custom_libera_top.pcf trce -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -e 3 -l 3 -s 6 -xml Custom_libera_top Custom_libera_top.ncd -o Custom_libera_top.twr Custom_libera_top.pcf bitgen -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -f Custom_libera_top.ut Custom_libera_top.ncd xst -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -ifn Custom_libera_top.xst -ofn Custom_libera_top.syr ngdbuild -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -dd _ngo -nt timestamp -uc Custom_Libera.ucf -p xc2vp30-ff1152-6 Custom_libera_top.ngc Custom_libera_top.ngd map -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -p xc2vp30-ff1152-6 -cm speed -gf C:/DESIGNS/FPGA/Custom_Libera/Custom_libera_top_map.ncd -gm leverage -pr b -k 4 -c 100 -tx off -o Custom_libera_top_map.ncd Custom_libera_top.ngd Custom_libera_top.pcf par -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -w -intstyle ise -ol std -t 1 -gf C:/DESIGNS/FPGA/Custom_Libera/Custom_libera_top_last_par.ncd -gm leverage Custom_libera_top_map.ncd Custom_libera_top.ncd Custom_libera_top.pcf trce -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -e 3 -l 3 -s 6 -xml Custom_libera_top Custom_libera_top.ncd -o Custom_libera_top.twr Custom_libera_top.pcf bitgen -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -f Custom_libera_top.ut Custom_libera_top.ncd xst -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -ifn Custom_libera_top.xst -ofn Custom_libera_top.syr xst -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -ifn Custom_libera_top.xst -ofn Custom_libera_top.syr ngdbuild -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -dd _ngo -nt timestamp -uc Custom_Libera.ucf -p xc2vp30-ff1152-6 Custom_libera_top.ngc Custom_libera_top.ngd map -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -p xc2vp30-ff1152-6 -cm speed -gf C:/DESIGNS/FPGA/Custom_Libera/Custom_libera_top_map.ncd -gm leverage -pr b -k 4 -c 100 -tx off -o Custom_libera_top_map.ncd Custom_libera_top.ngd Custom_libera_top.pcf xst -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -ifn Custom_libera_top.xst -ofn Custom_libera_top.syr ngdbuild -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -dd _ngo -nt timestamp -uc Custom_Libera.ucf -p xc2vp30-ff1152-6 Custom_libera_top.ngc Custom_libera_top.ngd map -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -p xc2vp30-ff1152-6 -cm speed -gf C:/DESIGNS/FPGA/Custom_Libera/Custom_libera_top_map.ncd -gm leverage -pr b -k 4 -c 100 -tx off -o Custom_libera_top_map.ncd Custom_libera_top.ngd Custom_libera_top.pcf ngdbuild -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -dd _ngo -nt timestamp -uc Custom_Libera.ucf -p xc2vp30-ff1152-6 Custom_libera_top.ngc Custom_libera_top.ngd map -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -p xc2vp30-ff1152-6 -cm speed -gf C:/DESIGNS/FPGA/Custom_Libera/Custom_libera_top_map.ncd -gm leverage -pr b -k 4 -c 100 -tx off -o Custom_libera_top_map.ncd Custom_libera_top.ngd Custom_libera_top.pcf par -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -w -intstyle ise -ol std -t 1 -gf C:/DESIGNS/FPGA/Custom_Libera/Custom_libera_top_last_par.ncd -gm leverage Custom_libera_top_map.ncd Custom_libera_top.ncd Custom_libera_top.pcf trce -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -e 3 -l 3 -s 6 -xml Custom_libera_top Custom_libera_top.ncd -o Custom_libera_top.twr Custom_libera_top.pcf bitgen -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -f Custom_libera_top.ut Custom_libera_top.ncd xst -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -ifn Custom_libera_top.xst -ofn Custom_libera_top.syr xst -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -ifn Custom_libera_top.xst -ofn Custom_libera_top.syr xst -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -ifn Custom_libera_top.xst -ofn Custom_libera_top.syr ngdbuild -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -dd _ngo -nt timestamp -uc Custom_Libera.ucf -p xc2vp30-ff1152-6 Custom_libera_top.ngc Custom_libera_top.ngd map -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -p xc2vp30-ff1152-6 -cm speed -gf C:/DESIGNS/FPGA/Custom_Libera/Custom_libera_top_map.ncd -gm leverage -pr b -k 4 -c 100 -tx off -o Custom_libera_top_map.ncd Custom_libera_top.ngd Custom_libera_top.pcf par -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -w -intstyle ise -ol std -t 1 -gf C:/DESIGNS/FPGA/Custom_Libera/Custom_libera_top_last_par.ncd -gm leverage Custom_libera_top_map.ncd Custom_libera_top.ncd Custom_libera_top.pcf trce -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -e 3 -l 3 -s 6 -xml Custom_libera_top Custom_libera_top.ncd -o Custom_libera_top.twr Custom_libera_top.pcf bitgen -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -f Custom_libera_top.ut Custom_libera_top.ncd xst -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -ifn Custom_libera_top.xst -ofn Custom_libera_top.syr ngdbuild -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -dd _ngo -nt timestamp -uc Custom_Libera.ucf -p xc2vp30-ff1152-6 Custom_libera_top.ngc Custom_libera_top.ngd map -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -p xc2vp30-ff1152-6 -cm speed -gf C:/DESIGNS/FPGA/Custom_Libera/Custom_libera_top_map.ncd -gm leverage -pr b -k 4 -c 100 -tx off -o Custom_libera_top_map.ncd Custom_libera_top.ngd Custom_libera_top.pcf par -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -w -intstyle ise -ol std -t 1 -gf C:/DESIGNS/FPGA/Custom_Libera/Custom_libera_top_last_par.ncd -gm leverage Custom_libera_top_map.ncd Custom_libera_top.ncd Custom_libera_top.pcf trce -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -e 3 -l 3 -s 6 -xml Custom_libera_top Custom_libera_top.ncd -o Custom_libera_top.twr Custom_libera_top.pcf bitgen -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -f Custom_libera_top.ut Custom_libera_top.ncd xst -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -ifn Custom_libera_top.xst -ofn Custom_libera_top.syr ngdbuild -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -dd _ngo -nt timestamp -uc Custom_Libera.ucf -p xc2vp30-ff1152-6 Custom_libera_top.ngc Custom_libera_top.ngd map -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -p xc2vp30-ff1152-6 -cm speed -gf C:/DESIGNS/FPGA/Custom_Libera/Custom_libera_top_map.ncd -gm leverage -pr b -k 4 -c 100 -tx off -o Custom_libera_top_map.ncd Custom_libera_top.ngd Custom_libera_top.pcf par -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -w -intstyle ise -ol std -t 1 -gf C:/DESIGNS/FPGA/Custom_Libera/Custom_libera_top_last_par.ncd -gm leverage Custom_libera_top_map.ncd Custom_libera_top.ncd Custom_libera_top.pcf trce -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -e 3 -l 3 -s 6 -xml Custom_libera_top Custom_libera_top.ncd -o Custom_libera_top.twr Custom_libera_top.pcf bitgen -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -f Custom_libera_top.ut Custom_libera_top.ncd xst -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -ifn Custom_libera_top.xst -ofn Custom_libera_top.syr xst -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -ifn Custom_libera_top.xst -ofn Custom_libera_top.syr xst -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -ifn Custom_libera_top.xst -ofn Custom_libera_top.syr ngdbuild -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -dd _ngo -nt timestamp -uc Custom_Libera.ucf -p xc2vp30-ff1152-6 Custom_libera_top.ngc Custom_libera_top.ngd map -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -p xc2vp30-ff1152-6 -cm speed -gf C:/DESIGNS/FPGA/Custom_Libera/Custom_libera_top_map.ncd -gm leverage -pr b -k 4 -c 100 -tx off -o Custom_libera_top_map.ncd Custom_libera_top.ngd Custom_libera_top.pcf par -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -w -intstyle ise -ol std -t 1 -gf C:/DESIGNS/FPGA/Custom_Libera/Custom_libera_top_last_par.ncd -gm leverage Custom_libera_top_map.ncd Custom_libera_top.ncd Custom_libera_top.pcf trce -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -e 3 -l 3 -s 6 -xml Custom_libera_top Custom_libera_top.ncd -o Custom_libera_top.twr Custom_libera_top.pcf bitgen -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -f Custom_libera_top.ut Custom_libera_top.ncd xst -ise "E:/CERN/Custom_Libera/Custom_Libera/Custom_Libera.ise" -intstyle ise -ifn Custom_libera_top.xst -ofn Custom_libera_top.syr ngdbuild -ise "E:/CERN/Custom_Libera/Custom_Libera/Custom_Libera.ise" -intstyle ise -dd _ngo -nt timestamp -uc "Custom_Libera.ucf" -p xc2vp30-ff1152-6 "Custom_libera_top.ngc" Custom_libera_top.ngd map -ise "E:/CERN/Custom_Libera/Custom_Libera/Custom_Libera.ise" -intstyle ise -p xc2vp30-ff1152-6 -cm speed -gf "C:/DESIGNS/FPGA/Custom_Libera/Custom_libera_top_map.ncd" -gm leverage -pr b -k 4 -c 100 -tx off -o Custom_libera_top_map.ncd Custom_libera_top.ngd Custom_libera_top.pcf par -ise "E:/CERN/Custom_Libera/Custom_Libera/Custom_Libera.ise" -w -intstyle ise -ol std -t 1 -gf "C:/DESIGNS/FPGA/Custom_Libera/Custom_libera_top_last_par.ncd" -gm leverage Custom_libera_top_map.ncd Custom_libera_top.ncd Custom_libera_top.pcf ngdbuild -ise "E:/CERN/Custom_Libera/Custom_Libera/Custom_Libera.ise" -intstyle ise -dd _ngo -nt timestamp -uc "Custom_Libera.ucf" -p xc2vp30-ff1152-6 "Custom_libera_top.ngc" Custom_libera_top.ngd map -ise "E:/CERN/Custom_Libera/Custom_Libera/Custom_Libera.ise" -intstyle ise -p xc2vp30-ff1152-6 -cm speed -gf "C:/DESIGNS/FPGA/Custom_Libera/Custom_libera_top_map.ncd" -gm leverage -pr b -k 4 -c 100 -tx off -o Custom_libera_top_map.ncd Custom_libera_top.ngd Custom_libera_top.pcf par -ise "E:/CERN/Custom_Libera/Custom_Libera/Custom_Libera.ise" -w -intstyle ise -ol std -t 1 -gf "C:/DESIGNS/FPGA/Custom_Libera/Custom_libera_top_last_par.ncd" -gm leverage Custom_libera_top_map.ncd Custom_libera_top.ncd Custom_libera_top.pcf par -ise "E:/CERN/Custom_Libera/Custom_Libera/Custom_Libera.ise" -w -intstyle ise -ol std -t 1 -gf "C:/DESIGNS/FPGA/Custom_Libera/Custom_libera_top_last_par.ncd" Custom_libera_top_map.ncd Custom_libera_top.ncd Custom_libera_top.pcf par -ise "E:/CERN/Custom_Libera/Custom_Libera/Custom_Libera.ise" -w -intstyle ise -ol std -t 1 -gf "E:/CERN/Custom_Libera/Custom_Libera/Custom_libera_top_last_par.ncd" Custom_libera_top_map.ncd Custom_libera_top.ncd Custom_libera_top.pcf trce -ise "E:/CERN/Custom_Libera/Custom_Libera/Custom_Libera.ise" -intstyle ise -e 3 -l 3 -s 6 -xml Custom_libera_top Custom_libera_top.ncd -o Custom_libera_top.twr Custom_libera_top.pcf -ucf Custom_Libera.ucf bitgen -ise "E:/CERN/Custom_Libera/Custom_Libera/Custom_Libera.ise" -intstyle ise -f Custom_libera_top.ut Custom_libera_top.ncd xst -ise "E:/CERN/Custom_Libera/Custom_Libera/Custom_Libera.ise" -intstyle ise -ifn Custom_libera_top.xst -ofn Custom_libera_top.syr xst -ise "E:/CERN/Custom_Libera/Custom_Libera/Custom_Libera.ise" -intstyle ise -ifn Custom_libera_top.xst -ofn Custom_libera_top.syr ngdbuild -ise "E:/CERN/Custom_Libera/Custom_Libera/Custom_Libera.ise" -intstyle ise -dd _ngo -nt timestamp -uc "Custom_Libera.ucf" -p xc2vp30-ff1152-6 "Custom_libera_top.ngc" Custom_libera_top.ngd map -ise "E:/CERN/Custom_Libera/Custom_Libera/Custom_Libera.ise" -intstyle ise -p xc2vp30-ff1152-6 -cm speed -gf "C:/DESIGNS/FPGA/Custom_Libera/Custom_libera_top_map.ncd" -gm leverage -pr b -k 4 -c 100 -tx off -o Custom_libera_top_map.ncd Custom_libera_top.ngd Custom_libera_top.pcf map -ise "E:/CERN/Custom_Libera/Custom_Libera/Custom_Libera.ise" -intstyle ise -p xc2vp30-ff1152-6 -cm speed -gf "E:/CERN/Custom_Libera/Custom_Libera/Custom_libera_top_map.ncd" -gm leverage -pr b -k 4 -c 100 -tx off -o Custom_libera_top_map.ncd Custom_libera_top.ngd Custom_libera_top.pcf par -ise "E:/CERN/Custom_Libera/Custom_Libera/Custom_Libera.ise" -w -intstyle ise -ol std -t 1 -gf "E:/CERN/Custom_Libera/Custom_Libera/Custom_libera_top_last_par.ncd" Custom_libera_top_map.ncd Custom_libera_top.ncd Custom_libera_top.pcf trce -ise "E:/CERN/Custom_Libera/Custom_Libera/Custom_Libera.ise" -intstyle ise -e 3 -l 3 -s 6 -xml Custom_libera_top Custom_libera_top.ncd -o Custom_libera_top.twr Custom_libera_top.pcf -ucf Custom_Libera.ucf bitgen -ise "E:/CERN/Custom_Libera/Custom_Libera/Custom_Libera.ise" -intstyle ise -f Custom_libera_top.ut Custom_libera_top.ncd xst -ise "E:/CERN/Custom_Libera/Custom_Libera/Custom_Libera.ise" -intstyle ise -ifn Custom_libera_top.xst -ofn Custom_libera_top.syr ngdbuild -ise "E:/CERN/Custom_Libera/Custom_Libera/Custom_Libera.ise" -intstyle ise -dd _ngo -nt timestamp -uc "Custom_Libera.ucf" -p xc2vp30-ff1152-6 "Custom_libera_top.ngc" Custom_libera_top.ngd map -ise "E:/CERN/Custom_Libera/Custom_Libera/Custom_Libera.ise" -intstyle ise -p xc2vp30-ff1152-6 -cm speed -gf "E:/CERN/Custom_Libera/Custom_Libera/Custom_libera_top_map.ncd" -gm leverage -pr b -k 4 -c 100 -tx off -o Custom_libera_top_map.ncd Custom_libera_top.ngd Custom_libera_top.pcf par -ise "E:/CERN/Custom_Libera/Custom_Libera/Custom_Libera.ise" -w -intstyle ise -ol std -t 1 -gf "E:/CERN/Custom_Libera/Custom_Libera/Custom_libera_top_last_par.ncd" Custom_libera_top_map.ncd Custom_libera_top.ncd Custom_libera_top.pcf trce -ise "E:/CERN/Custom_Libera/Custom_Libera/Custom_Libera.ise" -intstyle ise -e 3 -l 3 -s 6 -xml Custom_libera_top Custom_libera_top.ncd -o Custom_libera_top.twr Custom_libera_top.pcf -ucf Custom_Libera.ucf bitgen -ise "E:/CERN/Custom_Libera/Custom_Libera/Custom_Libera.ise" -intstyle ise -f Custom_libera_top.ut Custom_libera_top.ncd xst -ise "E:/CERN/Custom_Libera/Custom_Libera/Custom_Libera.ise" -intstyle ise -ifn Custom_libera_top.xst -ofn Custom_libera_top.syr ngdbuild -ise "E:/CERN/Custom_Libera/Custom_Libera/Custom_Libera.ise" -intstyle ise -dd _ngo -nt timestamp -uc "Custom_Libera.ucf" -p xc2vp30-ff1152-6 "Custom_libera_top.ngc" Custom_libera_top.ngd map -ise "E:/CERN/Custom_Libera/Custom_Libera/Custom_Libera.ise" -intstyle ise -p xc2vp30-ff1152-6 -cm speed -gf "E:/CERN/Custom_Libera/Custom_Libera/Custom_libera_top_map.ncd" -gm leverage -pr b -k 4 -c 100 -tx off -o Custom_libera_top_map.ncd Custom_libera_top.ngd Custom_libera_top.pcf par -ise "E:/CERN/Custom_Libera/Custom_Libera/Custom_Libera.ise" -w -intstyle ise -ol std -t 1 -gf "E:/CERN/Custom_Libera/Custom_Libera/Custom_libera_top_last_par.ncd" Custom_libera_top_map.ncd Custom_libera_top.ncd Custom_libera_top.pcf trce -ise "E:/CERN/Custom_Libera/Custom_Libera/Custom_Libera.ise" -intstyle ise -e 3 -l 3 -s 6 -xml Custom_libera_top Custom_libera_top.ncd -o Custom_libera_top.twr Custom_libera_top.pcf -ucf Custom_Libera.ucf bitgen -ise "E:/CERN/Custom_Libera/Custom_Libera/Custom_Libera.ise" -intstyle ise -f Custom_libera_top.ut Custom_libera_top.ncd xst -ise "E:/CERN/Custom_Libera/Custom_Libera/Custom_Libera.ise" -intstyle ise -ifn Custom_libera_top.xst -ofn Custom_libera_top.syr ngdbuild -ise "E:/CERN/Custom_Libera/Custom_Libera/Custom_Libera.ise" -intstyle ise -dd _ngo -nt timestamp -uc "Custom_Libera.ucf" -p xc2vp30-ff1152-6 "Custom_libera_top.ngc" Custom_libera_top.ngd map -ise "E:/CERN/Custom_Libera/Custom_Libera/Custom_Libera.ise" -intstyle ise -p xc2vp30-ff1152-6 -cm speed -gf "E:/CERN/Custom_Libera/Custom_Libera/Custom_libera_top_map.ncd" -gm leverage -pr b -k 4 -c 100 -tx off -o Custom_libera_top_map.ncd Custom_libera_top.ngd Custom_libera_top.pcf par -ise "E:/CERN/Custom_Libera/Custom_Libera/Custom_Libera.ise" -w -intstyle ise -ol std -t 1 -gf "E:/CERN/Custom_Libera/Custom_Libera/Custom_libera_top_last_par.ncd" Custom_libera_top_map.ncd Custom_libera_top.ncd Custom_libera_top.pcf trce -ise "E:/CERN/Custom_Libera/Custom_Libera/Custom_Libera.ise" -intstyle ise -e 3 -l 3 -s 6 -xml Custom_libera_top Custom_libera_top.ncd -o Custom_libera_top.twr Custom_libera_top.pcf -ucf Custom_Libera.ucf bitgen -ise "E:/CERN/Custom_Libera/Custom_Libera/Custom_Libera.ise" -intstyle ise -f Custom_libera_top.ut Custom_libera_top.ncd xst -ise "E:/CERN/Custom_Libera/Custom_Libera/Custom_Libera.ise" -intstyle ise -ifn Custom_libera_top.xst -ofn Custom_libera_top.syr xst -ise "E:/CERN/Custom_Libera/Custom_Libera/Custom_Libera.ise" -intstyle ise -ifn Custom_libera_top.xst -ofn Custom_libera_top.syr xst -ise "E:/CERN/Custom_Libera/Custom_Libera/Custom_Libera.ise" -intstyle ise -ifn Custom_libera_top.xst -ofn Custom_libera_top.syr ngdbuild -ise "E:/CERN/Custom_Libera/Custom_Libera/Custom_Libera.ise" -intstyle ise -dd _ngo -nt timestamp -uc "Custom_Libera.ucf" -p xc2vp30-ff1152-6 "Custom_libera_top.ngc" Custom_libera_top.ngd map -ise "E:/CERN/Custom_Libera/Custom_Libera/Custom_Libera.ise" -intstyle ise -p xc2vp30-ff1152-6 -cm speed -gf "E:/CERN/Custom_Libera/Custom_Libera/Custom_libera_top_map.ncd" -gm leverage -pr b -k 4 -c 100 -tx off -o Custom_libera_top_map.ncd Custom_libera_top.ngd Custom_libera_top.pcf par -ise "E:/CERN/Custom_Libera/Custom_Libera/Custom_Libera.ise" -w -intstyle ise -ol std -t 1 -gf "E:/CERN/Custom_Libera/Custom_Libera/Custom_libera_top_last_par.ncd" Custom_libera_top_map.ncd Custom_libera_top.ncd Custom_libera_top.pcf trce -ise "E:/CERN/Custom_Libera/Custom_Libera/Custom_Libera.ise" -intstyle ise -e 3 -l 3 -s 6 -xml Custom_libera_top Custom_libera_top.ncd -o Custom_libera_top.twr Custom_libera_top.pcf -ucf Custom_Libera.ucf bitgen -ise "E:/CERN/Custom_Libera/Custom_Libera/Custom_Libera.ise" -intstyle ise -f Custom_libera_top.ut Custom_libera_top.ncd xst -ise "E:/CERN/Custom_Libera/Custom_Libera/Custom_Libera.ise" -intstyle ise -ifn Custom_libera_top.xst -ofn Custom_libera_top.syr ngdbuild -ise "E:/CERN/Custom_Libera/Custom_Libera/Custom_Libera.ise" -intstyle ise -dd _ngo -nt timestamp -uc "Custom_Libera.ucf" -p xc2vp30-ff1152-6 "Custom_libera_top.ngc" Custom_libera_top.ngd map -ise "E:/CERN/Custom_Libera/Custom_Libera/Custom_Libera.ise" -intstyle ise -p xc2vp30-ff1152-6 -cm speed -gf "E:/CERN/Custom_Libera/Custom_Libera/Custom_libera_top_map.ncd" -gm leverage -pr b -k 4 -c 100 -tx off -o Custom_libera_top_map.ncd Custom_libera_top.ngd Custom_libera_top.pcf par -ise "E:/CERN/Custom_Libera/Custom_Libera/Custom_Libera.ise" -w -intstyle ise -ol std -t 1 -gf "E:/CERN/Custom_Libera/Custom_Libera/Custom_libera_top_last_par.ncd" Custom_libera_top_map.ncd Custom_libera_top.ncd Custom_libera_top.pcf trce -ise "E:/CERN/Custom_Libera/Custom_Libera/Custom_Libera.ise" -intstyle ise -e 3 -l 3 -s 6 -xml Custom_libera_top Custom_libera_top.ncd -o Custom_libera_top.twr Custom_libera_top.pcf -ucf Custom_Libera.ucf bitgen -ise "E:/CERN/Custom_Libera/Custom_Libera/Custom_Libera.ise" -intstyle ise -f Custom_libera_top.ut Custom_libera_top.ncd xst -ise "E:/CERN/Custom_Libera/Custom_Libera/Custom_Libera.ise" -intstyle ise -ifn Custom_libera_top.xst -ofn Custom_libera_top.syr xst -ise "E:/CERN/Custom_Libera/Custom_Libera/Custom_Libera.ise" -intstyle ise -ifn Custom_libera_top.xst -ofn Custom_libera_top.syr xst -ise "E:/CERN/Custom_Libera/Custom_Libera/Custom_Libera.ise" -intstyle ise -ifn Custom_libera_top.xst -ofn Custom_libera_top.syr ngdbuild -ise "E:/CERN/Custom_Libera/Custom_Libera/Custom_Libera.ise" -intstyle ise -dd _ngo -nt timestamp -uc "Custom_Libera.ucf" -p xc2vp30-ff1152-6 "Custom_libera_top.ngc" Custom_libera_top.ngd map -ise "E:/CERN/Custom_Libera/Custom_Libera/Custom_Libera.ise" -intstyle ise -p xc2vp30-ff1152-6 -cm speed -gf "E:/CERN/Custom_Libera/Custom_Libera/Custom_libera_top_map.ncd" -gm leverage -pr b -k 4 -c 100 -tx off -o Custom_libera_top_map.ncd Custom_libera_top.ngd Custom_libera_top.pcf par -ise "E:/CERN/Custom_Libera/Custom_Libera/Custom_Libera.ise" -w -intstyle ise -ol std -t 1 -gf "E:/CERN/Custom_Libera/Custom_Libera/Custom_libera_top_last_par.ncd" Custom_libera_top_map.ncd Custom_libera_top.ncd Custom_libera_top.pcf trce -ise "E:/CERN/Custom_Libera/Custom_Libera/Custom_Libera.ise" -intstyle ise -e 3 -l 3 -s 6 -xml Custom_libera_top Custom_libera_top.ncd -o Custom_libera_top.twr Custom_libera_top.pcf -ucf Custom_Libera.ucf bitgen -ise "E:/CERN/Custom_Libera/Custom_Libera/Custom_Libera.ise" -intstyle ise -f Custom_libera_top.ut Custom_libera_top.ncd xst -ise "E:/CERN/Custom_Libera/Custom_Libera/Custom_Libera.ise" -intstyle ise -ifn Custom_libera_top.xst -ofn Custom_libera_top.syr xst -ise "E:/CERN/Custom_Libera/Custom_Libera/Custom_Libera.ise" -intstyle ise -ifn Custom_libera_top.xst -ofn Custom_libera_top.syr xst -ise "E:/CERN/Custom_Libera/Custom_Libera/Custom_Libera.ise" -intstyle ise -ifn Custom_libera_top.xst -ofn Custom_libera_top.syr xst -ise "E:/CERN/Custom_Libera/Custom_Libera/Custom_Libera.ise" -intstyle ise -ifn Custom_libera_top.xst -ofn Custom_libera_top.syr xst -ise "E:/CERN/Custom_Libera/Custom_Libera/Custom_Libera.ise" -intstyle ise -ifn Custom_libera_top.xst -ofn Custom_libera_top.syr ngdbuild -ise "E:/CERN/Custom_Libera/Custom_Libera/Custom_Libera.ise" -intstyle ise -dd _ngo -nt timestamp -uc "Custom_Libera.ucf" -p xc2vp30-ff1152-6 "Custom_libera_top.ngc" Custom_libera_top.ngd map -ise "E:/CERN/Custom_Libera/Custom_Libera/Custom_Libera.ise" -intstyle ise -p xc2vp30-ff1152-6 -cm speed -gf "E:/CERN/Custom_Libera/Custom_Libera/Custom_libera_top_map.ncd" -gm leverage -pr b -k 4 -c 100 -tx off -o Custom_libera_top_map.ncd Custom_libera_top.ngd Custom_libera_top.pcf par -ise "E:/CERN/Custom_Libera/Custom_Libera/Custom_Libera.ise" -w -intstyle ise -ol std -t 1 -gf "E:/CERN/Custom_Libera/Custom_Libera/Custom_libera_top_last_par.ncd" Custom_libera_top_map.ncd Custom_libera_top.ncd Custom_libera_top.pcf trce -ise "E:/CERN/Custom_Libera/Custom_Libera/Custom_Libera.ise" -intstyle ise -e 3 -l 3 -s 6 -xml Custom_libera_top Custom_libera_top.ncd -o Custom_libera_top.twr Custom_libera_top.pcf -ucf Custom_Libera.ucf bitgen -ise "E:/CERN/Custom_Libera/Custom_Libera/Custom_Libera.ise" -intstyle ise -f Custom_libera_top.ut Custom_libera_top.ncd ngdbuild -ise "E:/CERN/Custom_Libera/Custom_Libera/Custom_Libera.ise" -intstyle ise -dd _ngo -nt timestamp -uc "Custom_Libera.ucf" -p xc2vp30-ff1152-6 "Custom_libera_top.ngc" Custom_libera_top.ngd ngdbuild -ise "E:/CERN/Custom_Libera/Custom_Libera/Custom_Libera.ise" -intstyle ise -dd _ngo -nt timestamp -uc "Custom_Libera.ucf" -p xc2vp30-ff1152-6 "Custom_libera_top.ngc" Custom_libera_top.ngd ngdbuild -ise "E:/CERN/Custom_Libera/Custom_Libera/Custom_Libera.ise" -intstyle ise -dd _ngo -nt timestamp -uc "Custom_Libera.ucf" -p xc2vp30-ff1152-6 "Custom_libera_top.ngc" Custom_libera_top.ngd map -ise "E:/CERN/Custom_Libera/Custom_Libera/Custom_Libera.ise" -intstyle ise -p xc2vp30-ff1152-6 -cm speed -gf "E:/CERN/Custom_Libera/Custom_Libera/Custom_libera_top_map.ncd" -gm leverage -pr b -k 4 -c 100 -tx off -o Custom_libera_top_map.ncd Custom_libera_top.ngd Custom_libera_top.pcf par -ise "E:/CERN/Custom_Libera/Custom_Libera/Custom_Libera.ise" -w -intstyle ise -ol std -t 1 -gf "E:/CERN/Custom_Libera/Custom_Libera/Custom_libera_top_last_par.ncd" Custom_libera_top_map.ncd Custom_libera_top.ncd Custom_libera_top.pcf trce -ise "E:/CERN/Custom_Libera/Custom_Libera/Custom_Libera.ise" -intstyle ise -e 3 -l 3 -s 6 -xml Custom_libera_top Custom_libera_top.ncd -o Custom_libera_top.twr Custom_libera_top.pcf -ucf Custom_Libera.ucf bitgen -ise "E:/CERN/Custom_Libera/Custom_Libera/Custom_Libera.ise" -intstyle ise -f Custom_libera_top.ut Custom_libera_top.ncd xst -ise "E:/CERN/Custom_Libera/Custom_Libera/Custom_Libera.ise" -intstyle ise -ifn Custom_libera_top.xst -ofn Custom_libera_top.syr ngdbuild -ise "E:/CERN/Custom_Libera/Custom_Libera/Custom_Libera.ise" -intstyle ise -dd _ngo -nt timestamp -uc "Custom_Libera.ucf" -p xc2vp30-ff1152-6 "Custom_libera_top.ngc" Custom_libera_top.ngd map -ise "E:/CERN/Custom_Libera/Custom_Libera/Custom_Libera.ise" -intstyle ise -p xc2vp30-ff1152-6 -cm speed -gf "E:/CERN/Custom_Libera/Custom_Libera/Custom_libera_top_map.ncd" -gm leverage -pr b -k 4 -c 100 -tx off -o Custom_libera_top_map.ncd Custom_libera_top.ngd Custom_libera_top.pcf par -ise "E:/CERN/Custom_Libera/Custom_Libera/Custom_Libera.ise" -w -intstyle ise -ol std -t 1 -gf "E:/CERN/Custom_Libera/Custom_Libera/Custom_libera_top_last_par.ncd" Custom_libera_top_map.ncd Custom_libera_top.ncd Custom_libera_top.pcf trce -ise "E:/CERN/Custom_Libera/Custom_Libera/Custom_Libera.ise" -intstyle ise -e 3 -l 3 -s 6 -xml Custom_libera_top Custom_libera_top.ncd -o Custom_libera_top.twr Custom_libera_top.pcf -ucf Custom_Libera.ucf bitgen -ise "E:/CERN/Custom_Libera/Custom_Libera/Custom_Libera.ise" -intstyle ise -f Custom_libera_top.ut Custom_libera_top.ncd xst -ise "E:/CERN/Custom_Libera/Custom_Libera/Custom_Libera.ise" -intstyle ise -ifn Custom_libera_top.xst -ofn Custom_libera_top.syr xst -ise "E:/CERN/Custom_Libera/Custom_Libera/Custom_Libera.ise" -intstyle ise -ifn Custom_libera_top.xst -ofn Custom_libera_top.syr ngdbuild -ise "E:/CERN/Custom_Libera/Custom_Libera/Custom_Libera.ise" -intstyle ise -dd _ngo -nt timestamp -uc "Custom_Libera.ucf" -p xc2vp30-ff1152-6 "Custom_libera_top.ngc" Custom_libera_top.ngd map -ise "E:/CERN/Custom_Libera/Custom_Libera/Custom_Libera.ise" -intstyle ise -p xc2vp30-ff1152-6 -cm speed -gf "E:/CERN/Custom_Libera/Custom_Libera/Custom_libera_top_map.ncd" -gm leverage -pr b -k 4 -c 100 -tx off -o Custom_libera_top_map.ncd Custom_libera_top.ngd Custom_libera_top.pcf par -ise "E:/CERN/Custom_Libera/Custom_Libera/Custom_Libera.ise" -w -intstyle ise -ol std -t 1 -gf "E:/CERN/Custom_Libera/Custom_Libera/Custom_libera_top_last_par.ncd" Custom_libera_top_map.ncd Custom_libera_top.ncd Custom_libera_top.pcf trce -ise "E:/CERN/Custom_Libera/Custom_Libera/Custom_Libera.ise" -intstyle ise -e 3 -l 3 -s 6 -xml Custom_libera_top Custom_libera_top.ncd -o Custom_libera_top.twr Custom_libera_top.pcf -ucf Custom_Libera.ucf bitgen -ise "E:/CERN/Custom_Libera/Custom_Libera/Custom_Libera.ise" -intstyle ise -f Custom_libera_top.ut Custom_libera_top.ncd xst -ise "E:/CERN/Custom_Libera/Custom_Libera/Custom_Libera.ise" -intstyle ise -ifn Custom_libera_top.xst -ofn Custom_libera_top.syr ngdbuild -ise "E:/CERN/Custom_Libera/Custom_Libera/Custom_Libera.ise" -intstyle ise -dd _ngo -nt timestamp -uc "Custom_Libera.ucf" -p xc2vp30-ff1152-6 "Custom_libera_top.ngc" Custom_libera_top.ngd map -ise "E:/CERN/Custom_Libera/Custom_Libera/Custom_Libera.ise" -intstyle ise -p xc2vp30-ff1152-6 -cm speed -gf "E:/CERN/Custom_Libera/Custom_Libera/Custom_libera_top_map.ncd" -gm leverage -pr b -k 4 -c 100 -tx off -o Custom_libera_top_map.ncd Custom_libera_top.ngd Custom_libera_top.pcf par -ise "E:/CERN/Custom_Libera/Custom_Libera/Custom_Libera.ise" -w -intstyle ise -ol std -t 1 -gf "E:/CERN/Custom_Libera/Custom_Libera/Custom_libera_top_last_par.ncd" Custom_libera_top_map.ncd Custom_libera_top.ncd Custom_libera_top.pcf trce -ise "E:/CERN/Custom_Libera/Custom_Libera/Custom_Libera.ise" -intstyle ise -e 3 -l 3 -s 6 -xml Custom_libera_top Custom_libera_top.ncd -o Custom_libera_top.twr Custom_libera_top.pcf -ucf Custom_Libera.ucf bitgen -ise "E:/CERN/Custom_Libera/Custom_Libera/Custom_Libera.ise" -intstyle ise -f Custom_libera_top.ut Custom_libera_top.ncd xst -ise "E:/CERN/Custom_Libera/Custom_Libera/Custom_Libera.ise" -intstyle ise -ifn Custom_libera_top.xst -ofn Custom_libera_top.syr ngdbuild -ise "E:/CERN/Custom_Libera/Custom_Libera/Custom_Libera.ise" -intstyle ise -dd _ngo -nt timestamp -uc "Custom_Libera.ucf" -p xc2vp30-ff1152-6 "Custom_libera_top.ngc" Custom_libera_top.ngd map -ise "E:/CERN/Custom_Libera/Custom_Libera/Custom_Libera.ise" -intstyle ise -p xc2vp30-ff1152-6 -cm speed -gf "E:/CERN/Custom_Libera/Custom_Libera/Custom_libera_top_map.ncd" -gm leverage -pr b -k 4 -c 100 -tx off -o Custom_libera_top_map.ncd Custom_libera_top.ngd Custom_libera_top.pcf par -ise "E:/CERN/Custom_Libera/Custom_Libera/Custom_Libera.ise" -w -intstyle ise -ol std -t 1 -gf "E:/CERN/Custom_Libera/Custom_Libera/Custom_libera_top_last_par.ncd" Custom_libera_top_map.ncd Custom_libera_top.ncd Custom_libera_top.pcf trce -ise "E:/CERN/Custom_Libera/Custom_Libera/Custom_Libera.ise" -intstyle ise -e 3 -l 3 -s 6 -xml Custom_libera_top Custom_libera_top.ncd -o Custom_libera_top.twr Custom_libera_top.pcf -ucf Custom_Libera.ucf bitgen -ise "E:/CERN/Custom_Libera/Custom_Libera/Custom_Libera.ise" -intstyle ise -f Custom_libera_top.ut Custom_libera_top.ncd xst -ise "E:/CERN/Custom_Libera/Custom_Libera/Custom_Libera.ise" -intstyle ise -ifn Custom_libera_top.xst -ofn Custom_libera_top.syr ngdbuild -ise "E:/CERN/Custom_Libera/Custom_Libera/Custom_Libera.ise" -intstyle ise -dd _ngo -nt timestamp -uc "Custom_Libera.ucf" -p xc2vp30-ff1152-6 "Custom_libera_top.ngc" Custom_libera_top.ngd map -ise "E:/CERN/Custom_Libera/Custom_Libera/Custom_Libera.ise" -intstyle ise -p xc2vp30-ff1152-6 -cm speed -gf "E:/CERN/Custom_Libera/Custom_Libera/Custom_libera_top_map.ncd" -gm leverage -pr b -k 4 -c 100 -tx off -o Custom_libera_top_map.ncd Custom_libera_top.ngd Custom_libera_top.pcf par -ise "E:/CERN/Custom_Libera/Custom_Libera/Custom_Libera.ise" -w -intstyle ise -ol std -t 1 -gf "E:/CERN/Custom_Libera/Custom_Libera/Custom_libera_top_last_par.ncd" Custom_libera_top_map.ncd Custom_libera_top.ncd Custom_libera_top.pcf trce -ise "E:/CERN/Custom_Libera/Custom_Libera/Custom_Libera.ise" -intstyle ise -e 3 -l 3 -s 6 -xml Custom_libera_top Custom_libera_top.ncd -o Custom_libera_top.twr Custom_libera_top.pcf -ucf Custom_Libera.ucf bitgen -ise "E:/CERN/Custom_Libera/Custom_Libera/Custom_Libera.ise" -intstyle ise -f Custom_libera_top.ut Custom_libera_top.ncd ngdbuild -ise "E:/CERN/Custom_Libera/Custom_Libera/Custom_Libera.ise" -intstyle ise -dd _ngo -nt timestamp -uc "Custom_Libera.ucf" -p xc2vp30-ff1152-6 "Custom_libera_top.ngc" Custom_libera_top.ngd ngdbuild -ise "E:/CERN/Custom_Libera/Custom_Libera/Custom_Libera.ise" -intstyle ise -dd _ngo -nt timestamp -uc "Custom_Libera.ucf" -p xc2vp30-ff1152-6 "Custom_libera_top.ngc" Custom_libera_top.ngd ngdbuild -ise "E:/CERN/Custom_Libera/Custom_Libera/Custom_Libera.ise" -intstyle ise -dd _ngo -nt timestamp -uc "Custom_Libera.ucf" -p xc2vp30-ff1152-6 "Custom_libera_top.ngc" Custom_libera_top.ngd ngdbuild -ise "E:/CERN/Custom_Libera/Custom_Libera/Custom_Libera.ise" -intstyle ise -dd _ngo -nt timestamp -uc "Custom_Libera.ucf" -p xc2vp30-ff1152-6 "Custom_libera_top.ngc" Custom_libera_top.ngd ngdbuild -ise "E:/CERN/Custom_Libera/Custom_Libera/Custom_Libera.ise" -intstyle ise -dd _ngo -nt timestamp -uc "Custom_Libera.ucf" -p xc2vp30-ff1152-6 "Custom_libera_top.ngc" Custom_libera_top.ngd ngdbuild -ise "E:/CERN/Custom_Libera/Custom_Libera/Custom_Libera.ise" -intstyle ise -dd _ngo -nt timestamp -uc "Custom_Libera.ucf" -p xc2vp30-ff1152-6 "Custom_libera_top.ngc" Custom_libera_top.ngd map -ise "E:/CERN/Custom_Libera/Custom_Libera/Custom_Libera.ise" -intstyle ise -p xc2vp30-ff1152-6 -cm speed -gf "E:/CERN/Custom_Libera/Custom_Libera/Custom_libera_top_map.ncd" -gm leverage -pr b -k 4 -c 100 -tx off -o Custom_libera_top_map.ncd Custom_libera_top.ngd Custom_libera_top.pcf par -ise "E:/CERN/Custom_Libera/Custom_Libera/Custom_Libera.ise" -w -intstyle ise -ol std -t 1 -gf "E:/CERN/Custom_Libera/Custom_Libera/Custom_libera_top_last_par.ncd" Custom_libera_top_map.ncd Custom_libera_top.ncd Custom_libera_top.pcf trce -ise "E:/CERN/Custom_Libera/Custom_Libera/Custom_Libera.ise" -intstyle ise -e 3 -l 3 -s 6 -xml Custom_libera_top Custom_libera_top.ncd -o Custom_libera_top.twr Custom_libera_top.pcf -ucf Custom_Libera.ucf bitgen -ise "E:/CERN/Custom_Libera/Custom_Libera/Custom_Libera.ise" -intstyle ise -f Custom_libera_top.ut Custom_libera_top.ncd xst -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -ifn Custom_libera_top.xst -ofn Custom_libera_top.syr ngdbuild -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -dd _ngo -nt timestamp -uc Custom_Libera.ucf -p xc2vp30-ff1152-6 Custom_libera_top.ngc Custom_libera_top.ngd map -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -p xc2vp30-ff1152-6 -cm speed -gf C:/DESIGNS/FPGA/Custom_Libera/Custom_libera_top_map.ncd -gm leverage -pr b -k 4 -c 100 -tx off -o Custom_libera_top_map.ncd Custom_libera_top.ngd Custom_libera_top.pcf par -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -w -intstyle ise -ol std -t 1 -gf C:/DESIGNS/FPGA/Custom_Libera/Custom_libera_top_last_par.ncd -gm leverage Custom_libera_top_map.ncd Custom_libera_top.ncd Custom_libera_top.pcf trce -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -e 3 -l 3 -s 6 -xml Custom_libera_top Custom_libera_top.ncd -o Custom_libera_top.twr Custom_libera_top.pcf xst -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -ifn Custom_libera_top.xst -ofn Custom_libera_top.syr ngdbuild -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -dd _ngo -nt timestamp -uc Custom_Libera.ucf -p xc2vp30-ff1152-6 Custom_libera_top.ngc Custom_libera_top.ngd ngdbuild -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -dd _ngo -nt timestamp -uc Custom_Libera.ucf -p xc2vp30-ff1152-6 Custom_libera_top.ngc Custom_libera_top.ngd ngdbuild -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -dd _ngo -nt timestamp -uc Custom_Libera.ucf -p xc2vp30-ff1152-6 Custom_libera_top.ngc Custom_libera_top.ngd ngdbuild -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -dd _ngo -nt timestamp -uc Custom_Libera.ucf -p xc2vp30-ff1152-6 Custom_libera_top.ngc Custom_libera_top.ngd map -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -p xc2vp30-ff1152-6 -cm speed -gf C:/DESIGNS/FPGA/Custom_Libera/Custom_libera_top_map.ncd -gm leverage -pr b -k 4 -c 100 -tx off -o Custom_libera_top_map.ncd Custom_libera_top.ngd Custom_libera_top.pcf par -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -w -intstyle ise -ol std -t 1 -gf C:/DESIGNS/FPGA/Custom_Libera/Custom_libera_top_last_par.ncd -gm leverage Custom_libera_top_map.ncd Custom_libera_top.ncd Custom_libera_top.pcf ngdbuild -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -dd _ngo -nt timestamp -uc Custom_Libera.ucf -p xc2vp30-ff1152-6 Custom_libera_top.ngc Custom_libera_top.ngd ngdbuild -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -dd _ngo -nt timestamp -uc Custom_Libera.ucf -p xc2vp30-ff1152-6 Custom_libera_top.ngc Custom_libera_top.ngd ngdbuild -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -dd _ngo -nt timestamp -uc Custom_Libera.ucf -p xc2vp30-ff1152-6 Custom_libera_top.ngc Custom_libera_top.ngd ngdbuild -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -dd _ngo -nt timestamp -uc Custom_Libera.ucf -p xc2vp30-ff1152-6 Custom_libera_top.ngc Custom_libera_top.ngd ngdbuild -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -dd _ngo -nt timestamp -uc Custom_Libera.ucf -p xc2vp30-ff1152-6 Custom_libera_top.ngc Custom_libera_top.ngd ngdbuild -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -dd _ngo -nt timestamp -uc Custom_Libera.ucf -p xc2vp30-ff1152-6 Custom_libera_top.ngc Custom_libera_top.ngd ngdbuild -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -dd _ngo -nt timestamp -uc Custom_Libera.ucf -p xc2vp30-ff1152-6 Custom_libera_top.ngc Custom_libera_top.ngd ngdbuild -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -dd _ngo -nt timestamp -uc Custom_Libera.ucf -p xc2vp30-ff1152-6 Custom_libera_top.ngc Custom_libera_top.ngd ngdbuild -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -dd _ngo -nt timestamp -uc Custom_Libera.ucf -p xc2vp30-ff1152-6 Custom_libera_top.ngc Custom_libera_top.ngd map -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -p xc2vp30-ff1152-6 -timing -logic_opt off -ol high -t 1 -cm speed -gf C:/DESIGNS/FPGA/Custom_Libera/Custom_libera_top_map.ncd -gm leverage -pr b -k 4 -tx off -o Custom_libera_top_map.ncd Custom_libera_top.ngd Custom_libera_top.pcf ngdbuild -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -dd _ngo -nt timestamp -uc Custom_Libera.ucf -p xc2vp30-ff1152-6 Custom_libera_top.ngc Custom_libera_top.ngd ngdbuild -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -dd _ngo -nt timestamp -uc Custom_Libera.ucf -p xc2vp30-ff1152-6 Custom_libera_top.ngc Custom_libera_top.ngd ngdbuild -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -dd _ngo -nt timestamp -uc Custom_Libera.ucf -p xc2vp30-ff1152-6 Custom_libera_top.ngc Custom_libera_top.ngd ngdbuild -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -dd _ngo -nt timestamp -uc Custom_Libera.ucf -p xc2vp30-ff1152-6 Custom_libera_top.ngc Custom_libera_top.ngd xst -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -ifn Custom_libera_top.xst -ofn Custom_libera_top.syr ngdbuild -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -dd _ngo -nt timestamp -uc Custom_Libera.ucf -p xc2vp30-ff1152-6 Custom_libera_top.ngc Custom_libera_top.ngd ngdbuild -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -dd _ngo -nt timestamp -uc Custom_Libera.ucf -p xc2vp30-ff1152-6 Custom_libera_top.ngc Custom_libera_top.ngd map -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -p xc2vp30-ff1152-6 -timing -logic_opt off -ol high -t 1 -cm speed -gf C:/DESIGNS/FPGA/Custom_Libera/Custom_libera_top_map.ncd -gm leverage -pr b -k 4 -tx off -o Custom_libera_top_map.ncd Custom_libera_top.ngd Custom_libera_top.pcf map -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -p xc2vp30-ff1152-6 -timing -logic_opt off -ol std -t 1 -cm speed -gf C:/DESIGNS/FPGA/Custom_Libera/Custom_libera_top_map.ncd -gm leverage -pr b -k 4 -tx off -o Custom_libera_top_map.ncd Custom_libera_top.ngd Custom_libera_top.pcf map -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -p xc2vp30-ff1152-6 -cm speed -gf C:/DESIGNS/FPGA/Custom_Libera/Custom_libera_top_map.ncd -gm leverage -pr b -k 4 -c 100 -tx off -o Custom_libera_top_map.ncd Custom_libera_top.ngd Custom_libera_top.pcf par -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -w -intstyle ise -ol std -t 1 -gf C:/DESIGNS/FPGA/Custom_Libera/Custom_libera_top_last_par.ncd -gm leverage Custom_libera_top_map.ncd Custom_libera_top.ncd Custom_libera_top.pcf trce -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -e 3 -l 3 -s 6 -xml Custom_libera_top Custom_libera_top.ncd -o Custom_libera_top.twr Custom_libera_top.pcf bitgen -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -f Custom_libera_top.ut Custom_libera_top.ncd xst -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -ifn Custom_libera_top.xst -ofn Custom_libera_top.syr xst -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -ifn Custom_libera_top.xst -ofn Custom_libera_top.syr xst -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -ifn Custom_libera_top.xst -ofn Custom_libera_top.syr ngdbuild -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -dd _ngo -nt timestamp -uc Custom_Libera.ucf -p xc2vp30-ff1152-6 Custom_libera_top.ngc Custom_libera_top.ngd map -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -p xc2vp30-ff1152-6 -cm speed -gf C:/DESIGNS/FPGA/Custom_Libera/Custom_libera_top_map.ncd -gm leverage -pr b -k 4 -c 100 -tx off -o Custom_libera_top_map.ncd Custom_libera_top.ngd Custom_libera_top.pcf par -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -w -intstyle ise -ol std -t 1 -gf C:/DESIGNS/FPGA/Custom_Libera/Custom_libera_top_last_par.ncd -gm leverage Custom_libera_top_map.ncd Custom_libera_top.ncd Custom_libera_top.pcf trce -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -e 3 -l 3 -s 6 -xml Custom_libera_top Custom_libera_top.ncd -o Custom_libera_top.twr Custom_libera_top.pcf bitgen -ise "C:/DESIGNS/FPGA/Custom_Libera/Custom_Libera" -intstyle ise -f Custom_libera_top.ut Custom_libera_top.ncd